Chip Revision: v0.0

Known Errors

• [Reset] System Reset Triggered by RTC Watchdog Timer Cannot Be Correctly Reported
• [SAR ADC] Data Duplication May Occur When SAR ADC Accessing GDMA
• [SAR ADC] Loss of Precision in Lower Four Bits of SAR ADC
• [SPI] Enabling Flash Auto Suspend May Cause Abnormalities in Data Read
• [Wi-Fi] ESP32-C6 Cannot Be 802.11mc FTM Initiator
• [Clock] Inaccurate Calibration of RC_FAST_CLK Clock
• [CPU] Possible Deadlock Due to Out-of-Order Execution of Instructions When Writing to LP SRAM Is Involved
• [RMT] The Idle State Signal Level Might Run into Error in RMT Continuous TX Mode