# SoC Capability Macros

[中文]

Different models of ESP chips integrate various hardware modules. Even the same type of module may have subtle differences across different chips. ESP-IDF provides a small "database" to describe the differences between chips (please note, only differences are described, not commonalities). The contents of this "database" are defined as macros in the soc/soc_caps.h file, referred to as SoC capability macros. Users can utilize these macros in their code with conditional compilation directives (such as `#if`) to control which code is actually compiled.

Note

Please note that the contents of soc/soc_caps.h are currently unstable and may undergo significant changes in the future.

## Using SoC Capability Macros

We recommend accessing SoC capability macros indirectly through the following macro functions:

Macro Function | Description | Example
--- | --- | ---
`SOC_IS` | Determines the chip model | `#if SOC_IS(ESP32)` checks if the chip is ESP32
`SOC_HAS` | Checks if the chip has a specific hardware module or feature | `#if SOC_HAS(DAC)` checks if the chip has a DAC module

## API Reference

### Header File

- components/soc/esp32h4/include/soc/soc_caps.h

- This header file can be included with:

  >     #include "soc/soc_caps.h"

### Macros

_SOC_CAPS_TARGET_IS_ESP32H4

SOC_ADC_SUPPORTED

SOC_ANA_CMPR_SUPPORTED

SOC_DEDICATED_GPIO_SUPPORTED

SOC_UART_SUPPORTED

SOC_UHCI_SUPPORTED

SOC_GDMA_SUPPORTED

SOC_AHB_GDMA_SUPPORTED

SOC_GPTIMER_SUPPORTED

SOC_PCNT_SUPPORTED

SOC_MCPWM_SUPPORTED

SOC_TWAI_SUPPORTED

SOC_TWAI_FD_SUPPORTED

SOC_ETM_SUPPORTED

SOC_PARLIO_SUPPORTED

SOC_PARLIO_LCD_SUPPORTED

SOC_BT_SUPPORTED

SOC_IEEE802154_BLE_ONLY

SOC_PHY_SUPPORTED

SOC_IEEE802154_SUPPORTED

SOC_ASYNC_MEMCPY_SUPPORTED

SOC_USB_OTG_SUPPORTED

SOC_USB_SERIAL_JTAG_SUPPORTED

SOC_TEMP_SENSOR_SUPPORTED

SOC_EFUSE_KEY_PURPOSE_FIELD

SOC_EFUSE_SUPPORTED

SOC_I2S_SUPPORTED

SOC_RMT_SUPPORTED

SOC_SDM_SUPPORTED

SOC_GPSPI_SUPPORTED

SOC_LEDC_SUPPORTED

SOC_I2C_SUPPORTED

SOC_RNG_SUPPORTED

SOC_SYSTIMER_SUPPORTED

SOC_SUPPORT_COEXISTENCE

SOC_AES_SUPPORTED

SOC_SHA_SUPPORTED

SOC_HMAC_SUPPORTED

SOC_ECC_SUPPORTED

SOC_ECC_EXTENDED_MODES_SUPPORTED

SOC_FLASH_ENC_SUPPORTED

SOC_SECURE_BOOT_SUPPORTED

SOC_BOD_SUPPORTED

SOC_RISCV_TRACE_SUPPORTED

SOC_PMU_SUPPORTED

SOC_PAU_SUPPORTED

SOC_RTC_TIMER_SUPPORTED

SOC_LP_AON_SUPPORTED

SOC_TOUCH_SENSOR_SUPPORTED

SOC_REGI2C_SUPPORTED

SOC_CLK_TREE_SUPPORTED

SOC_ASSIST_DEBUG_SUPPORTED

SOC_CPU_LOCKUP_DEBUG_SUPPORTED

SOC_WDT_SUPPORTED

SOC_RTC_WDT_SUPPORTED

SOC_SPI_FLASH_SUPPORTED

SOC_SPI_EXTERNAL_NOR_FLASH_SUPPORTED

SOC_ECDSA_SUPPORTED

SOC_SPIRAM_SUPPORTED

SOC_LIGHT_SLEEP_SUPPORTED

SOC_DEEP_SLEEP_SUPPORTED

SOC_MODEM_CLOCK_SUPPORTED

SOC_PM_SUPPORTED

SOC_XTAL_SUPPORT_32M

SOC_XTAL_CLOCK_PATH_DEPENDS_ON_TOP_DOMAIN

SOC_AES_SUPPORT_DMA

SOC_AES_GDMA

SOC_AES_SUPPORT_AES_128

SOC_AES_SUPPORT_AES_256

SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION

SOC_ADC_DIG_CTRL_SUPPORTED

  < SAR ADC Module

SOC_ADC_DIG_IIR_FILTER_SUPPORTED

SOC_ADC_MONITOR_SUPPORTED

SOC_ADC_DMA_SUPPORTED

SOC_ADC_PERIPH_NUM

SOC_ADC_ATTEN_NUM

  Digital

SOC_ADC_PATT_LEN_MAX

  Two pattern tables, each contains 4 items. Each item takes 1 byte

SOC_ADC_DIGI_MIN_BITWIDTH

SOC_ADC_DIGI_MAX_BITWIDTH

SOC_ADC_DIGI_MONITOR_NUM

SOC_ADC_DIGI_RESULT_BYTES

SOC_ADC_DIGI_DATA_BYTES_PER_CONV

  Calibration

SOC_ADC_TEMPERATURE_SHARE_INTR

  < Interrupt ADC power control is shared by PWDET

SOC_ADC_SHARED_POWER

SOC_APB_BACKUP_DMA

SOC_ANA_CMPR_SUPPORT_ETM

SOC_ANA_CMPR_SUPPORT_ETM_SCAN

SOC_CACHE_WRITEBACK_SUPPORTED

SOC_CACHE_FREEZE_SUPPORTED

SOC_CPU_CORES_NUM

SOC_CPU_INTR_NUM

SOC_CPU_HAS_FLEXIBLE_INTC

SOC_INT_PLIC_SUPPORTED

SOC_INT_CLIC_SUPPORTED

SOC_INT_HW_NESTED_SUPPORTED

SOC_BRANCH_PREDICTOR_SUPPORTED

SOC_CPU_HAS_FPU

SOC_CPU_HAS_FPU_EXT_ILL_BUG

SOC_CPU_HAS_DSP

SOC_CPU_COPROC_NUM

SOC_CPU_BREAKPOINTS_NUM

SOC_CPU_WATCHPOINTS_NUM

SOC_CPU_WATCHPOINT_MAX_REGION_SIZE

SOC_CPU_HAS_PMA

SOC_CPU_IDRAM_SPLIT_USING_PMP

SOC_HP_CPU_HAS_MULTIPLE_CORES

SOC_CPU_HAS_LOCKUP_RESET

SOC_CPU_HAS_ZC_EXTENSIONS

SOC_CPU_HAS_ZB_EXTENSIONS

SOC_CPU_ZCMP_WORKAROUND

SOC_CPU_ZCMP_PUSH_REVERSED

SOC_CPU_ZCMP_POPRET_ISSUE

SOC_DMA_CAN_ACCESS_FLASH

  DMA can access Flash memory

SOC_AHB_GDMA_VERSION

SOC_GDMA_SUPPORT_ETM

SOC_GDMA_SUPPORT_SLEEP_RETENTION

SOC_MODEM_SUPPORT_ETM

SOC_GPIO_PORT

SOC_GPIO_PIN_COUNT

SOC_GPIO_IN_RANGE_MAX

SOC_GPIO_OUT_RANGE_MAX

SOC_GPIO_VALID_GPIO_MASK

SOC_GPIO_VALID_OUTPUT_GPIO_MASK

SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER

SOC_GPIO_FLEX_GLITCH_FILTER_NUM

SOC_GPIO_SUPPORT_ETM

SOC_LP_IO_CLOCK_IS_INDEPENDENT

SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP

SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP

SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK

SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED

SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK

SOC_GPIO_SUPPORT_FORCE_HOLD

SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP

SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX

SOC_CLOCKOUT_HAS_SOURCE_GATE

SOC_GPIO_CLOCKOUT_CHANNEL_NUM

SOC_RTCIO_PIN_COUNT

SOC_RTCIO_INPUT_OUTPUT_SUPPORTED

  This macro indicates that the target has separate RTC IOMUX hardware feature, so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.) when the pins are switched to RTC function.

SOC_RTCIO_HOLD_SUPPORTED

SOC_RTCIO_WAKE_SUPPORTED

SOC_SDM_SUPPORT_SLEEP_RETENTION

SOC_ETM_SUPPORT_SLEEP_RETENTION

SOC_I2C_NUM

SOC_HP_I2C_NUM

SOC_I2C_SUPPORT_XTAL

SOC_I2C_SUPPORT_RTC

SOC_I2C_SUPPORT_10BIT_ADDR

SOC_I2C_SUPPORT_SLAVE

SOC_I2C_SLAVE_SUPPORT_BROADCAST

SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE

SOC_I2C_SUPPORT_SLEEP_RETENTION

SOC_I2S_HW_VERSION_2

SOC_I2S_SUPPORTS_ETM

SOC_I2S_SUPPORTS_PCM

SOC_I2S_SUPPORTS_PDM

SOC_I2S_SUPPORTS_PDM_TX

SOC_I2S_SUPPORTS_PCM2PDM

SOC_I2S_SUPPORTS_PDM_RX

SOC_I2S_SUPPORTS_TX_SYNC_CNT

SOC_I2S_SUPPORTS_TX_FIFO_SYNC

SOC_I2S_PDM_MAX_TX_LINES

SOC_I2S_PDM_MAX_RX_LINES

SOC_I2S_SUPPORTS_TDM

SOC_LEDC_SUPPORT_PLL_DIV_CLOCK

SOC_LEDC_SUPPORT_XTAL_CLOCK

SOC_LEDC_TIMER_NUM

SOC_LEDC_CHANNEL_NUM

SOC_LEDC_TIMER_BIT_WIDTH

SOC_LEDC_SUPPORT_FADE_STOP

SOC_LEDC_FADE_PARAMS_BIT_WIDTH

SOC_LEDC_SUPPORT_SLEEP_RETENTION

SOC_LEDC_SUPPORT_ETM

SOC_MMU_PAGE_SIZE_CONFIGURABLE

SOC_MMU_PERIPH_NUM

SOC_MMU_LINEAR_ADDRESS_REGION_NUM

SOC_MMU_DI_VADDR_SHARED

  D/I vaddr are shared

SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE

SOC_PCNT_SUPPORT_CLEAR_SIGNAL

SOC_PCNT_SUPPORT_STEP_NOTIFY

SOC_RMT_MEM_WORDS_PER_CHANNEL

  Each channel owns 48 words memory (1 word = 4 Bytes)

SOC_RMT_SUPPORT_RX_PINGPONG

  Support Ping-Pong mode on RX path

SOC_RMT_SUPPORT_TX_LOOP_COUNT

  Support transmit specified number of cycles in loop mode

SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP

  Hardware support of auto-stop in loop mode

SOC_RMT_SUPPORT_SLEEP_RETENTION

  The sleep retention feature can help back up RMT registers before sleep

SOC_MCPWM_SWSYNC_CAN_PROPAGATE

  Software sync event can be routed to its output.

SOC_MCPWM_SUPPORT_ETM

  Support ETM (Event Task Matrix)

SOC_MCPWM_SUPPORT_EVENT_COMPARATOR

  Support event comparator (based on ETM)

SOC_MCPWM_CAPTURE_CLK_FROM_GROUP

  Capture timer shares clock with other PWM timers.

SOC_MCPWM_SUPPORT_SLEEP_RETENTION

  Support back up registers before sleep.

SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH

  Number of data lines of the TX unit

SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH

  Number of data lines of the RX unit

SOC_PARLIO_TX_CLK_SUPPORT_GATING

  Support gating TX clock

SOC_PARLIO_RX_CLK_SUPPORT_GATING

  Support gating RX clock

SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION

  Support loop transmission

SOC_PARLIO_SUPPORT_SLEEP_RETENTION

  Support back up registers before sleep

SOC_PARLIO_SUPPORT_I80_LCD

  Support to drive I80 interfaced LCD

SOC_SHA_DMA_MAX_BUFFER_SIZE

SOC_SHA_SUPPORT_DMA

SOC_SHA_SUPPORT_RESUME

SOC_SHA_GDMA

SOC_SHA_SUPPORT_SHA1

SOC_SHA_SUPPORT_SHA224

SOC_SHA_SUPPORT_SHA256

SOC_SHA_SUPPORT_SHA384

SOC_SHA_SUPPORT_SHA512

SOC_SHA_SUPPORT_SHA512_T

SOC_ECC_CONSTANT_TIME_POINT_MUL

SOC_ECC_SUPPORT_CURVE_P384

SOC_ECDSA_SUPPORT_EXPORT_PUBKEY

SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE

SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP

SOC_ECDSA_SUPPORT_CURVE_P384

SOC_ECDSA_SUPPORT_CURVE_SPECIFIC_KEY_PURPOSES

  Support individual key purposes for different ECDSA curves (P192, P256, P384)

SOC_SPI_PERIPH_NUM

SOC_SPI_MAXIMUM_BUFFER_SIZE

SOC_SPI_SUPPORT_SLAVE_HD_VER2

SOC_SPI_SUPPORT_SLEEP_RETENTION

SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE

SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND

SOC_SPI_MEM_SUPPORT_AUTO_RESUME

SOC_SPI_MEM_SUPPORT_IDLE_INTR

SOC_SPI_MEM_SUPPORT_SW_SUSPEND

SOC_SPI_MEM_SUPPORT_CHECK_SUS

SOC_SPI_MEM_SUPPORT_WRAP

SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR

SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP

SOC_MEMSPI_IS_INDEPENDENT

SOC_MEMSPI_ENCRYPTION_ALIGNMENT

  16-byte alignment restriction to mem addr and size if encryption is enabled

SOC_SYSTIMER_SUPPORT_ETM

SOC_LP_TIMER_BIT_WIDTH_LO

SOC_LP_TIMER_BIT_WIDTH_HI

SOC_RTC_TIMER_V2

SOC_TIMER_SUPPORT_ETM

SOC_TIMER_SUPPORT_SLEEP_RETENTION

SOC_MWDT_SUPPORT_XTAL

SOC_MWDT_SUPPORT_SLEEP_RETENTION

SOC_TWAI_CONTROLLER_NUM

SOC_TWAI_MASK_FILTER_NUM

SOC_TWAI_RANGE_FILTER_NUM

SOC_TWAI_SUPPORT_SLEEP_RETENTION

SOC_EFUSE_DIS_DOWNLOAD_ICACHE

SOC_EFUSE_DIS_PAD_JTAG

SOC_EFUSE_DIS_USB_JTAG

SOC_EFUSE_DIS_DIRECT_BOOT

SOC_EFUSE_SOFT_DIS_JTAG

SOC_EFUSE_DIS_ICACHE

SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK

SOC_EFUSE_ECDSA_KEY

SOC_EFUSE_ECDSA_KEY_P192

SOC_EFUSE_ECDSA_KEY_P384

SOC_EFUSE_XTS_AES_KEY_128

SOC_EFUSE_XTS_AES_KEY_256

SOC_SECURE_BOOT_V2_RSA

SOC_SECURE_BOOT_V2_ECC

SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS

SOC_EFUSE_SECURE_BOOT_P384_WR_DIS

SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS

SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY

SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX

SOC_FLASH_ENCRYPTION_XTS_AES

SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS

SOC_FLASH_ENCRYPTION_XTS_AES_128

SOC_FLASH_ENCRYPTION_XTS_AES_256

SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND

SOC_APM_CTRL_FILTER_SUPPORTED

  Support for APM control filter

SOC_UART_NUM

SOC_UART_HP_NUM

SOC_UART_FIFO_LEN

  The UART hardware FIFO length

SOC_UART_BITRATE_MAX

  Max bit rate supported by UART

SOC_UART_SUPPORT_RTC_CLK

  Support RTC clock as the clock source

SOC_UART_SUPPORT_XTAL_CLK

  Support XTAL clock as the clock source

SOC_UART_SUPPORT_WAKEUP_INT

  Support UART wakeup interrupt

SOC_UART_SUPPORT_SLEEP_RETENTION

  Support back up registers before sleep

SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN

SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE

SOC_UART_WAKEUP_SUPPORT_FIFO_THRESH_MODE

SOC_UART_WAKEUP_SUPPORT_START_BIT_MODE

SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE

SOC_SPIRAM_XIP_SUPPORTED

SOC_PSRAM_DMA_CAPABLE

SOC_COEX_HW_PTI

SOC_EXTERNAL_COEX_ADVANCE

  HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS

SOC_PHY_DIG_REGS_MEM_SIZE

SOC_PM_SUPPORT_BT_WAKEUP

SOC_PM_SUPPORT_EXT1_WAKEUP

SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN

  Supports one bit per pin to configure the EXT1 trigger level

SOC_PM_SUPPORT_TOUCH_WAKEUP

SOC_PM_SUPPORT_CPU_PD

SOC_PM_SUPPORT_MODEM_PD

SOC_PM_SUPPORT_XTAL32K_PD

SOC_PM_SUPPORT_RC32K_PD

SOC_PM_SUPPORT_RC_FAST_PD

SOC_PM_SUPPORT_VDDSDIO_PD

SOC_PM_SUPPORT_TOP_PD

SOC_PM_SUPPORT_HP_AON_PD

SOC_PM_SUPPORT_MAC_BB_PD

SOC_PM_SUPPORT_RTC_PERIPH_PD

SOC_PM_SUPPORT_PMU_CLK_ICG

SOC_PM_SUPPORT_PMU_RETENTION_CLK_ICG

SOC_PM_SUPPORT_MODEM_CLOCK_DOMAIN_ICG

SOC_PM_CPU_RETENTION_BY_SW

SOC_PM_FPU_RETENTION_BY_SW

SOC_PM_MODEM_RETENTION_BY_REGDMA

SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN

SOC_PM_PAU_LINK_NUM

SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE

SOC_PM_RETENTION_MODULE_NUM

SOC_PM_TOP_DEPENDS_ON_RTC_PERIPH

SOC_PM_BBPLL_PD_IN_MODEM_STATE

SOC_PM_MODEM_LOCK_CLK_WORKAROUND

SOC_PM_FLASH_KEEP_POWER_IN_LSLP

  Keep flash on in light sleep to reduce wake latency

SOC_PM_SUPPORT_BUS_CLK_AUTO_GATE

  Support hardware auto clock gating for system bus

SOC_CLK_RC_FAST_SUPPORT_CALIBRATION

SOC_MODEM_CLOCK_IS_INDEPENDENT

SOC_RNG_CLOCK_IS_INDEPENDENT

SOC_CLK_XTAL32K_SUPPORTED

  Support to connect an external low frequency crystal

SOC_CLK_OSC_SLOW_SUPPORTED

  Support to connect an external oscillator, not a crystal

SOC_CLK_LP_FAST_SUPPORT_XTAL_D2

  Support XTAL_D2 clock as the LP_FAST clock source

SOC_RCC_IS_INDEPENDENT

  Reset and Clock Control is independent, thanks to the PCR registers

SOC_ASYNCHRONOUS_BUS_ERROR_MODE

SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC

SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL

SOC_TEMPERATURE_SENSOR_INTR_SUPPORT

SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION

SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN

SOC_TOUCH_SENSOR_VERSION

  Hardware version of touch sensor

SOC_TOUCH_MIN_CHAN_ID

  Touch minimum channel number

SOC_TOUCH_MAX_CHAN_ID

  Touch maximum channel number

SOC_TOUCH_SUPPORT_SLEEP_WAKEUP

  Touch sensor supports sleep awake

SOC_TOUCH_SUPPORT_BENCHMARK

  Touch sensor supports benchmark configuration

SOC_TOUCH_SUPPORT_WATERPROOF

  Touch sensor supports waterproof

SOC_TOUCH_SUPPORT_PROX_SENSING

  Touch sensor supports proximity sensing

SOC_TOUCH_PROXIMITY_CHANNEL_NUM

  Support touch proximity channel number.

SOC_TOUCH_SAMPLE_CFG_NUM

  The sample configurations number in total, each sampler can be used to sample on one frequency

SOC_BLE_SUPPORTED

  Support Bluetooth Low Energy hardware

SOC_BLE_MESH_SUPPORTED

  Support BLE MESH

SOC_BLE_ISO_SUPPORTED

  Support BLE ISO

SOC_BLE_AUDIO_SUPPORTED

  Support BLE Audio

SOC_ESP_NIMBLE_CONTROLLER

  Support BLE EMBEDDED controller V1

SOC_BLE_50_SUPPORTED

  Support Bluetooth 5.0

SOC_BLE_DEVICE_PRIVACY_SUPPORTED

  Support BLE device privacy mode

SOC_BLE_POWER_CONTROL_SUPPORTED

  Support Bluetooth Power Control

SOC_BLE_MULTI_CONN_OPTIMIZATION

  Support multiple connections optimization

SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED

  Support For BLE Periodic Adv Enhancements

SOC_BLE_CTE_SUPPORTED

  Support Bluetooth LE Constant Tone Extension (CTE)

SOC_BLE_SUBRATE_SUPPORTED

  Support Bluetooth LE Connection Subrating

SOC_BLE_PERIODIC_ADV_WITH_RESPONSE

  Support Bluetooth LE Periodic Advertising with Response (PAwR)

SOC_USB_OTG_PERIPH_NUM

SOC_USB_FSLS_PHY_NUM

SOC_DEBUG_HAVE_OCD_STUB_BINS

SOC_RISCV_TRACE_HAS_CONFIG_REG

  Has the encoder config register

SOC_RISCV_TRACE_AHB_CONFIGURABLE

  AHB write master is configurable

SOC_RISCV_TRACE_FILTER_SUPPORTED

  Has the filter unit

SOC_RISCV_TRACE_PRIV_WIDTH

  Bits in the privilege field (privilege_width_p)

SOC_ASRC_SUPPORTED

### Header File

- components/soc/include/soc/soc_caps_eval.h

- This header file can be included with:

  >     #include "soc/soc_caps_eval.h"

### Macros

_SOC_CAPS_EVAL(_name)

  SOC Capability evaluation helpers

  These macros provide a standardized way to query SOC capabilities without directly accessing the macros in soc_caps.h.

  The main categories of macros are:

  - SOC_IS : Check if the SOC is a specific target (e.g., SOC_IS(ESP32S3))

  - SOC_MODULE_ATTR : Get a specific attribute of a module (e.g., SOC_MODULE_ATTR(GPTIMER, NUM))

  - SOC_MODULE_SUPPORT : Check if a module supports a feature (e.g., SOC_MODULE_SUPPORT(GPTIMER, ETM))

SOC_HAS(_module)

SOC_IS(_target)

SOC_MODULE_ATTR(_module, _attr)

SOC_MODULE_SUPPORT(_module, _feat)

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