Clock Tree

[中文]

The clock subsystem of ESP32-S31 is used to source and distribute system/module clocks from a range of root clocks. The clock tree driver maintains the basic functionality of the system clock and the intricate relationship among module clocks.

This document starts with the introduction to root and module clocks. Then it covers the clock tree APIs that can be called to monitor the status of the module clocks at runtime.

Introduction

This section lists definitions of ESP32-S31's supported root clocks and module clocks. These definitions are commonly used in the driver configuration, to help select a proper source clock for the peripheral.

Root Clocks

Root clocks generate reliable clock signals. These clock signals then pass through various gates, muxes, dividers, or multipliers to become the clock sources for every functional module: the CPU core(s), Wi-Fi, Bluetooth, the RTC, and the peripherals.

ESP32-S31's root clocks are listed in soc_root_clk_t:

Internal 17.5 MHz RC Oscillator (RC_FAST)

This RC oscillator generates a about 17.5 MHz clock signal output as the RC_FAST_CLK.

The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.

External 40 MHz Crystal (XTAL)

Internal 136 kHz RC Oscillator (RC_SLOW)

This RC oscillator generates a about 136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock can be computed in runtime through calibration.

External 32 kHz Crystal - optional (XTAL32K)

The clock source for this XTAL32K_CLK is a 32 kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N pins.

XTAL32K_CLK can also be calibrated to get its exact frequency.

Typically, the frequency of the signal generated from an RC oscillator circuit is less accurate and more sensitive to the environment compared to the signal generated from a crystal. ESP32-S31 provides several clock source options for the RTC_SLOW_CLK, and it is possible to make the choice based on the requirements for system time accuracy and power consumption. For more details, please refer to RTC Timer Clock Sources.

Module Clocks

ESP32-S31's available module clocks are listed in soc_module_clk_t. Each module clock has a unique ID. You can get more information on each clock by checking the documented enum value.

API Usage

The clock tree driver provides an all-in-one API to get the frequency of the module clocks, esp_clk_tree_src_get_freq_hz(). This function allows you to obtain the clock frequency at any time by providing the clock name soc_module_clk_t and specifying the desired precision level for the returned frequency value esp_clk_tree_src_freq_precision_t.

API Reference

Header File

components/soc/esp32s31/include/soc/clk_tree_defs.h
This header file can be included with:
#include "soc/clk_tree_defs.h"

Macros

SOC_CLK_RC_FAST_FREQ_APPROX: Approximate RC_FAST_CLK frequency in Hz

SOC_CLK_RC_SLOW_FREQ_APPROX: Approximate RC_SLOW_CLK frequency in Hz

SOC_CLK_XTAL32K_FREQ_APPROX: Approximate XTAL32K_CLK frequency in Hz

SOC_LCD_CLKS: Array initializer for all supported clock sources of LCD.

SOC_CAM_CLKS: Array initializer for all supported clock sources of CAM.

SOC_GPTIMER_CLKS

Array initializer for all supported clock sources of GPTimer.

The following code can be used to iterate all possible clocks:

soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
    soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
// Test GPTimer with the clock `clk`
}

SOC_RMT_CLKS: Array initializer for all supported clock sources of RMT.

SOC_UART_CLKS: Array initializer for all supported clock sources of UART.

SOC_LP_UART_CLKS: Array initializer for all supported clock sources of LP_UART.

SOC_LEDC_CLKS: Array initializer for all supported clock sources of LEDC.

SOC_LEDC_CLK_STRS

SOC_I2C_CLKS: Array initializer for all supported clock sources of I2C.

SOC_LP_I2C_CLKS: Array initializer for all supported clock sources of LP_I2C.

SOC_SDMMC_CLKS: Array initializer for all supported clock sources of SDMMC.

SOC_SPI_CLKS: Array initializer for all supported clock sources of SPI.

SOC_PSRAM_CLKS: Array initializer for all supported clock sources of PSRAM.

SOC_FLASH_CLKS: Array initializer for all supported clock sources of FLASH.

SOC_MWDT_CLKS: Array initializer for all supported clock sources of MWDT.

SOC_ANA_CMPR_CLKS: Array initializer for all supported clock sources of Analog Comparator.

SOC_TWAI_CLKS: Array initializer for all supported clock sources of TWAI.

SOC_MCPWM_TIMER_CLKS: Array initializer for all supported clock sources of MCPWM Timer.

SOC_MCPWM_CAPTURE_CLKS: Array initializer for all supported clock sources of MCPWM Capture Timer.

SOC_MCPWM_CARRIER_CLKS: Array initializer for all supported clock sources of MCPWM Carrier.

SOC_I2S_CLKS: I2S clock source.

SOC_PARLIO_CLKS: Array initializer for all supported clock sources of PARLIO.

SOC_CORDIC_CLKS: Array initializer for all supported clock sources of CORDIC.

SOC_PCNT_CLKS: Array initializer for all supported clock sources of PCNT.

SOC_ADC_DIGI_CLKS: Array initializer for all supported clock sources of ADC.

SOC_TEMP_SENSOR_CLKS: Array initializer for all supported clock sources of Temperature Sensor.

Enumerations

enum soc_root_clk_t

Root clock.

Values:

enumerator SOC_ROOT_CLK_INT_RC_FAST: Internal 17.5MHz RC oscillator

enumerator SOC_ROOT_CLK_INT_RC_SLOW: Internal 136kHz RC oscillator

enumerator SOC_ROOT_CLK_EXT_XTAL: External 40MHz crystal

enumerator SOC_ROOT_CLK_EXT_XTAL32K: External 32kHz crystal

enum soc_root_clk_circuit_t

ROOT clock circuit, which requires explicitly enabling the targeting circuit to use.

Values:

enumerator SOC_ROOT_CIRCUIT_CLK_BBPLL: BBPLL_CLK is the output of the BBPLL generator circuit

enumerator SOC_ROOT_CIRCUIT_CLK_CPLL: CPLL_CLK is the output of the CPLL generator circuit

enumerator SOC_ROOT_CIRCUIT_CLK_MPLL: MPLL_CLK is the output of the MPLL generator circuit

enumerator SOC_ROOT_CIRCUIT_CLK_APLL: APLL_CLK is the output of the APLL generator circuit

enum soc_cpu_clk_src_t

CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK.

Note

Enum values are matched with the register field values on purpose

Values:

enumerator SOC_CPU_CLK_SRC_XTAL: Select XTAL_CLK as CPU_CLK source

enumerator SOC_CPU_CLK_SRC_CPLL: Select CPLL_CLK as CPU_CLK source (CPLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 320MHz)

enumerator SOC_CPU_CLK_SRC_RC_FAST: Select RC_FAST_CLK as CPU_CLK source

enumerator SOC_CPU_CLK_SRC_PLL_F240M: Select PLL_F240M_CLK as CPU_CLK source (PLL_F240M_CLK is derived from BBPLL (480MHz), which is the output of the main crystal oscillator frequency multiplier)

enumerator SOC_CPU_CLK_SRC_INVALID: Invalid CPU_CLK source

enum soc_rtc_slow_clk_src_t

RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK.

Note

Enum values are matched with the register field values on purpose

Values:

enumerator SOC_RTC_SLOW_CLK_SRC_RC_SLOW: Select RC_SLOW_CLK as RTC_SLOW_CLK source

enumerator SOC_RTC_SLOW_CLK_SRC_XTAL32K: Select XTAL32K_CLK as RTC_SLOW_CLK source

enumerator SOC_RTC_SLOW_CLK_SRC_INVALID: Invalid RTC_SLOW_CLK source

enumerator SOC_RTC_SLOW_CLK_SRC_DEFAULT: RC_SLOW_CLK is the default clock source for RTC_SLOW_CLK

enum soc_rtc_fast_clk_src_t

RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK.

Note

Enum values are matched with the register field values on purpose

Values:

enumerator SOC_RTC_FAST_CLK_SRC_RC_FAST: Select RC_FAST_CLK as RTC_FAST_CLK source

enumerator SOC_RTC_FAST_CLK_SRC_XTAL: Select XTAL_CLK as RTC_FAST_CLK source

enumerator SOC_RTC_FAST_CLK_SRC_INVALID: Invalid RTC_FAST_CLK source

enumerator SOC_RTC_FAST_CLK_SRC_DEFAULT: XTAL_CLK is the default clock source for RTC_FAST_CLK

enum soc_xtal_freq_t

Possible main XTAL frequency options on the target.

Note

Enum values equal to the frequency value in MHz

Note

Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for the supported ones.

Values:

enumerator SOC_XTAL_FREQ_40M: 40MHz XTAL

enum soc_module_clk_t

Supported clock sources for modules (CPU, peripherals, RTC, etc.)

Note

enum starts from 1, to save 0 for special purpose

Values:

enumerator SOC_MOD_CLK_CPU: CPU_CLK can be sourced from XTAL, CPLL, or RC_FAST by configuring soc_cpu_clk_src_t

enumerator SOC_MOD_CLK_RTC_FAST: RTC_FAST_CLK can be sourced from XTAL, or RC_FAST by configuring soc_rtc_fast_clk_src_t

enumerator SOC_MOD_CLK_RTC_SLOW: RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC32K by configuring soc_rtc_slow_clk_src_t

enumerator SOC_MOD_CLK_PLL_F20M: PLL_F20M_CLK is derived from BBPLL (clock gating + default divider 24), its default frequency is 20MHz

enumerator SOC_MOD_CLK_PLL_F25M: PLL_F25M_CLK is derived from MPLL (clock gating + configurable divider), it will have a frequency of 25MHz

enumerator SOC_MOD_CLK_PLL_F50M: PLL_F50M_CLK is derived from MPLL (clock gating + configurable divider 10), it will have a frequency of 50MHz

enumerator SOC_MOD_CLK_PLL_F80M: PLL_F80M_CLK is derived from BBPLL (clock gating + default divider 6), its default frequency is 80MHz

enumerator SOC_MOD_CLK_PLL_F160M: PLL_F160M_CLK is derived from BBPLL (clock gating + default divider 3), its default frequency is 160MHz

enumerator SOC_MOD_CLK_PLL_F240M: PLL_F240M_CLK is derived from BBPLL (clock gating + default divider 2), its default frequency is 240MHz

enumerator SOC_MOD_CLK_CPLL: CPLL is from 40MHz XTAL oscillator frequency multipliers

enumerator SOC_MOD_CLK_BBPLL: BBPLL is from 40MHz XTAL oscillator frequency multipliers, its default frequency is 480MHz

enumerator SOC_MOD_CLK_MPLL: MPLL is from 40MHz XTAL oscillator frequency multipliers

enumerator SOC_MOD_CLK_XTAL32K: XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals

enumerator SOC_MOD_CLK_RC_FAST: RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals

enumerator SOC_MOD_CLK_XTAL: XTAL_CLK comes from the external 40MHz crystal

enumerator SOC_MOD_CLK_APLL: Audio PLL is sourced from PLL, and its frequency is configurable through APLL configuration registers

enumerator SOC_MOD_CLK_APB: APB_CLK is highly dependent on the CPU_CLK source

enumerator SOC_MOD_CLK_XTAL_D2: XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals

enumerator SOC_MOD_CLK_LP_DYN_FAST: LP_DYN_FAST can be derived from RTC_SLOW_CLK or RTC_FAST_CLK depending on the chip’s power mode: Only in LP_SLEEP mode, select RTC_SLOW_CLK as the clock source; In other non-LP_SLEEP mode, select RTC_FAST_CLK as the clock source;

enumerator SOC_MOD_CLK_LP_PERI: LP_PERI_CLK is derived from LP_DYN_FAST (configurable divider)

enumerator SOC_MOD_CLK_INVALID: Indication of the end of the available module clock sources

enum soc_periph_lcd_clk_src_t

Type of LCD clock source.

Values:

enumerator LCD_CLK_SRC_PLL160M: Select PLL_F160M as the source clock

enumerator LCD_CLK_SRC_XTAL: Select XTAL as the source clock

enumerator LCD_CLK_SRC_APLL: Select APLL as the source clock

enumerator LCD_CLK_SRC_DEFAULT: Select PLL_F160M as the default choice

enum soc_periph_cam_clk_src_t

Type of CAM clock source.

Values:

enumerator CAM_CLK_SRC_PLL160M: Select PLL_F160M as the source clock

enumerator CAM_CLK_SRC_XTAL: Select XTAL as the source clock

enumerator CAM_CLK_SRC_APLL: Select APLL as the source clock

enumerator CAM_CLK_SRC_DEFAULT: Select PLL_F160M as the default choice

enum soc_periph_systimer_clk_src_t

Type of SYSTIMER clock source.

Values:

enumerator SYSTIMER_CLK_SRC_XTAL: SYSTIMER source clock is XTAL

enumerator SYSTIMER_CLK_SRC_RC_FAST: SYSTIMER source clock is RC_FAST

enumerator SYSTIMER_CLK_SRC_DEFAULT: SYSTIMER source clock default choice is XTAL

enum soc_periph_gptimer_clk_src_t

Type of GPTimer clock source.

Values:

enumerator GPTIMER_CLK_SRC_PLL_F80M: Select PLL_F80M as the source clock

enumerator GPTIMER_CLK_SRC_RC_FAST: Select RC_FAST as the source clock

enumerator GPTIMER_CLK_SRC_XTAL: Select XTAL as the source clock

enumerator GPTIMER_CLK_SRC_DEFAULT: Select PLL_F80M as the default choice

enum soc_periph_etm_clk_src_t

Values:

enumerator ETM_CLK_SRC_PLL_F80M: Select PLL_F80M as the source clock

enumerator ETM_CLK_SRC_RC_FAST: Select RC_FAST as the source clock

enumerator ETM_CLK_SRC_XTAL: Select XTAL as the source clock

enumerator ETM_CLK_SRC_DEFAULT: Select PLL_F80M as the default choice

enum soc_periph_rmt_clk_src_t

Type of RMT clock source.

Values:

enumerator RMT_CLK_SRC_PLL_F80M: Select PLL_F80M as the source clock

enumerator RMT_CLK_SRC_RC_FAST: Select RC_FAST as the source clock

enumerator RMT_CLK_SRC_XTAL: Select XTAL as the source clock

enumerator RMT_CLK_SRC_DEFAULT: Select PLL_F80M as the default choice

enum soc_periph_uart_clk_src_legacy_t

Type of UART clock source, reserved for the legacy UART driver.

Values:

enumerator UART_SCLK_PLL_F80M: UART source clock is PLL_F80M

enumerator UART_SCLK_RTC: UART source clock is RC_FAST

enumerator UART_SCLK_XTAL: UART source clock is XTAL

enumerator UART_SCLK_DEFAULT: UART source clock default choice is PLL_F80M

enum soc_periph_lp_uart_clk_src_t

Type of LP_UART clock source.

Values:

enumerator LP_UART_SCLK_RC_FAST: LP_UART source clock is FOSC

enumerator LP_UART_SCLK_XTAL: LP_UART source clock is XTAL

enumerator LP_UART_SCLK_DEFAULT: LP_UART source clock default choice is FOSC

enum soc_periph_ledc_clk_src_legacy_t

Type of LEDC clock source, reserved for the legacy LEDC driver.

Values:

enumerator LEDC_AUTO_CLK: LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer

enumerator LEDC_USE_PLL_DIV_CLK: Select PLL_F80M clock as the source clock

enumerator LEDC_USE_RC_FAST_CLK: Select RC_FAST as the source clock

enumerator LEDC_USE_XTAL_CLK: Select XTAL as the source clock

enum soc_periph_i2c_clk_src_t

Type of I2C clock source.

Values:

enumerator I2C_CLK_SRC_XTAL: Select XTAL as the source clock

enumerator I2C_CLK_SRC_RC_FAST: Select RC_FAST as the source clock

enumerator I2C_CLK_SRC_DEFAULT: Select XTAL as the default clock choice

enum soc_periph_lp_i2c_clk_src_t

Type of LP_I2C clock source.

Values:

enumerator LP_I2C_SCLK_LP_FAST: LP_I2C source clock is RTC_FAST

enumerator LP_I2C_SCLK_XTAL: LP_I2C source clock is XTAL

enumerator LP_I2C_SCLK_DEFAULT: LP_I2C source clock default choice is RTC_FAST

enum soc_periph_sdmmc_clk_src_t

Type of SDMMC clock source.

Values:

enumerator SDMMC_CLK_SRC_DEFAULT: Select MPLL as the default choice

enumerator SDMMC_CLK_SRC_MPLL: Select MPLL as the source clock

enum soc_periph_spi_clk_src_t

Type of SPI clock source.

Values:

enumerator SPI_CLK_SRC_XTAL: Select XTAL as SPI source clock

enumerator SPI_CLK_SRC_RC_FAST: Select RC_FAST_20M as SPI source clock

enumerator SPI_CLK_SRC_BBPLL: Select BBPLL as SPI source clock

enumerator SPI_CLK_SRC_DEFAULT: Select BBPLL as default source clock

enum soc_periph_psram_clk_src_t

Type of PSRAM clock source.

Values:

enumerator PSRAM_CLK_SRC_DEFAULT: Select SOC_MOD_CLK_MPLL as PSRAM source clock

enumerator PSRAM_CLK_SRC_XTAL: Select SOC_MOD_CLK_XTAL as PSRAM source clock

enumerator PSRAM_CLK_SRC_CPLL: Select SOC_MOD_CLK_CPLL as PSRAM source clock

enumerator PSRAM_CLK_SRC_MPLL: Select SOC_MOD_CLK_MPLL as PSRAM source clock

enum soc_periph_flash_clk_src_t

Type of FLASH clock source.

Values:

enumerator FLASH_CLK_SRC_DEFAULT: Select SOC_MOD_CLK_BBPLL as FLASH source clock

enumerator FLASH_CLK_SRC_XTAL: Select SOC_MOD_CLK_XTAL as FLASH source clock

enumerator FLASH_CLK_SRC_CPLL: Select SOC_MOD_CLK_CPLL as FLASH source clock

enumerator FLASH_CLK_SRC_BBPLL: Select SOC_MOD_CLK_BBPLL as FLASH source clock

enum soc_periph_mwdt_clk_src_t

MWDT clock source.

Values:

enumerator MWDT_CLK_SRC_XTAL: Select XTAL as the source clock

enumerator MWDT_CLK_SRC_PLL_F80M: Select PLL fixed 80 MHz as the source clock

enumerator MWDT_CLK_SRC_RC_FAST: Select RTC fast as the source clock

enumerator MWDT_CLK_SRC_DEFAULT: Select XTAL 40 MHz as the default clock choice

enum soc_periph_sdm_clk_src_t

Sigma Delta Modulator clock source.

Values:

enumerator SDM_CLK_SRC_XTAL: Select XTAL clock as the source clock

enumerator SDM_CLK_SRC_PLL_F80M: Select PLL_F80M clock as the source clock

enumerator SDM_CLK_SRC_DEFAULT: Select PLL_F80M clock as the default clock choice

enum soc_periph_glitch_filter_clk_src_t

Glitch filter clock source.

Values:

enumerator GLITCH_FILTER_CLK_SRC_XTAL: Select XTAL clock as the source clock

enumerator GLITCH_FILTER_CLK_SRC_PLL_F80M: Select PLL_F80M clock as the source clock

enumerator GLITCH_FILTER_CLK_SRC_DEFAULT: Select PLL_F80M clock as the default clock choice

enum soc_periph_ana_cmpr_clk_src_t

Type of Analog Comparator clock source.

Values:

enumerator ANA_CMPR_CLK_SRC_XTAL: Select XTAL clock as the source clock

enumerator ANA_CMPR_CLK_SRC_RC_FAST: Select RC_FAST as the source clock

enumerator ANA_CMPR_CLK_SRC_PLL_F80M: Select PLL_F80M as the source clock

enumerator ANA_CMPR_CLK_SRC_DEFAULT: Select PLL_F80M as the default clock choice

enum soc_periph_twai_clk_src_t

TWAI clock source.

Values:

enumerator TWAI_CLK_SRC_XTAL: Select XTAL as the source clock

enumerator TWAI_CLK_SRC_PLL_F80M: Select PLL_F80M as the source clock

enumerator TWAI_CLK_SRC_DEFAULT: Select PLL_F80M as the default clock choice

enum soc_periph_mcpwm_timer_clk_src_t

Type of MCPWM timer clock source.

Values:

enumerator MCPWM_TIMER_CLK_SRC_XTAL: Select XTAL as the source clock

enumerator MCPWM_TIMER_CLK_SRC_RC_FAST: Select RC_FAST as the source clock

enumerator MCPWM_TIMER_CLK_SRC_PLL160M: Select PLL_F160M as the source clock

enumerator MCPWM_TIMER_CLK_SRC_DEFAULT: Select PLL_F160M as the default choice

enum soc_periph_mcpwm_capture_clk_src_t

Type of MCPWM capture clock source.

Values:

enumerator MCPWM_CAPTURE_CLK_SRC_XTAL: Select XTAL as the source clock

enumerator MCPWM_CAPTURE_CLK_SRC_RC_FAST: Select RC_FAST as the source clock

enumerator MCPWM_CAPTURE_CLK_SRC_PLL160M: Select PLL_F160M as the source clock

enumerator MCPWM_CAPTURE_CLK_SRC_DEFAULT: Select PLL_F160M as the default choice

enum soc_periph_mcpwm_carrier_clk_src_t

Type of MCPWM carrier clock source.

Values:

enumerator MCPWM_CARRIER_CLK_SRC_XTAL: Select XTAL as the source clock

enumerator MCPWM_CARRIER_CLK_SRC_RC_FAST: Select RC_FAST as the source clock

enumerator MCPWM_CARRIER_CLK_SRC_PLL160M: Select PLL_F160M as the source clock

enumerator MCPWM_CARRIER_CLK_SRC_DEFAULT: Select PLL_F160M as the default choice

enum soc_periph_i2s_clk_src_t

I2S clock source enum.

Note

Enum values are matched with the register field values on purpose

Values:

enumerator I2S_CLK_SRC_DEFAULT: Auto select maximum clock source as default source clock

enumerator I2S_CLK_SRC_XTAL: Select XTAL as the source clock

enumerator I2S_CLK_SRC_APLL: Select APLL as the source clock

enumerator I2S_CLK_SRC_RC_FAST: Select RC_FAST as the source clock

enumerator I2S_CLK_SRC_EXTERNAL: Select external clock as source clock

enum soc_periph_parlio_clk_src_t

PARLIO clock source.

Values:

enumerator PARLIO_CLK_SRC_XTAL: Select XTAL as the source clock

enumerator PARLIO_CLK_SRC_RC_FAST: Select RC_FAST as the source clock

enumerator PARLIO_CLK_SRC_PLL_F160M: Select PLL_F160M as the source clock

enumerator PARLIO_CLK_SRC_EXTERNAL: Select EXTERNAL clock as the source clock

enumerator PARLIO_CLK_SRC_DEFAULT: Select PLL_F160M as the default clock choice

enum soc_clkout_sig_id_t

Values:

enumerator CLKOUT_SIG_MPLL_500M: MPLL output at 500MHz

enumerator CLKOUT_SIG_BBPLL_480M: BBPLL output at 480MHz

enumerator CLKOUT_SIG_CPLL_300M: CPLL output at 300MHz

enumerator CLKOUT_SIG_XTAL_40M: Main crystal clock at 40MHz

enumerator CLKOUT_SIG_FOSC_20M: Fast RC oscillator ; nominally ~20MHz

enumerator CLKOUT_SIG_SOSC_600KD4: Slow RC oscillator ; ~150kHz before RTC divider path, used for RTC slow timing

enumerator CLKOUT_SIG_RC_32K: Internal ~32kHz RC oscillator output (low-precision; not recommended for applications)

enumerator CLKOUT_SIG_XTAL_32K: External 32kHz crystal clock (XTAL32K on XTAL_32K_P/N)

enumerator CLKOUT_SIG_ANA_PLL_80M: 80MHz analog PLL

enumerator CLKOUT_SIG_USB_OTGHS_PHYREF: USB OTG HS PHY reference clock output for the high-speed PHY

enumerator CLKOUT_SIG_USB_OTGHS_ULPI: USB OTG HS ULPI interface clock output

enumerator CLKOUT_SIG_MCPWM2: MCPWM 2 module clock

enumerator CLKOUT_SIG_MCPWM3: MCPWM 3 module clock

enumerator CLKOUT_SIG_CORE0_CLIC: Core 0 clock

enumerator CLKOUT_SIG_CORE1_CLIC: Core 1 clock

enumerator CLKOUT_SIG_AUDIO_PLL: Audio PLL (APLL) output; frequency set via APLL configuration registers

enumerator CLKOUT_SIG_PAD_I2S0_MCLK: I2S0 master clock

enumerator CLKOUT_SIG_PAD_I2S1_MCLK: I2S1 master clock

enumerator CLKOUT_SIG_USB_DEVICE_INTPHY: Full-speed USB device internal PHY clock

enumerator CLKOUT_SIG_PAD_UART0_SLP: UART0 sleep pad clock

enumerator CLKOUT_SIG_PAD_UART1_SLP: UART1 sleep pad clock

enumerator CLKOUT_SIG_PAD_UART2_SLP: UART2 sleep pad clock

enumerator CLKOUT_SIG_PAD_UART3_SLP: UART3 sleep pad clock

enumerator CLKOUT_SIG_USB_DEVICE_48M: USB device 48MHz functional clock output

enumerator CLKOUT_SIG_PAD_PARLIO_RX: Parallel IO (PARLIO) RX clock

enumerator CLKOUT_SIG_PAD_PARLIO_TX: Parallel IO (PARLIO) TX clock

enumerator CLKOUT_SIG_TCELL_CPU: CPU domain clock

enumerator CLKOUT_SIG_TCELL_MEM: memory subsystem clock

enumerator CLKOUT_SIG_TCELL_SYS: system bus clock

enumerator CLKOUT_SIG_TCELL_APB: APB peripheral bus clock

enumerator CLKOUT_SIG_FLASH_PLL: MSPI flash PLL

enumerator CLKOUT_SIG_FLASH_CORE: MSPI flash controller core clock

enumerator CLKOUT_SIG_PSRAM_PLL: MSPI PSRAM PLL clock

enumerator CLKOUT_SIG_PSRAM_CORE: MSPI PSRAM controller core clock

enumerator CLKOUT_SIG_ULPI_CLK_PAD_OUT: ULPI clock forwarded to pad output

enumerator CLKOUT_SIG_SDIO_SLF: SDIO slave

enumerator CLKOUT_SIG_SDIO_DRV: sdio_drv_clk_o

enumerator CLKOUT_SIG_SDIO_SAM: sdio_sam_clk_o

enumerator CLKOUT_SIG_I2C0: I2C0 peripheral module clock

enumerator CLKOUT_SIG_I2C1: I2C1 peripheral module clock

enumerator CLKOUT_SIG_I2S0_RX: I2S0 rx clock

enumerator CLKOUT_SIG_I2S0_TX: I2S0 tx clock

enumerator CLKOUT_SIG_I2S1_RX: I2S1 rx clock

enumerator CLKOUT_SIG_I2S1_TX: I2S1 tx clock

enumerator CLKOUT_SIG_LCD: LCD controller module clock

enumerator CLKOUT_SIG_UART0_SCLK: UART0 source clock

enumerator CLKOUT_SIG_UART0_FCLK: UART0 functional clock

enumerator CLKOUT_SIG_UART0_SLP: UART0 sleep clock

enumerator CLKOUT_SIG_UART1_SCLK: UART1 source clock

enumerator CLKOUT_SIG_UART1_FCLK: UART1 functional clock

enumerator CLKOUT_SIG_UART1_SLP: UART1 sleep clock

enumerator CLKOUT_SIG_UART2_SCLK: UART2 source clock

enumerator CLKOUT_SIG_UART2_FCLK: UART2 functional clock

enumerator CLKOUT_SIG_UART2_SLP: UART2 sleep clock

enumerator CLKOUT_SIG_UART3_SCLK: UART3 source clock

enumerator CLKOUT_SIG_UART3_FCLK: UART3 functional clock

enumerator CLKOUT_SIG_UART3_SLP: UART3 sleep clock

enumerator CLKOUT_SIG_CORDIC_CORE: CORDIC accelerator core clock

enumerator CLKOUT_SIG_ZERO_DET_CORE: Zero-cross / zero-detection peripheral core clock

enumerator CLKOUT_SIG_TWAI0: TWAI0 module clock

enumerator CLKOUT_SIG_TWAI1: TWAI1 module clock

enumerator CLKOUT_SIG_GPSPI2_HS: SPI2 high-speed clock

enumerator CLKOUT_SIG_GPSPI2_MST: SPI2 master functional clock

enumerator CLKOUT_SIG_GPSPI3_HS: SPI3 high-speed clock

enumerator CLKOUT_SIG_GPSPI3_MST: SPI3 master functional clock

enumerator CLKOUT_SIG_PARLIO_RX: PARLIO RX clock

enumerator CLKOUT_SIG_PARLIO_TX: PARLIO TX clock

enumerator CLKOUT_SIG_MCPWM0: MCPWM0 module clock

enumerator CLKOUT_SIG_MCPWM1: MCPWM1 module clock

enumerator CLKOUT_SIG_TIMERGRP0_T0: Timer group 0, timer 0 module clock

enumerator CLKOUT_SIG_TIMERGRP0_T1: Timer group 0, timer 1 module clock

enumerator CLKOUT_SIG_TIMERGRP0_WDT: Timer group 0 watchdog module clock

enumerator CLKOUT_SIG_TIMERGRP1_T0: Timer group 1, timer 0 module clock

enumerator CLKOUT_SIG_TIMERGRP1_T1: Timer group 1, timer 1 module clock

enumerator CLKOUT_SIG_TIMERGRP1_WDT: Timer group 1 watchdog module clock

enumerator CLKOUT_SIG_SYSTIMER: System timer module clock

enumerator CLKOUT_SIG_LEDC0: LED PWM controller instance 0 module clock

enumerator CLKOUT_SIG_RMT: RMT peripheral module clock

enumerator CLKOUT_SIG_ADC: ADC module clock

enumerator CLKOUT_SIG_ADC_SAR1: SAR_ADC1 clock

enumerator CLKOUT_SIG_ADC_SAR2: SAR_ADC2 clock

enumerator CLKOUT_SIG_ADC_SAR1_GCLK: SAR_ADC1 GCLK

enumerator CLKOUT_SIG_ADC_SAR2_GCLK: SAR_ADC2 GCLK

enumerator CLKOUT_SIG_PVT: PVT module clock

enumerator CLKOUT_SIG_PVT_PERI_GROUP1: PVT peripheral group 1 clock

enumerator CLKOUT_SIG_CRYPTO_SEC: Security / crypto accelerator module clock

enumerator CLKOUT_SIG_LEDC1: LED PWM controller instance 1 module clock

enumerator CLKOUT_SIG_IOMUX: IO MUX clock

enumerator CLKOUT_SIG_REF_50M: 50MHz reference clock

enumerator CLKOUT_SIG_REF_120M: 120MHz reference clock

enumerator CLKOUT_SIG_REF_160M: 160MHz reference clock

enumerator CLKOUT_SIG_REF_20M: 20MHz reference clock

enumerator CLKOUT_SIG_REF_240M: 240MHz reference clock

enumerator CLKOUT_SIG_REF_25M: 25MHz reference clock

enumerator CLKOUT_SIG_REF_80M: 80MHz reference clock

enumerator CLKOUT_SIG_REF_60M: 60MHz reference clock

enumerator CLKOUT_SIG_MPLL: Legacy short name; same mux as CLKOUT_SIG_MPLL_500M

enumerator CLKOUT_SIG_BBPLL: Legacy short name; same mux as CLKOUT_SIG_BBPLL_480M

enumerator CLKOUT_SIG_CPLL: Legacy short name; same mux as CLKOUT_SIG_CPLL_300M

enumerator CLKOUT_SIG_XTAL: Legacy short name; same mux as CLKOUT_SIG_XTAL_40M

enumerator CLKOUT_SIG_RC_FAST: Legacy name for RC_FAST / FOSC domain; same mux as CLKOUT_SIG_FOSC_20M

enumerator CLKOUT_SIG_RC_SLOW: Legacy name for RC_SLOW / SOSC domain; same mux as CLKOUT_SIG_SOSC_600KD4

enumerator CLKOUT_SIG_XTAL32K: Legacy short name; same mux as CLKOUT_SIG_XTAL_32K

enumerator CLKOUT_SIG_I2S0: Legacy short name; same mux as CLKOUT_SIG_PAD_I2S0_MCLK

enumerator CLKOUT_SIG_I2S1: Legacy short name; same mux as CLKOUT_SIG_PAD_I2S1_MCLK

enumerator CLKOUT_SIG_CPU: Legacy short name; same mux as CLKOUT_SIG_TCELL_CPU

enumerator CLKOUT_SIG_MEM: Legacy short name; same mux as CLKOUT_SIG_TCELL_MEM

enumerator CLKOUT_SIG_SYS: Legacy short name; same mux as CLKOUT_SIG_TCELL_SYS

enumerator CLKOUT_SIG_APB: Legacy short name; same mux as CLKOUT_SIG_TCELL_APB

enumerator CLKOUT_SIG_PLL_F80M: Legacy name; same mux as CLKOUT_SIG_REF_80M (80MHz reference tap)

enumerator CLKOUT_SIG_INVALID: Invalid mux value; channel disabled or not connected

enum soc_clk_freq_calculation_src_t

Clock frequency calculation source selection.

Values:

enumerator CLK_CAL_RTC_SLOW: Select to calculate frequency of RTC_SLOW_CLK

enumerator CLK_CAL_MPLL: Select to calculate frequency of MPLL_CLK

enumerator CLK_CAL_BBPLL: Select to calculate frequency of BBPLL_CLK

enumerator CLK_CAL_CPLL: Select to calculate frequency of CPLL_CLK

enumerator CLK_CAL_APLL: Select to calculate frequency of APLL_CLK

enumerator CLK_CAL_AHB: Select to calculate frequency of AHB_CLK

enumerator CLK_CAL_APB: Select to calculate frequency of APB_CLK

enumerator CLK_CAL_ROM: Select to calculate frequency of ROM_CLK

enumerator CLK_CAL_RC_FAST: Select to calculate frequency of RC_FAST_CLK

enumerator CLK_CAL_RC_SLOW: Select to calculate frequency of RC_SLOW_CLK

enumerator CLK_CAL_32K_XTAL: Select to calculate frequency of XTAL32K_CLK

enumerator CLK_CAL_XTAL: Select to calculate frequency of XTAL_CLK

enumerator CLK_CAL_UART0_PAD: Select to calculate frequency of UART0_PAD_CLK

enumerator CLK_CAL_CORE0: Select to calculate frequency of CORE0_CLK

enumerator CLK_CAL_CORE1: Select to calculate frequency of CORE1_CLK

enum soc_periph_cordic_clk_src_t

Values:

enumerator CORDIC_CLK_SRC_XTAL

enumerator CORDIC_CLK_SRC_PLL_F160M

enumerator CORDIC_CLK_SRC_RC_FAST

enumerator CORDIC_CLK_SRC_DEFAULT

enum soc_periph_pcnt_clk_src_t

Type of PCNT clock source.

Values:

enumerator PCNT_CLK_SRC_APB: Select APB as the source clock

enumerator PCNT_CLK_SRC_DEFAULT: Select APB as the default choice

enum soc_periph_adc_digi_clk_src_t

Values:

enumerator ADC_DIGI_CLK_SRC_RC_FAST: Select FOSC (internal RC oscillator) as ADC source clock

enumerator ADC_DIGI_CLK_SRC_XTAL: Select XTAL as ADC source clock

enumerator ADC_DIGI_CLK_SRC_DEFAULT: Select XTAL as the default clock choice

enum soc_periph_temperature_sensor_clk_src_t

Type of Temp Sensor clock source.

Values:

enumerator TEMPERATURE_SENSOR_CLK_SRC_LP_PERI: Select LP_PERI as the source clock

enumerator TEMPERATURE_SENSOR_CLK_SRC_DEFAULT: Select LP_PERI as the default choice

Header File

components/esp_hw_support/include/esp_clk_tree.h
This header file can be included with:
#include "esp_clk_tree.h"

Functions

esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision, uint32_t *freq_value)

Get frequency of module clock source.

Parameters:

clk_src -- [in] Clock source available to modules, in soc_module_clk_t
precision -- [in] Degree of precision, one of esp_clk_tree_src_freq_precision_t values This arg only applies to the clock sources that their frequencies can vary: SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_RTC_SLOW, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_RC_FAST_D256, SOC_MOD_CLK_XTAL32K For other clock sources, this field is ignored.
freq_value -- [out] Frequency of the clock source, in Hz

Returns:

ESP_OK Success
ESP_ERR_INVALID_ARG Parameter error
ESP_FAIL Calibration failed

esp_err_t esp_clk_tree_src_set_freq_hz(soc_module_clk_t clk_src, uint32_t expt_freq_value, uint32_t *ret_freq_value)

Set frequency of module clock source.

Parameters:

clk_src -- [in] Clock source available to modules, in soc_module_clk_t
expt_freq_value -- [in] Expected frequency of the clock source, in Hz
ret_freq_value -- [out] Real frequency of the clock source, in Hz

Returns:

ESP_OK Success
ESP_ERR_INVALID_ARG Parameter error
ESP_ERR_NOT_SUPPORTED Unsupported clock source

Enumerations

enum esp_clk_tree_src_freq_precision_t

Degree of precision of frequency value to be returned by esp_clk_tree_src_get_freq_hz()

Values:

enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED

enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX

enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT

enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID

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