Clock Tree

This section lists definitions of the ESP32-C2’s supported root clocks and module clocks. These definitions are commonly used in the driver configuration, to help user select a proper source clock for the peripheral.

Root Clocks

Root clocks generate reliable clock signals. These clock signals then pass through various gates, muxes, dividers, or multipliers to become the clock sources for every functional module: the CPU core(s), WIFI, BT, the RTC, and the peripherals.

ESP32-C2’s root clocks are listed in soc_root_clk_t:

• Internal 17.5MHz RC Oscillator (RC_FAST)

  This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK.

  The ~17.5MHz signal output is also passed into a configurable divider, which by default divides the input clock frequency by 256, to generate a RC_FAST_D256_CLK.

  The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK.

• External 40MHz Crystal (XTAL)

• Internal 136kHz RC Oscillator (RC_SLOW)

  This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock can be computed in runtime through calibration.

• External Slow Clock - optional (OSC_SLOW)

  A clock signal generated by an external circuit can be connected to pin0 to be the clock source for the RTC_SLOW_CLK. This clock can also be calibrated to get its exact frequency.

Typically, the frequency of the signal generated from a RC oscillator circuit is less accurate and more sensitive to environment comparing to the signal generated from a crystal. ESP32-C2 provides several clock source options for the RTC_SLOW_CLK, and users can make the choice based on the requirements for system time accuracy and power consumption (refer to RTC Timer Clock Sources for more details).

Module Clocks

ESP32-C2’s available module clocks are listed in soc_module_clk_t. Each module clock has a unique ID. You can get more information on each clock by checking the documented enum value.

API Reference

Header File

• components/soc/esp32c2/include/soc/clk_tree_defs.h

Macros

SOC_CLK_RC_FAST_FREQ_APPROX

Approximate RC_FAST_CLK frequency in Hz

SOC_CLK_RC_SLOW_FREQ_APPROX

Approximate RC_SLOW_CLK frequency in Hz

SOC_CLK_RC_FAST_D256_FREQ_APPROX

Approximate RC_FAST_D256_CLK frequency in Hz

SOC_CLK_OSC_SLOW_FREQ_APPROX

Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz

SOC_GPTIMER_CLKS

Array initializer for all supported clock sources of GPTimer.

The following code can be used to iterate all possible clocks:

soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
    soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
    // Test GPTimer with the clock `clk`
}

SOC_TEMP_SENSOR_CLKS

Array initializer for all supported clock sources of Temperature Sensor.

SOC_I2C_CLKS

Array initializer for all supported clock sources of I2C.

Enumerations

enum soc_root_clk_t

Root clock.

Values:

enumerator SOC_ROOT_CLK_INT_RC_FAST

Internal 17.5MHz RC oscillator

enumerator SOC_ROOT_CLK_INT_RC_SLOW

Internal 136kHz RC oscillator

enumerator SOC_ROOT_CLK_EXT_XTAL

External 26/40MHz crystal

enumerator SOC_ROOT_CLK_EXT_OSC_SLOW

External slow clock signal at pin0, only support 32.768 KHz currently

enum soc_cpu_clk_src_t

CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK.

Note

Enum values are matched with the register field values on purpose

Values:

enumerator SOC_CPU_CLK_SRC_XTAL

Select XTAL_CLK as CPU_CLK source

enumerator SOC_CPU_CLK_SRC_PLL

Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 26/40MHz crystal oscillator frequency multiplier, 480MHz)

enumerator SOC_CPU_CLK_SRC_RC_FAST

Select RC_FAST_CLK as CPU_CLK source

enumerator SOC_CPU_CLK_SRC_INVALID

Invalid CPU_CLK source

enum soc_rtc_slow_clk_src_t

RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK.

Note

Enum values are matched with the register field values on purpose

Values:

enumerator SOC_RTC_SLOW_CLK_SRC_RC_SLOW

Select RC_SLOW_CLK as RTC_SLOW_CLK source

enumerator SOC_RTC_SLOW_CLK_SRC_OSC_SLOW

Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source

enumerator SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256

Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source

enumerator SOC_RTC_SLOW_CLK_SRC_INVALID

Invalid RTC_SLOW_CLK source

enum soc_rtc_fast_clk_src_t

RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK.

Note

Enum values are matched with the register field values on purpose

Values:

enumerator SOC_RTC_FAST_CLK_SRC_XTAL_D2

Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source

enumerator SOC_RTC_FAST_CLK_SRC_XTAL_DIV

Alias name for SOC_RTC_FAST_CLK_SRC_XTAL_D2

enumerator SOC_RTC_FAST_CLK_SRC_RC_FAST

Select RC_FAST_CLK as RTC_FAST_CLK source

enumerator SOC_RTC_FAST_CLK_SRC_INVALID

Invalid RTC_FAST_CLK source

enum soc_module_clk_t

Supported clock sources for modules (CPU, peripherals, RTC, etc.)

Note

enum starts from 1, to save 0 for special purpose

Values:

enumerator SOC_MOD_CLK_CPU

CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t

enumerator SOC_MOD_CLK_RTC_FAST

RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t

enumerator SOC_MOD_CLK_RTC_SLOW

RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t

enumerator SOC_MOD_CLK_PLL_F40M

PLL_F40M_CLK is derived from PLL, and has a fixed frequency of 40MHz

enumerator SOC_MOD_CLK_PLL_F60M

PLL_F60M_CLK is derived from PLL, and has a fixed frequency of 60MHz

enumerator SOC_MOD_CLK_PLL_F80M

PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz

enumerator SOC_MOD_CLK_OSC_SLOW

OSC_SLOW_CLK comes from an external slow clock signal, passing a clock gating to the peripherals

enumerator SOC_MOD_CLK_RC_FAST

RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals

enumerator SOC_MOD_CLK_RC_FAST_D256

RC_FAST_D256_CLK comes from the internal 20MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals

enumerator SOC_MOD_CLK_XTAL

XTAL_CLK comes from the external 26/40MHz crystal

enum soc_periph_gptimer_clk_src_t

Type of GPTimer clock source.

Values:

enumerator GPTIMER_CLK_SRC_PLL_F40M

Select PLL_F40M as the source clock

enumerator GPTIMER_CLK_SRC_XTAL

Select XTAL as the source clock

enumerator GPTIMER_CLK_SRC_DEFAULT

Select PLL_F40M as the default choice

enum soc_periph_tg_clk_src_legacy_t

Type of Timer Group clock source, reserved for the legacy timer group driver.

Values:

enumerator TIMER_SRC_CLK_PLL_F40M

Timer group clock source is PLL_F40M

enumerator TIMER_SRC_CLK_XTAL

Timer group clock source is XTAL

enumerator TIMER_SRC_CLK_DEFAULT

Timer group clock source default choice is PLL_F40M

enum soc_periph_temperature_sensor_clk_src_t

Type of Temp Sensor clock source.

Values:

enumerator TEMPERATURE_SENSOR_CLK_SRC_XTAL

Select XTAL as the source clock

enumerator TEMPERATURE_SENSOR_CLK_SRC_RC_FAST

Select RC_FAST as the source clock

enumerator TEMPERATURE_SENSOR_CLK_SRC_DEFAULT

Select XTAL as the default choice

enum soc_periph_uart_clk_src_legacy_t

Type of UART clock source, reserved for the legacy UART driver.

Values:

enumerator UART_SCLK_PLL_F40M

UART source clock is APB CLK

enumerator UART_SCLK_RTC

UART source clock is RC_FAST

enumerator UART_SCLK_XTAL

UART source clock is XTAL

enumerator UART_SCLK_DEFAULT

UART source clock default choice is PLL_F40M

enum soc_periph_i2c_clk_src_t

Type of I2C clock source.

Values:

enumerator I2C_CLK_SRC_XTAL

enumerator I2C_CLK_SRC_RC_FAST

enumerator I2C_CLK_SRC_DEFAULT

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