SoC Capabilities

This section lists definitions of the ESP32-C2’s SoC hardware capabilities. These definitions are commonly used in IDF to control which hardware dependent features are supported and thus compiled into the binary.

Note

These defines are currently not considered to be part of the public API, and may be changed at any time.

API Reference

Header File

components/soc/esp32c2/include/soc/soc_caps.h

Macros

SOC_ADC_SUPPORTED

SOC_DEDICATED_GPIO_SUPPORTED

SOC_GDMA_SUPPORTED

SOC_BT_SUPPORTED

SOC_WIFI_SUPPORTED

SOC_ASYNC_MEMCPY_SUPPORTED

SOC_SUPPORTS_SECURE_DL_MODE

SOC_EFUSE_KEY_PURPOSE_FIELD

SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK

SOC_TEMP_SENSOR_SUPPORTED

SOC_SHA_SUPPORTED

SOC_ECC_SUPPORTED

SOC_FLASH_ENC_SUPPORTED

SOC_SECURE_BOOT_SUPPORTED

SOC_SYSTIMER_SUPPORTED

SOC_XTAL_SUPPORT_26M

SOC_XTAL_SUPPORT_40M

SOC_ADC_DIG_CTRL_SUPPORTED: < SAR ADC Module

SOC_ADC_FILTER_SUPPORTED

SOC_ADC_MONITOR_SUPPORTED

SOC_ADC_DIG_SUPPORTED_UNIT(UNIT)

SOC_ADC_PERIPH_NUM

SOC_ADC_CHANNEL_NUM(PERIPH_NUM)

SOC_ADC_MAX_CHANNEL_NUM

SOC_ADC_ATTEN_NUM: Digital

SOC_ADC_DIGI_CONTROLLER_NUM

SOC_ADC_PATT_LEN_MAX: One pattern table, each contains 8 items. Each item takes 1 byte

SOC_ADC_DIGI_MIN_BITWIDTH

SOC_ADC_DIGI_MAX_BITWIDTH

SOC_ADC_DIGI_FILTER_NUM

SOC_ADC_DIGI_MONITOR_NUM: F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095

SOC_ADC_SAMPLE_FREQ_THRES_HIGH

SOC_ADC_SAMPLE_FREQ_THRES_LOW: RTC

SOC_ADC_RTC_MIN_BITWIDTH

SOC_ADC_RTC_MAX_BITWIDTH

SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256: Calibration

SOC_ADC_CALIBRATION_V1_SUPPORTED: support HW offset calibration version 1

SOC_BROWNOUT_RESET_SUPPORTED

SOC_SHARED_IDCACHE_SUPPORTED

SOC_CPU_CORES_NUM

SOC_CPU_INTR_NUM

SOC_CPU_HAS_FLEXIBLE_INTC

SOC_CPU_BREAKPOINTS_NUM

SOC_CPU_WATCHPOINTS_NUM

SOC_CPU_WATCHPOINT_MAX_REGION_SIZE

SOC_CPU_IDRAM_SPLIT_USING_PMP

SOC_GDMA_GROUPS

SOC_GDMA_PAIRS_PER_GROUP

SOC_GDMA_TX_RX_SHARE_INTERRUPT

SOC_GPIO_PORT

SOC_GPIO_PIN_COUNT

SOC_GPIO_SUPPORTS_RTC_INDEPENDENT

SOC_GPIO_SUPPORT_FORCE_HOLD

SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP

SOC_GPIO_VALID_GPIO_MASK

SOC_GPIO_VALID_OUTPUT_GPIO_MASK

SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK

SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK

SOC_DEDIC_GPIO_OUT_CHANNELS_NUM: 8 outward channels on each CPU core

SOC_DEDIC_GPIO_IN_CHANNELS_NUM: 8 inward channels on each CPU core

SOC_DEDIC_PERIPH_ALWAYS_ENABLE: The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled

SOC_I2C_NUM

SOC_I2C_FIFO_LEN: I2C hardware FIFO depth

SOC_I2C_SUPPORT_HW_CLR_BUS

SOC_I2C_SUPPORT_XTAL

SOC_I2C_SUPPORT_RTC

SOC_LEDC_SUPPORT_PLL_DIV_CLOCK

SOC_LEDC_SUPPORT_XTAL_CLOCK

SOC_LEDC_CHANNEL_NUM

SOC_LEDC_TIMER_BIT_WIDE_NUM

SOC_LEDC_SUPPORT_FADE_STOP

SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED

SOC_MPU_MIN_REGION_SIZE

SOC_MPU_REGIONS_MAX_NUM

SOC_MPU_REGION_RO_SUPPORTED

SOC_MPU_REGION_WO_SUPPORTED

SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH

SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM

SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN

SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE

SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE

SOC_RTCIO_PIN_COUNT

SOC_RSA_MAX_BIT_LEN

SOC_SHA_SUPPORT_RESUME

SOC_SHA_SUPPORT_SHA1

SOC_SHA_SUPPORT_SHA224

SOC_SHA_SUPPORT_SHA256

SOC_SPI_PERIPH_NUM

SOC_SPI_PERIPH_CS_NUM(i)

SOC_SPI_MAX_CS_NUM

SOC_SPI_MAXIMUM_BUFFER_SIZE

SOC_SPI_SUPPORT_DDRCLK

SOC_SPI_SLAVE_SUPPORT_SEG_TRANS

SOC_SPI_SUPPORT_CD_SIG

SOC_SPI_SUPPORT_CONTINUOUS_TRANS

SOC_SPI_SUPPORT_SLAVE_HD_VER2

SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)

SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT

SOC_MEMSPI_IS_INDEPENDENT

SOC_SPI_MAX_PRE_DIVIDER

SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE

SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND

SOC_SPI_MEM_SUPPORT_AUTO_RESUME

SOC_SPI_MEM_SUPPORT_IDLE_INTR

SOC_SPI_MEM_SUPPORT_SW_SUSPEND

SOC_SPI_MEM_SUPPORT_CHECK_SUS

SOC_MEMSPI_SRC_FREQ_60M_SUPPORTED

SOC_MEMSPI_SRC_FREQ_30M_SUPPORTED

SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED

SOC_MEMSPI_SRC_FREQ_15M_SUPPORTED

SOC_SYSTIMER_COUNTER_NUM

SOC_SYSTIMER_ALARM_NUM

SOC_SYSTIMER_BIT_WIDTH_LO

SOC_SYSTIMER_BIT_WIDTH_HI

SOC_SYSTIMER_FIXED_DIVIDER

SOC_SYSTIMER_INT_LEVEL

SOC_SYSTIMER_ALARM_MISS_COMPENSATE

SOC_TIMER_GROUPS

SOC_TIMER_GROUP_TIMERS_PER_GROUP

SOC_TIMER_GROUP_COUNTER_BIT_WIDTH

SOC_TIMER_GROUP_SUPPORT_XTAL

SOC_TIMER_GROUP_SUPPORT_PLL_F40M

SOC_TIMER_GROUP_TOTAL_TIMERS

SOC_EFUSE_DIS_PAD_JTAG

SOC_EFUSE_DIS_DIRECT_BOOT

SOC_SECURE_BOOT_V2_ECC

SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS

SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX

SOC_FLASH_ENCRYPTION_XTS_AES

SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS

SOC_FLASH_ENCRYPTION_XTS_AES_128

SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED

SOC_UART_NUM

SOC_UART_FIFO_LEN: The UART hardware FIFO length

SOC_UART_BITRATE_MAX: Max bit rate supported by UART

SOC_UART_SUPPORT_WAKEUP_INT: Support UART wakeup interrupt

SOC_UART_SUPPORT_PLL_F40M_CLK: Support APB as the clock source

SOC_UART_SUPPORT_RTC_CLK: Support RTC clock as the clock source

SOC_UART_SUPPORT_XTAL_CLK: Support XTAL clock as the clock source

SOC_UART_SUPPORT_FSM_TX_WAIT_SEND

SOC_SUPPORT_COEXISTENCE

SOC_COEX_HW_PTI

SOC_EXTERNAL_COEX_ADVANCE

SOC_PHY_DIG_REGS_MEM_SIZE

SOC_MAC_BB_PD_MEM_SIZE

SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH

SOC_PM_SUPPORT_WIFI_WAKEUP

SOC_PM_SUPPORT_BT_WAKEUP

SOC_MMU_PAGE_SIZE_CONFIGURABLE

SOC_WIFI_HW_TSF: Support hardware TSF

SOC_WIFI_FTM_SUPPORT: Support FTM

SOC_WIFI_GCMP_SUPPORT: GCMP is not supported(GCMP128 and GCMP256)

SOC_WIFI_WAPI_SUPPORT: WAPI is not supported

SOC_WIFI_CSI_SUPPORT: CSI is not supported

SOC_WIFI_MESH_SUPPORT: WIFI MESH is not supported

SOC_BLE_SUPPORTED: Support Bluetooth Low Energy hardware

SOC_BLE_MESH_SUPPORTED: Support BLE MESH

SOC_ESP_NIMBLE_CONTROLLER: Support BLE EMBEDDED controller V1

SOC_BLE_50_SUPPORTED: Support Bluetooth 5.0

SOC_BLE_DEVICE_PRIVACY_SUPPORTED: Support BLE device privacy mode

SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED: Support For BLE Periodic Adv Enhancements

SOC_PHY_IMPROVE_RX_11B

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