SoC Capabilities
This section lists definitions of the ESP32-S2's SoC hardware capabilities. These definitions are commonly used in IDF to control which hardware dependent features are supported and thus compiled into the binary.
Note
These defines are currently not considered to be part of the public API, and may be changed at any time.
API Reference
Header File
Macros
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SOC_ADC_SUPPORTED
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SOC_DAC_SUPPORTED
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SOC_UART_SUPPORTED
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SOC_TWAI_SUPPORTED
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SOC_CP_DMA_SUPPORTED
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SOC_DEDICATED_GPIO_SUPPORTED
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SOC_GPTIMER_SUPPORTED
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SOC_SUPPORTS_SECURE_DL_MODE
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SOC_ULP_FSM_SUPPORTED
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SOC_RISCV_COPROC_SUPPORTED
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SOC_USB_OTG_SUPPORTED
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SOC_PCNT_SUPPORTED
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SOC_WIFI_SUPPORTED
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SOC_ULP_SUPPORTED
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SOC_CCOMP_TIMER_SUPPORTED
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SOC_ASYNC_MEMCPY_SUPPORTED
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SOC_EFUSE_KEY_PURPOSE_FIELD
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SOC_TEMP_SENSOR_SUPPORTED
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SOC_CACHE_SUPPORT_WRAP
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SOC_RTC_FAST_MEM_SUPPORTED
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SOC_RTC_SLOW_MEM_SUPPORTED
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SOC_RTC_MEM_SUPPORTED
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SOC_PSRAM_DMA_CAPABLE
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SOC_XT_WDT_SUPPORTED
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SOC_I2S_SUPPORTED
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SOC_RMT_SUPPORTED
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SOC_SDM_SUPPORTED
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SOC_GPSPI_SUPPORTED
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SOC_LEDC_SUPPORTED
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SOC_I2C_SUPPORTED
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SOC_SYSTIMER_SUPPORTED
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SOC_SUPPORT_COEXISTENCE
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SOC_AES_SUPPORTED
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SOC_MPI_SUPPORTED
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SOC_SHA_SUPPORTED
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SOC_HMAC_SUPPORTED
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SOC_DIG_SIGN_SUPPORTED
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SOC_FLASH_ENC_SUPPORTED
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SOC_SECURE_BOOT_SUPPORTED
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SOC_MEMPROT_SUPPORTED
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SOC_TOUCH_SENSOR_SUPPORTED
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SOC_BOD_SUPPORTED
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SOC_XTAL_SUPPORT_40M
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SOC_ADC_RTC_CTRL_SUPPORTED
< SAR ADC Module
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SOC_ADC_DIG_CTRL_SUPPORTED
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SOC_ADC_ARBITER_SUPPORTED
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SOC_ADC_DIG_IIR_FILTER_SUPPORTED
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SOC_ADC_DIG_IIR_FILTER_UNIT_BINDED
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SOC_ADC_MONITOR_SUPPORTED
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SOC_ADC_DMA_SUPPORTED
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SOC_ADC_DIG_SUPPORTED_UNIT(UNIT)
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SOC_ADC_PERIPH_NUM
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SOC_ADC_CHANNEL_NUM(UNIT)
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SOC_ADC_MAX_CHANNEL_NUM
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SOC_ADC_ATTEN_NUM
Digital
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SOC_ADC_DIGI_CONTROLLER_NUM
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SOC_ADC_PATT_LEN_MAX
Two pattern table, each contains 16 items. Each item takes 1 byte
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SOC_ADC_DIGI_MIN_BITWIDTH
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SOC_ADC_DIGI_MAX_BITWIDTH
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SOC_ADC_DIGI_IIR_FILTER_NUM
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SOC_ADC_DIGI_RESULT_BYTES
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SOC_ADC_DIGI_DATA_BYTES_PER_CONV
F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095
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SOC_ADC_SAMPLE_FREQ_THRES_HIGH
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SOC_ADC_SAMPLE_FREQ_THRES_LOW
RTC
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SOC_ADC_RTC_MIN_BITWIDTH
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SOC_ADC_RTC_MAX_BITWIDTH
Calibration
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SOC_ADC_CALIBRATION_V1_SUPPORTED
support HW offset calibration version 1
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SOC_ADC_SELF_HW_CALI_SUPPORTED
support HW offset self calibration
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SOC_BROWNOUT_RESET_SUPPORTED
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SOC_CACHE_WRITEBACK_SUPPORTED
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SOC_CP_DMA_MAX_BUFFER_SIZE
Maximum size of the buffer that can be attached to descriptor
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SOC_CPU_CORES_NUM
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SOC_CPU_INTR_NUM
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SOC_CPU_BREAKPOINTS_NUM
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SOC_CPU_WATCHPOINTS_NUM
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SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
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SOC_DAC_CHAN_NUM
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SOC_DAC_RESOLUTION
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SOC_GPIO_PORT
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SOC_GPIO_PIN_COUNT
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SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
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SOC_GPIO_FILTER_CLK_SUPPORT_APB
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SOC_GPIO_SUPPORT_RTC_INDEPENDENT
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SOC_GPIO_SUPPORT_FORCE_HOLD
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SOC_GPIO_VALID_GPIO_MASK
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SOC_GPIO_VALID_OUTPUT_GPIO_MASK
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SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
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SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
8 outward channels on each CPU core
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SOC_DEDIC_GPIO_IN_CHANNELS_NUM
8 inward channels on each CPU core
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SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
Allow access dedicated GPIO channel by register
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SOC_DEDIC_GPIO_HAS_INTERRUPT
Dedicated GPIO has its own interrupt source
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SOC_DEDIC_GPIO_OUT_AUTO_ENABLE
Dedicated GPIO output attribution is enabled automatically
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SOC_I2C_NUM
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SOC_I2C_FIFO_LEN
I2C hardware FIFO depth
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SOC_I2C_CMD_REG_NUM
Number of I2C command registers
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SOC_I2C_SUPPORT_SLAVE
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SOC_I2C_SUPPORT_HW_CLR_BUS
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SOC_I2C_SUPPORT_REF_TICK
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SOC_I2C_SUPPORT_APB
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SOC_I2S_NUM
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SOC_I2S_HW_VERSION_1
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SOC_I2S_SUPPORTS_APLL
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SOC_I2S_SUPPORTS_PLL_F160M
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SOC_I2S_SUPPORTS_DMA_EQUAL
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SOC_I2S_SUPPORTS_LCD_CAMERA
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SOC_I2S_APLL_MIN_FREQ
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SOC_I2S_APLL_MAX_FREQ
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SOC_I2S_APLL_MIN_RATE
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SOC_I2S_LCD_I80_VARIANT
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SOC_LCD_I80_SUPPORTED
Intel 8080 LCD is supported
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SOC_LCD_I80_BUSES
Only I2S0 has LCD mode
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SOC_LCD_I80_BUS_WIDTH
Intel 8080 bus width
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SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
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SOC_LEDC_SUPPORT_APB_CLOCK
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SOC_LEDC_SUPPORT_REF_TICK
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SOC_LEDC_SUPPORT_XTAL_CLOCK
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SOC_LEDC_CHANNEL_NUM
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SOC_LEDC_TIMER_BIT_WIDTH
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SOC_LEDC_SUPPORT_FADE_STOP
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SOC_MMU_LINEAR_ADDRESS_REGION_NUM
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SOC_MMU_PERIPH_NUM
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SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
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SOC_MPU_MIN_REGION_SIZE
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SOC_MPU_REGIONS_MAX_NUM
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SOC_MPU_REGION_RO_SUPPORTED
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SOC_MPU_REGION_WO_SUPPORTED
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SOC_PCNT_GROUPS
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SOC_PCNT_UNITS_PER_GROUP
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SOC_PCNT_CHANNELS_PER_UNIT
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SOC_PCNT_THRES_POINT_PER_UNIT
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SOC_RMT_GROUPS
One RMT group
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SOC_RMT_TX_CANDIDATES_PER_GROUP
Number of channels that capable of Transmit in each group
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SOC_RMT_RX_CANDIDATES_PER_GROUP
Number of channels that capable of Receive in each group
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SOC_RMT_CHANNELS_PER_GROUP
Total 4 channels
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SOC_RMT_MEM_WORDS_PER_CHANNEL
Each channel owns 64 words memory (1 word = 4 Bytes)
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SOC_RMT_SUPPORT_RX_DEMODULATION
Support signal demodulation on RX path (i.e. remove carrier)
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SOC_RMT_SUPPORT_TX_ASYNC_STOP
Support stop transmission asynchronously
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SOC_RMT_SUPPORT_TX_LOOP_COUNT
Support transmiting specified number of cycles in loop mode
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SOC_RMT_SUPPORT_TX_SYNCHRO
Support coordinate a group of TX channels to start simultaneously
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SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY
TX carrier can be modulated to data phase only
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SOC_RMT_SUPPORT_REF_TICK
Support set REF_TICK as the RMT clock source
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SOC_RMT_SUPPORT_APB
Support set APB as the RMT clock source
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SOC_RMT_CHANNEL_CLK_INDEPENDENT
Can select different source clock for each channel
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SOC_RTCIO_PIN_COUNT
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SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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SOC_RTCIO_HOLD_SUPPORTED
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SOC_RTCIO_WAKE_SUPPORTED
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SOC_SDM_GROUPS
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SOC_SDM_CHANNELS_PER_GROUP
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SOC_SDM_CLK_SUPPORT_APB
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SOC_SPI_HD_BOTH_INOUT_SUPPORTED
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SOC_SPI_PERIPH_NUM
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SOC_SPI_DMA_CHAN_NUM
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SOC_SPI_PERIPH_CS_NUM(i)
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SOC_SPI_MAX_CS_NUM
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SOC_SPI_MAXIMUM_BUFFER_SIZE
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SOC_SPI_MAX_PRE_DIVIDER
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SOC_SPI_SUPPORT_DDRCLK
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SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
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SOC_SPI_SUPPORT_CD_SIG
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SOC_SPI_SUPPORT_CONTINUOUS_TRANS
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SOC_SPI_SUPPORT_CLK_APB
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SOC_SPI_SUPPORT_SLAVE_HD_VER2
The SPI Slave half duplex mode has been updated greatly in ESP32-S2.
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SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)
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SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
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SOC_MEMSPI_IS_INDEPENDENT
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SOC_SPI_SUPPORT_OCT
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SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
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SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
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SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED
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SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
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SOC_SYSTIMER_COUNTER_NUM
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SOC_SYSTIMER_ALARM_NUM
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SOC_SYSTIMER_BIT_WIDTH_LO
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SOC_SYSTIMER_BIT_WIDTH_HI
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SOC_TIMER_GROUPS
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SOC_TIMER_GROUP_TIMERS_PER_GROUP
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SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
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SOC_TIMER_GROUP_SUPPORT_XTAL
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SOC_TIMER_GROUP_SUPPORT_APB
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SOC_TIMER_GROUP_TOTAL_TIMERS
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SOC_TOUCH_VERSION_2
Hardware version of touch sensor
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SOC_TOUCH_SENSOR_NUM
15 Touch channels
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SOC_TOUCH_PROXIMITY_CHANNEL_NUM
Support touch proximity channel number.
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SOC_TOUCH_PAD_THRESHOLD_MAX
If set touch threshold max value, The touch sensor can't be in touched status
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SOC_TOUCH_PAD_MEASURE_WAIT_MAX
The timer frequency is 8Mhz, the max value is 0xff
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SOC_TWAI_CONTROLLER_NUM
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SOC_TWAI_CLK_SUPPORT_APB
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SOC_TWAI_BRP_MIN
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SOC_TWAI_BRP_MAX
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SOC_TWAI_SUPPORTS_RX_STATUS
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SOC_UART_NUM
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SOC_UART_SUPPORT_WAKEUP_INT
Support UART wakeup interrupt
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SOC_UART_SUPPORT_APB_CLK
Support APB as the clock source
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SOC_UART_SUPPORT_REF_TICK
Support REF_TICK as the clock source
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SOC_UART_FIFO_LEN
The UART hardware FIFO length
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SOC_UART_BITRATE_MAX
Max bit rate supported by UART
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SOC_SPIRAM_SUPPORTED
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SOC_SPIRAM_XIP_SUPPORTED
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SOC_USB_OTG_PERIPH_NUM
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SOC_SHA_DMA_MAX_BUFFER_SIZE
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SOC_SHA_SUPPORT_DMA
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SOC_SHA_SUPPORT_RESUME
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SOC_SHA_CRYPTO_DMA
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SOC_SHA_SUPPORT_SHA1
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SOC_SHA_SUPPORT_SHA224
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SOC_SHA_SUPPORT_SHA256
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SOC_SHA_SUPPORT_SHA384
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SOC_SHA_SUPPORT_SHA512
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SOC_SHA_SUPPORT_SHA512_224
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SOC_SHA_SUPPORT_SHA512_256
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SOC_SHA_SUPPORT_SHA512_T
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SOC_RSA_MAX_BIT_LEN
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SOC_AES_SUPPORT_DMA
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SOC_AES_SUPPORT_GCM
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SOC_EFUSE_DIS_DOWNLOAD_ICACHE
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SOC_EFUSE_DIS_DOWNLOAD_DCACHE
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SOC_EFUSE_HARD_DIS_JTAG
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SOC_EFUSE_SOFT_DIS_JTAG
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SOC_EFUSE_DIS_BOOT_REMAP
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SOC_EFUSE_DIS_LEGACY_SPI_BOOT
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SOC_EFUSE_DIS_ICACHE
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SOC_SECURE_BOOT_V2_RSA
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SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
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SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
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SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
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SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
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SOC_FLASH_ENCRYPTION_XTS_AES
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SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS
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SOC_FLASH_ENCRYPTION_XTS_AES_128
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SOC_FLASH_ENCRYPTION_XTS_AES_256
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SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE
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SOC_MEMPROT_MEM_ALIGN_SIZE
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SOC_AES_CRYPTO_DMA
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SOC_AES_SUPPORT_AES_128
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SOC_AES_SUPPORT_AES_192
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SOC_AES_SUPPORT_AES_256
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SOC_PHY_DIG_REGS_MEM_SIZE
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SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
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SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
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SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
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SOC_SPI_MEM_SUPPORT_SW_SUSPEND
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SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
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SOC_SPI_MEM_SUPPORT_WRAP
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SOC_PM_SUPPORT_EXT0_WAKEUP
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SOC_PM_SUPPORT_EXT1_WAKEUP
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SOC_PM_SUPPORT_EXT_WAKEUP
Compatible to the old version of IDF
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SOC_PM_SUPPORT_WIFI_WAKEUP
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SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP
Supports waking up from touch pad trigger
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SOC_PM_SUPPORT_WIFI_PD
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SOC_PM_SUPPORT_RTC_PERIPH_PD
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SOC_PM_SUPPORT_RTC_FAST_MEM_PD
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SOC_PM_SUPPORT_RTC_SLOW_MEM_PD
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SOC_PM_SUPPORT_RC_FAST_PD
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SOC_PM_SUPPORT_VDDSDIO_PD
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SOC_CONFIGURABLE_VDDSDIO_SUPPORTED
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SOC_CLK_APLL_SUPPORTED
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SOC_APLL_MULTIPLIER_OUT_MIN_HZ
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SOC_APLL_MULTIPLIER_OUT_MAX_HZ
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SOC_APLL_MIN_HZ
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SOC_APLL_MAX_HZ
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SOC_CLK_RC_FAST_D256_SUPPORTED
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SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256
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SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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SOC_CLK_XTAL32K_SUPPORTED
Support to connect an external low frequency crystal
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SOC_COEX_HW_PTI
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SOC_EXTERNAL_COEX_ADVANCE
HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS
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SOC_EXTERNAL_COEX_LEADER_TX_LINE
EXTERNAL COEXISTENCE TX LINE CAPS
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SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
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SOC_WIFI_HW_TSF
Support hardware TSF
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SOC_WIFI_FTM_SUPPORT
Support FTM
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SOC_WIFI_WAPI_SUPPORT
Support WAPI
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SOC_WIFI_CSI_SUPPORT
Support CSI
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SOC_WIFI_MESH_SUPPORT
Support WIFI MESH
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SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW
Support delta early time for rf phy on/off
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SOC_WIFI_NAN_SUPPORT
Support WIFI Aware (NAN)
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SOC_ULP_HAS_ADC
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SOC_PHY_COMBO_MODULE
Only support Wi-Fi