# Interrupt Allocation

[中文]

## Overview

The ESP32-C5 has one core, with 32 external asynchronous interrupts. Each interrupt's priority is independently programmable. In addition, there are also 3 core local interrupt sources (CLINT). For details, see ESP32-C5 Technical Reference Manual > High-Performance CPU [PDF].

Because there are more interrupt sources than interrupts, sometimes it makes sense to share an interrupt in multiple drivers. The `esp_intr_alloc()` abstraction exists to hide all these implementation details.

A driver can allocate an interrupt for a certain peripheral by calling `esp_intr_alloc()` (or `esp_intr_alloc_intrstatus()`). It can use the flags passed to this function to specify the type, priority, and trigger method of the interrupt to allocate. The interrupt allocation code will then find an applicable interrupt, use the interrupt matrix to hook it up to the peripheral, and install the given interrupt handler and ISR to it.

The interrupt allocator presents two different types of interrupts, namely shared interrupts and non-shared interrupts, both of which require different handling. Non-shared interrupts will allocate a separate interrupt for every `esp_intr_alloc()` call, and this interrupt is use solely for the peripheral attached to it, with only one ISR that will get called. Shared interrupts can have multiple peripherals triggering them, with multiple ISRs being called when one of the peripherals attached signals an interrupt. Thus, ISRs that are intended for shared interrupts should check the interrupt status of the peripheral they service in order to check if any action is required.

Non-shared interrupts can be either level- or edge-triggered. Shared interrupts can only be level interrupts due to the chance of missed interrupts when edge interrupts are used.

To illustrate why shared interrupts can only be level-triggered, take the scenario where peripheral A and peripheral B share the same edge-triggered interrupt. Peripheral B triggers an interrupt and sets its interrupt signal high, causing a low-to-high edge, which in turn latches the CPU's interrupt bit and triggers the ISR. The ISR executes, checks that peripheral A did not trigger an interrupt, and proceeds to handle and clear peripheral B's interrupt signal. Before the ISR returns, the CPU clears its interrupt bit latch. Thus, during the entire interrupt handling process, if peripheral A triggers an interrupt, it will be missed due the CPU clearing the interrupt bit latch.

## IRAM-Safe Interrupt Handlers

When performing write and erase operations on SPI flash, ESP32-C5 will disable the cache, making SPI flash and SPIRAM inaccessible for interrupt handlers. This is why there are two types of interrupt handlers in ESP-IDF, which have their advantages and disadvantages:

IRAM-safe interrupt handlers - only access code and data in internal memory (IRAM for code, DRAM for data).

- + Latency: They execute relatively fast and with low latency, since they are not blocked by slow flash write and erase operations (erases can take tens or hundreds of milliseconds to complete). This is useful for interrupts which need a guaranteed minimum execution latency.

- - Internal memory use: They consume precious internal memory that could otherwise be used for something else.

- + Cache misses: They do not rely on the cache with potential cache misses since the code and data are in internal memory already.

- Usage: To register such an interrupt via the interrupt allocator API, use the `ESP_INTR_FLAG_IRAM` flag.

Non-IRAM-safe interrupt handlers - may access code and (read-only) data in flash.

- - Latency: In case of flash operations, these interrupt handlers are postponed, which makes their average latency longer and less predictable.

- + Internal memory use: They do not use any or not as much memory in internal RAM as IRAM-safe interrupts.

- Usage: To register such an interrupt via the interrupt allocator API, do not use the `ESP_INTR_FLAG_IRAM` flag.

Note that there is nothing that explicitly marks an interrupt handler as IRAM-safe. An interrupt handler is IRAM-safe implicitly if and only if the code and data it may access are placed in internal memory. The term "IRAM-safe" is actually a bit misleading, since there are more requirements than just placing the handler's code in IRAM memory. Examples of interrupt handlers that are not IRAM-safe include:

- A handler that has some of its code placed in flash memory.

- A handler that is placed in IRAM but calls functions placed in flash memory.

- A handler that accesses a read-only variable placed in flash, even though the handler's code is actually placed in IRAM.

For details on placing code and data in IRAM or DRAM, see How to Place Code in IRAM.

For more details about SPI flash operations and their interactions with interrupt handlers, see the SPI flash API documentation.

Note

Never register an interrupt handler with `ESP_INTR_FLAG_IRAM` flag if you are not 100% sure that all the code and data that the interrupt ever accesses are in IRAM (code) or DRAM (data). Disregarding this will lead to (sometimes spurious) cache errors. This must also be true for code and data accessed indirectly through function calls.

## Multiple Handlers Sharing A Source

Several handlers can be assigned to a same source, given that all handlers are allocated using the `ESP_INTR_FLAG_SHARED` flag. They will all be allocated to the interrupt, which the source is attached to, and called sequentially when the source is active. The handlers can be disabled and freed individually. The source is attached to the interrupt (enabled), if one or more handlers are enabled, otherwise detached. A handler will never be called when disabled, while its source may still be triggered if any one of its handler enabled.

Sources attached to non-shared interrupt do not support this feature.

Though the framework supports this feature, you have to use it very carefully. There usually exist two ways to stop an interrupt from being triggered: disable the source or mask peripheral interrupt status. ESP-IDF only handles enabling and disabling of the source itself, leaving status and mask bits to be handled by users.

Status bits shall either be masked before the handler responsible for it is disabled, or be masked and then properly handled in another enabled interrupt.

Note

Leaving some status bits unhandled without masking them, while disabling the handlers for them, will cause the interrupt(s) to be triggered indefinitely, resulting therefore in a system crash.

## Troubleshooting Interrupt Allocation

On most Espressif SoCs, CPU interrupts are a limited resource. Therefore it is possible for a program to run out of CPU interrupts, for example by initializing several peripheral drivers. Typically, this will result in the driver initialization function returning `ESP_ERR_NOT_FOUND` error code.

If this happens, you can use `esp_intr_dump()` function to print the list of interrupts along with their status. The output of this function typically looks like this:

    CPU 0 interrupt status:
    Int  Level  Type   Status
    0     1    Level  Reserved
    1     1    Level  Reserved
    2     1    Level  Used: RTC_CORE
    3     1    Level  Used: TG0_LACT_LEVEL
    ...

The columns of the output have the following meaning:

- `Int`: CPU interrupt input number. This is typically not used in software directly, and is provided for reference only.

- `Level`: For interrupts which have been allocated, the priority of the interrupt. For free interrupts `*` is printed.

- `Type`: For interrupts which have been allocated, the type (Level or Edge) of the interrupt. For free interrupts `*` is printed.

- `Status`: One of the possible statuses of the interrupt:

    - `Reserved`: The interrupt is reserved either at hardware level, or by one of the parts of ESP-IDF. It can not be allocated using `esp_intr_alloc()`.

    - `Used: <source>`: The interrupt is allocated and connected to a single peripheral.

    - `Shared: <source1> <source2> ...`: The interrupt is allocated and connected to multiple peripherals. See Multiple Handlers Sharing A Source above.

    - `Free`: The interrupt is not allocated and can be used by `esp_intr_alloc()`.

If you have confirmed that the application is indeed running out of interrupts, a combination of the following suggestions can help resolve the issue:

- Determine the interrupts which can tolerate higher latency, and allocate them using `ESP_INTR_FLAG_SHARED` flag (optionally ORed with `ESP_INTR_FLAG_LOWMED`). Using this flag for two or more peripherals will let them use a single interrupt input, and therefore save interrupt inputs for other peripherals. See Multiple Handlers Sharing A Source above.

- Check if some of the peripheral drivers do not need to be used all the time, and initialize or deinitialize them on demand. This can reduce the number of simultaneously allocated interrupts.

## API Reference

### Header File

- components/esp_hw_support/include/esp_intr_types.h

- This header file can be included with:

  >     #include "esp_intr_types.h"

### Macros

ESP_INTR_CPU_AFFINITY_TO_CORE_ID(cpu_affinity)

  Convert esp_intr_cpu_affinity_t to CPU core ID.

### Type Definitions

typedef void (*intr_handler_t)(void *arg)

  Function prototype for interrupt handler function

typedef struct intr_handle_data_t *intr_handle_t

  Handle to an interrupt handler

### Enumerations

enum esp_intr_cpu_affinity_t

  Interrupt CPU core affinity.

  This type specify the CPU core that the peripheral interrupt is connected to.

  Values:

  enumerator ESP_INTR_CPU_AFFINITY_AUTO

    Install the peripheral interrupt to ANY CPU core, decided by on which CPU the interrupt allocator is running.

  enumerator ESP_INTR_CPU_AFFINITY_0

    Install the peripheral interrupt to CPU core 0.

  enumerator ESP_INTR_CPU_AFFINITY_1

    Install the peripheral interrupt to CPU core 1.

### Header File

- components/esp_hw_support/include/esp_intr_alloc.h

- This header file can be included with:

  >     #include "esp_intr_alloc.h"

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