# SoC Capabilities

[中文]

This section lists the macro definitions of the ESP32-C5's SoC hardware capabilities. These macros are commonly used by conditional-compilation directives (e.g., `#if`) in ESP-IDF to determine which hardware-dependent features are supported, thus control what portions of code are compiled.

Warning

These macro definitions are currently not considered to be part of the public API, and may be changed in a breaking manner (see ESP-IDF Versions for more details).

## API Reference

### Header File

- components/soc/esp32c5/include/soc/soc_caps.h

- This header file can be included with:

  >     #include "soc/soc_caps.h"

### Macros

SOC_ADC_SUPPORTED

SOC_DEDICATED_GPIO_SUPPORTED

SOC_UART_SUPPORTED

SOC_GDMA_SUPPORTED

SOC_AHB_GDMA_SUPPORTED

SOC_GPTIMER_SUPPORTED

SOC_PCNT_SUPPORTED

SOC_MCPWM_SUPPORTED

SOC_ETM_SUPPORTED

SOC_PARLIO_SUPPORTED

SOC_ASYNC_MEMCPY_SUPPORTED

SOC_USB_SERIAL_JTAG_SUPPORTED

SOC_TEMP_SENSOR_SUPPORTED

SOC_WIFI_SUPPORTED

SOC_SUPPORTS_SECURE_DL_MODE

SOC_LP_CORE_SUPPORTED

SOC_ULP_SUPPORTED

SOC_EFUSE_KEY_PURPOSE_FIELD

SOC_EFUSE_SUPPORTED

SOC_RTC_FAST_MEM_SUPPORTED

SOC_RTC_MEM_SUPPORTED

SOC_I2S_SUPPORTED

SOC_RMT_SUPPORTED

SOC_SDM_SUPPORTED

SOC_GPSPI_SUPPORTED

SOC_LEDC_SUPPORTED

SOC_I2C_SUPPORTED

SOC_SYSTIMER_SUPPORTED

SOC_AES_SUPPORTED

SOC_MPI_SUPPORTED

SOC_SHA_SUPPORTED

SOC_RSA_SUPPORTED

SOC_HMAC_SUPPORTED

SOC_DIG_SIGN_SUPPORTED

SOC_ECC_SUPPORTED

SOC_ECC_EXTENDED_MODES_SUPPORTED

SOC_FLASH_ENC_SUPPORTED

SOC_SECURE_BOOT_SUPPORTED

SOC_IEEE802154_SUPPORTED

SOC_BOD_SUPPORTED

SOC_APM_SUPPORTED

  Support for APM peripheral

SOC_PMU_SUPPORTED

SOC_PAU_SUPPORTED

SOC_LP_TIMER_SUPPORTED

SOC_LP_AON_SUPPORTED

SOC_LP_PERIPHERALS_SUPPORTED

SOC_LP_I2C_SUPPORTED

SOC_ULP_LP_UART_SUPPORTED

SOC_CLK_TREE_SUPPORTED

SOC_WDT_SUPPORTED

SOC_SPI_FLASH_SUPPORTED

SOC_ECDSA_SUPPORTED

SOC_RNG_SUPPORTED

SOC_MODEM_CLOCK_SUPPORTED

SOC_LIGHT_SLEEP_SUPPORTED

SOC_DEEP_SLEEP_SUPPORTED

SOC_PM_SUPPORTED

SOC_SPIRAM_SUPPORTED

SOC_BT_SUPPORTED

SOC_PHY_SUPPORTED

SOC_XTAL_SUPPORT_40M

SOC_XTAL_SUPPORT_48M

SOC_XTAL_CLOCK_PATH_DEPENDS_ON_TOP_DOMAIN

SOC_AES_SUPPORT_DMA

SOC_AES_GDMA

SOC_AES_SUPPORT_AES_128

SOC_AES_SUPPORT_AES_256

SOC_ADC_DIG_CTRL_SUPPORTED

  < SAR ADC Module

SOC_ADC_DIG_IIR_FILTER_SUPPORTED

SOC_ADC_MONITOR_SUPPORTED

SOC_ADC_DIG_SUPPORTED_UNIT(UNIT)

SOC_ADC_DMA_SUPPORTED

SOC_ADC_PERIPH_NUM

SOC_ADC_CHANNEL_NUM(PERIPH_NUM)

SOC_ADC_MAX_CHANNEL_NUM

SOC_ADC_ATTEN_NUM

  Digital

SOC_ADC_DIGI_CONTROLLER_NUM

SOC_ADC_PATT_LEN_MAX

  Two pattern tables, each contains 4 items. Each item takes 1 byte

SOC_ADC_DIGI_MAX_BITWIDTH

SOC_ADC_DIGI_MIN_BITWIDTH

SOC_ADC_DIGI_IIR_FILTER_NUM

SOC_ADC_DIGI_MONITOR_NUM

SOC_ADC_DIGI_RESULT_BYTES

SOC_ADC_DIGI_DATA_BYTES_PER_CONV

  F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095

SOC_ADC_SAMPLE_FREQ_THRES_HIGH

SOC_ADC_SAMPLE_FREQ_THRES_LOW

  RTC

SOC_ADC_RTC_MIN_BITWIDTH

SOC_ADC_RTC_MAX_BITWIDTH

  Calibration

SOC_ADC_TEMPERATURE_SHARE_INTR

  < Interrupt ADC power control is shared by PWDET

SOC_ADC_SHARED_POWER

SOC_BROWNOUT_RESET_SUPPORTED

SOC_SHARED_IDCACHE_SUPPORTED

SOC_CACHE_WRITEBACK_SUPPORTED

SOC_CACHE_FREEZE_SUPPORTED

SOC_CPU_CORES_NUM

SOC_CPU_INTR_NUM

SOC_CPU_HAS_FLEXIBLE_INTC

SOC_CPU_SUPPORT_WFE

SOC_INT_CLIC_SUPPORTED

SOC_INT_HW_NESTED_SUPPORTED

SOC_BRANCH_PREDICTOR_SUPPORTED

SOC_CPU_BREAKPOINTS_NUM

SOC_CPU_WATCHPOINTS_NUM

SOC_CPU_WATCHPOINT_MAX_REGION_SIZE

SOC_CPU_HAS_PMA

SOC_CPU_IDRAM_SPLIT_USING_PMP

SOC_CPU_PMP_REGION_GRANULARITY

SOC_CPU_HAS_LOCKUP_RESET

SOC_DS_SIGNATURE_MAX_BIT_LEN

  The maximum length of a Digital Signature in bits.

SOC_DS_KEY_PARAM_MD_IV_LENGTH

  Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes.

SOC_DS_KEY_CHECK_MAX_WAIT_US

  Maximum wait time for DS parameter decryption key. If overdue, then key error. See TRM DS chapter for more details

SOC_DMA_CAN_ACCESS_FLASH

  DMA can access Flash memory

SOC_AHB_GDMA_VERSION

SOC_GDMA_NUM_GROUPS_MAX

SOC_GDMA_PAIRS_PER_GROUP_MAX

SOC_GDMA_SUPPORT_ETM

SOC_GDMA_SUPPORT_SLEEP_RETENTION

SOC_AHB_GDMA_SUPPORT_PSRAM

SOC_ETM_GROUPS

SOC_ETM_CHANNELS_PER_GROUP

SOC_ETM_SUPPORT_SLEEP_RETENTION

SOC_GPIO_PORT

SOC_GPIO_PIN_COUNT

SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER

SOC_GPIO_FLEX_GLITCH_FILTER_NUM

SOC_GPIO_SUPPORT_PIN_HYS_FILTER

SOC_GPIO_SUPPORT_ETM

SOC_GPIO_SUPPORT_RTC_INDEPENDENT

SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP

SOC_LP_IO_CLOCK_IS_INDEPENDENT

SOC_GPIO_VALID_GPIO_MASK

SOC_GPIO_VALID_OUTPUT_GPIO_MASK

SOC_GPIO_IN_RANGE_MAX

SOC_GPIO_OUT_RANGE_MAX

SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK

SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT

SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK

SOC_GPIO_SUPPORT_FORCE_HOLD

SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP

SOC_GPIO_CLOCKOUT_CHANNEL_NUM

SOC_RTCIO_PIN_COUNT

SOC_RTCIO_INPUT_OUTPUT_SUPPORTED

SOC_RTCIO_HOLD_SUPPORTED

SOC_RTCIO_WAKE_SUPPORTED

SOC_RTCIO_EDGE_WAKE_SUPPORTED

SOC_DEDIC_GPIO_OUT_CHANNELS_NUM

  8 outward channels on each CPU core

SOC_DEDIC_GPIO_IN_CHANNELS_NUM

  8 inward channels on each CPU core

SOC_DEDIC_PERIPH_ALWAYS_ENABLE

  The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled

SOC_I2C_NUM

SOC_HP_I2C_NUM

SOC_I2C_FIFO_LEN

  I2C hardware FIFO depth

SOC_I2C_CMD_REG_NUM

  Number of I2C command registers

SOC_I2C_SUPPORT_SLAVE

SOC_I2C_SUPPORT_HW_FSM_RST

SOC_I2C_SUPPORT_XTAL

SOC_I2C_SUPPORT_RTC

SOC_I2C_SUPPORT_10BIT_ADDR

SOC_I2C_SLAVE_SUPPORT_BROADCAST

SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE

SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS

SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH

SOC_I2C_SUPPORT_SLEEP_RETENTION

SOC_LP_I2C_NUM

SOC_LP_I2C_FIFO_LEN

  LP_I2C hardware FIFO depth

SOC_I2S_NUM

SOC_I2S_HW_VERSION_2

SOC_I2S_SUPPORTS_ETM

SOC_I2S_SUPPORTS_TX_SYNC_CNT

SOC_I2S_SUPPORTS_XTAL

SOC_I2S_SUPPORTS_PLL_F160M

SOC_I2S_SUPPORTS_PLL_F240M

SOC_I2S_SUPPORTS_PCM

SOC_I2S_SUPPORTS_PDM

SOC_I2S_SUPPORTS_PDM_TX

SOC_I2S_PDM_MAX_TX_LINES

SOC_I2S_SUPPORTS_TDM

SOC_I2S_TDM_FULL_DATA_WIDTH

  No limitation to data bit width when using multiple slots

SOC_I2S_SUPPORT_SLEEP_RETENTION

  The sleep retention feature can help back up I2S registers before sleep

SOC_LEDC_SUPPORT_PLL_DIV_CLOCK

SOC_LEDC_SUPPORT_XTAL_CLOCK

SOC_LEDC_TIMER_NUM

SOC_LEDC_CHANNEL_NUM

SOC_LEDC_TIMER_BIT_WIDTH

SOC_LEDC_SUPPORT_FADE_STOP

SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED

SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX

SOC_LEDC_FADE_PARAMS_BIT_WIDTH

SOC_LEDC_SUPPORT_SLEEP_RETENTION

SOC_MMU_PERIPH_NUM

SOC_MMU_LINEAR_ADDRESS_REGION_NUM

SOC_MMU_DI_VADDR_SHARED

  D/I vaddr are shared

SOC_PCNT_GROUPS

SOC_PCNT_UNITS_PER_GROUP

SOC_PCNT_CHANNELS_PER_UNIT

SOC_PCNT_THRES_POINT_PER_UNIT

SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE

SOC_PCNT_SUPPORT_CLEAR_SIGNAL

SOC_PCNT_SUPPORT_STEP_NOTIFY

SOC_PCNT_SUPPORT_SLEEP_RETENTION

  The sleep retention feature can help back up PCNT registers before sleep

SOC_RMT_GROUPS

  One RMT group

SOC_RMT_TX_CANDIDATES_PER_GROUP

  Number of channels that capable of Transmit

SOC_RMT_RX_CANDIDATES_PER_GROUP

  Number of channels that capable of Receive

SOC_RMT_CHANNELS_PER_GROUP

  Total 4 channels

SOC_RMT_MEM_WORDS_PER_CHANNEL

  Each channel owns 48 words memory (1 word = 4 Bytes)

SOC_RMT_SUPPORT_RX_PINGPONG

  Support Ping-Pong mode on RX path

SOC_RMT_SUPPORT_RX_DEMODULATION

  Support signal demodulation on RX path (i.e. remove carrier)

SOC_RMT_SUPPORT_ASYNC_STOP

  Support stop transmission asynchronously

SOC_RMT_SUPPORT_TX_LOOP_COUNT

  Support transmit specified number of cycles in loop mode

SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP

  Hardware support of auto-stop in loop mode

SOC_RMT_SUPPORT_TX_SYNCHRO

  Support coordinate a group of TX channels to start simultaneously

SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY

  TX carrier can be modulated to data phase only

SOC_RMT_SUPPORT_XTAL

  Support set XTAL clock as the RMT clock source

SOC_RMT_SUPPORT_SLEEP_RETENTION

  The sleep retention feature can help back up RMT registers before sleep

SOC_MCPWM_GROUPS

  1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)

SOC_MCPWM_TIMERS_PER_GROUP

  The number of timers that each group has.

SOC_MCPWM_OPERATORS_PER_GROUP

  The number of operators that each group has.

SOC_MCPWM_COMPARATORS_PER_OPERATOR

  The number of comparators that each operator has.

SOC_MCPWM_GENERATORS_PER_OPERATOR

  The number of generators that each operator has.

SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR

  The number of event comparators that each operator has.

SOC_MCPWM_TRIGGERS_PER_OPERATOR

  The number of triggers that each operator has.

SOC_MCPWM_GPIO_FAULTS_PER_GROUP

  The number of fault signal detectors that each group has.

SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP

  The number of capture timers that each group has.

SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER

  The number of capture channels that each capture timer has.

SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP

  The number of GPIO synchros that each group has.

SOC_MCPWM_SWSYNC_CAN_PROPAGATE

  Software sync event can be routed to its output.

SOC_MCPWM_SUPPORT_ETM

  Support ETM (Event Task Matrix)

SOC_MCPWM_SUPPORT_EVENT_COMPARATOR

  Support event comparator (based on ETM)

SOC_MCPWM_CAPTURE_CLK_FROM_GROUP

  Capture timer shares clock with other PWM timers.

SOC_MCPWM_SUPPORT_SLEEP_RETENTION

  Support back up registers before sleep.

SOC_PARLIO_GROUPS

  Number of parallel IO peripherals

SOC_PARLIO_TX_UNITS_PER_GROUP

  number of TX units in each group

SOC_PARLIO_RX_UNITS_PER_GROUP

  number of RX units in each group

SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH

  Number of data lines of the TX unit

SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH

  Number of data lines of the RX unit

SOC_PARLIO_TX_CLK_SUPPORT_GATING

  Support gating TX clock

SOC_PARLIO_RX_CLK_SUPPORT_GATING

  Support gating RX clock

SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT

  Support output RX clock to a GPIO

SOC_PARLIO_TRANS_BIT_ALIGN

  Support bit alignment in transaction

SOC_PARLIO_TX_SIZE_BY_DMA

  Transaction length is controlled by DMA instead of indicated by register

SOC_PARLIO_SUPPORT_SLEEP_RETENTION

  Support back up registers before sleep

SOC_MPI_MEM_BLOCKS_NUM

SOC_MPI_OPERATIONS_NUM

SOC_RSA_MAX_BIT_LEN

SOC_SHA_DMA_MAX_BUFFER_SIZE

SOC_SHA_SUPPORT_DMA

SOC_SHA_SUPPORT_RESUME

SOC_SHA_GDMA

SOC_SHA_SUPPORT_SHA1

SOC_SHA_SUPPORT_SHA224

SOC_SHA_SUPPORT_SHA256

SOC_ECC_CONSTANT_TIME_POINT_MUL

SOC_ECDSA_SUPPORT_EXPORT_PUBKEY

SOC_SDM_GROUPS

SOC_SDM_CHANNELS_PER_GROUP

SOC_SDM_CLK_SUPPORT_PLL_F80M

SOC_SDM_CLK_SUPPORT_XTAL

SOC_SPI_PERIPH_NUM

SOC_SPI_PERIPH_CS_NUM(i)

SOC_SPI_MAX_CS_NUM

SOC_SPI_MAXIMUM_BUFFER_SIZE

SOC_SPI_SUPPORT_DDRCLK

SOC_SPI_SLAVE_SUPPORT_SEG_TRANS

SOC_SPI_SUPPORT_CD_SIG

SOC_SPI_SUPPORT_CONTINUOUS_TRANS

SOC_SPI_SUPPORT_SLAVE_HD_VER2

SOC_SPI_SUPPORT_SLEEP_RETENTION

SOC_SPI_SUPPORT_CLK_XTAL

SOC_SPI_SUPPORT_CLK_PLL_F160M

SOC_SPI_SUPPORT_CLK_RC_FAST

SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)

SOC_MEMSPI_IS_INDEPENDENT

SOC_SPI_MAX_PRE_DIVIDER

SOC_SPIRAM_XIP_SUPPORTED

SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE

SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND

SOC_SPI_MEM_SUPPORT_AUTO_RESUME

SOC_SPI_MEM_SUPPORT_IDLE_INTR

SOC_SPI_MEM_SUPPORT_SW_SUSPEND

SOC_SPI_MEM_SUPPORT_CHECK_SUS

SOC_SPI_MEM_SUPPORT_WRAP

SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED

SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED

SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED

SOC_MEMSPI_FLASH_CLK_SRC_IS_INDEPENDENT

SOC_SYSTIMER_COUNTER_NUM

SOC_SYSTIMER_ALARM_NUM

SOC_SYSTIMER_BIT_WIDTH_LO

SOC_SYSTIMER_BIT_WIDTH_HI

SOC_SYSTIMER_FIXED_DIVIDER

SOC_SYSTIMER_SUPPORT_RC_FAST

SOC_SYSTIMER_INT_LEVEL

SOC_SYSTIMER_ALARM_MISS_COMPENSATE

SOC_SYSTIMER_SUPPORT_ETM

SOC_LP_TIMER_BIT_WIDTH_LO

SOC_LP_TIMER_BIT_WIDTH_HI

SOC_TIMER_GROUPS

SOC_TIMER_GROUP_TIMERS_PER_GROUP

SOC_TIMER_GROUP_COUNTER_BIT_WIDTH

SOC_TIMER_GROUP_SUPPORT_XTAL

SOC_TIMER_GROUP_SUPPORT_RC_FAST

SOC_TIMER_GROUP_TOTAL_TIMERS

SOC_TIMER_SUPPORT_ETM

SOC_TIMER_SUPPORT_SLEEP_RETENTION

SOC_MWDT_SUPPORT_SLEEP_RETENTION

SOC_EFUSE_ECDSA_KEY

SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY

  Key manager responsible to deploy ECDSA key

SOC_KEY_MANAGER_FE_KEY_DEPLOY

  Key manager responsible to deploy Flash Encryption key

SOC_SECURE_BOOT_V2_ECC

SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS

SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS

SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY

SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX

SOC_FLASH_ENCRYPTION_XTS_AES

SOC_FLASH_ENCRYPTION_XTS_AES_128

SOC_APM_CTRL_FILTER_SUPPORTED

  Support for APM control filter

SOC_APM_LP_APM0_SUPPORTED

  Support for LP APM0 control filter

SOC_CRYPTO_DPA_PROTECTION_SUPPORTED

SOC_UART_NUM

SOC_UART_HP_NUM

SOC_UART_LP_NUM

SOC_UART_FIFO_LEN

  The UART hardware FIFO length

SOC_LP_UART_FIFO_LEN

  The LP UART hardware FIFO length

SOC_UART_BITRATE_MAX

  Max bit rate supported by UART

SOC_UART_SUPPORT_PLL_F80M_CLK

  Support PLL_F80M as the clock source

SOC_UART_SUPPORT_RTC_CLK

  Support RTC clock as the clock source

SOC_UART_SUPPORT_XTAL_CLK

  Support XTAL clock as the clock source

SOC_UART_SUPPORT_WAKEUP_INT

  Support UART wakeup interrupt

SOC_UART_HAS_LP_UART

  Support LP UART

SOC_UART_SUPPORT_SLEEP_RETENTION

  Support back up registers before sleep

SOC_UART_SUPPORT_FSM_TX_WAIT_SEND

SOC_UHCI_NUM

SOC_COEX_HW_PTI

SOC_EXTERNAL_COEX_ADVANCE

  HARDWARE EXTERNAL COEXISTENCE CAPS

SOC_EXTERNAL_COEX_LEADER_TX_LINE

  EXTERNAL COEXISTENCE TX LINE CAPS

SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH

SOC_PM_SUPPORT_WIFI_WAKEUP

SOC_PM_SUPPORT_BEACON_WAKEUP

SOC_PM_SUPPORT_BT_WAKEUP

SOC_PM_SUPPORT_EXT1_WAKEUP

SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN

  Supports one bit per pin to configure the EXT1 trigger level

SOC_PM_SUPPORT_CPU_PD

SOC_PM_SUPPORT_MODEM_PD

SOC_PM_SUPPORT_XTAL32K_PD

SOC_PM_SUPPORT_RC32K_PD

SOC_PM_SUPPORT_RC_FAST_PD

SOC_PM_SUPPORT_VDDSDIO_PD

SOC_PM_SUPPORT_TOP_PD

SOC_PM_SUPPORT_HP_AON_PD

SOC_PM_SUPPORT_MAC_BB_PD

SOC_PM_SUPPORT_RTC_PERIPH_PD

SOC_PM_SUPPORT_PMU_MODEM_STATE

MAC_SUPPORT_PMU_MODEM_STATE

SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY

  Supports CRC only the stub code in RTC memory

SOC_PM_CPU_RETENTION_BY_SW

SOC_PM_MODEM_RETENTION_BY_REGDMA

SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN

SOC_PM_PAU_LINK_NUM

SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE

SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC

SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE

SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED

SOC_PM_RETENTION_MODULE_NUM

SOC_CLK_RC_FAST_SUPPORT_CALIBRATION

SOC_MODEM_CLOCK_IS_INDEPENDENT

SOC_CLK_XTAL32K_SUPPORTED

  Support to connect an external low frequency crystal

SOC_CLK_OSC_SLOW_SUPPORTED

  Support to connect an external oscillator, not a crystal

SOC_CLK_LP_FAST_SUPPORT_XTAL

  Support XTAL clock as the LP_FAST clock source

SOC_RCC_IS_INDEPENDENT

  Reset and Clock Control is independent, thanks to the PCR registers

SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC

SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL

SOC_TEMPERATURE_SENSOR_INTR_SUPPORT

SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION

SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN

SOC_WIFI_HW_TSF

  Support hardware TSF

SOC_WIFI_FTM_SUPPORT

SOC_WIFI_GCMP_SUPPORT

  Support GCMP(GCMP128 and GCMP256)

SOC_WIFI_WAPI_SUPPORT

  Support WAPI

SOC_WIFI_TXOP_SUPPORT

  Support TXOP

SOC_WIFI_CSI_SUPPORT

  Support CSI

SOC_WIFI_MESH_SUPPORT

  Support WIFI MESH

SOC_WIFI_HE_SUPPORT

  Support Wi-Fi 6

SOC_WIFI_SUPPORT_5G

  Support 5G

SOC_WIFI_MAC_VERSION_NUM

  Wi-Fi MAC version num is 3

SOC_WIFI_NAN_SUPPORT

  Support WIFI Aware (NAN)

SOC_BLE_SUPPORTED

  Support Bluetooth Low Energy hardware

SOC_BLE_MESH_SUPPORTED

  Support BLE MESH

SOC_ESP_NIMBLE_CONTROLLER

  Support BLE EMBEDDED controller V1

SOC_BLE_50_SUPPORTED

  Support Bluetooth 5.0

SOC_BLE_DEVICE_PRIVACY_SUPPORTED

  Support BLE device privacy mode

SOC_BLE_POWER_CONTROL_SUPPORTED

  Support Bluetooth Power Control

SOC_BLE_MULTI_CONN_OPTIMIZATION

  Support multiple connections optimization

SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED

  Support For BLE Periodic Adv Enhancements

SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR

  LP Core interrupts all map to a single entry in vector table

SOC_LP_CORE_SUPPORT_ETM

  LP Core supports ETM

Was this page helpful?

- Thank you! We received your feedback.
- If you have any comments, fill in Espressif Documentation Feedback Form.

- We value your feedback.
- Let us know how we can improve this page by filling in Espressif Documentation Feedback Form.