# SoC Capability Macros

[中文]

Different models of ESP chips integrate various hardware modules. Even the same type of module may have subtle differences across different chips. ESP-IDF provides a small "database" to describe the differences between chips (please note, only differences are described, not commonalities). The contents of this "database" are defined as macros in the soc/soc_caps.h file, referred to as SoC capability macros. Users can utilize these macros in their code with conditional compilation directives (such as `#if`) to control which code is actually compiled.

Note

Please note that the contents of soc/soc_caps.h are currently unstable and may undergo significant changes in the future.

## Using SoC Capability Macros

We recommend accessing SoC capability macros indirectly through the following macro functions:

Macro Function | Description | Example
--- | --- | ---
`SOC_IS` | Determines the chip model | `#if SOC_IS(ESP32)` checks if the chip is ESP32
`SOC_HAS` | Checks if the chip has a specific hardware module or feature | `#if SOC_HAS(DAC)` checks if the chip has a DAC module

## API Reference

### Header File

- components/soc/esp32p4/include/soc/soc_caps.h

- This header file can be included with:

  >     #include "soc/soc_caps.h"

### Macros

_SOC_CAPS_TARGET_IS_ESP32P4

SOC_ADC_SUPPORTED

SOC_ANA_CMPR_SUPPORTED

SOC_DEDICATED_GPIO_SUPPORTED

SOC_UART_SUPPORTED

SOC_GDMA_SUPPORTED

SOC_UHCI_SUPPORTED

SOC_AHB_GDMA_SUPPORTED

SOC_AXI_GDMA_SUPPORTED

SOC_DW_GDMA_SUPPORTED

SOC_DMA2D_SUPPORTED

SOC_GPTIMER_SUPPORTED

SOC_PCNT_SUPPORTED

SOC_LCDCAM_CAM_SUPPORTED

SOC_LCDCAM_I80_LCD_SUPPORTED

SOC_LCDCAM_RGB_LCD_SUPPORTED

SOC_LCD_I80_SUPPORTED

SOC_LCD_RGB_SUPPORTED

SOC_MIPI_CSI_SUPPORTED

SOC_MIPI_DSI_SUPPORTED

SOC_MCPWM_SUPPORTED

SOC_TWAI_SUPPORTED

SOC_ETM_SUPPORTED

SOC_PARLIO_SUPPORTED

SOC_PARLIO_LCD_SUPPORTED

SOC_ASYNC_MEMCPY_SUPPORTED

SOC_EMAC_SUPPORTED

SOC_USB_OTG_SUPPORTED

SOC_WIRELESS_HOST_SUPPORTED

SOC_USB_SERIAL_JTAG_SUPPORTED

SOC_TEMP_SENSOR_SUPPORTED

SOC_SUPPORTS_SECURE_DL_MODE

SOC_ULP_SUPPORTED

SOC_LP_CORE_SUPPORTED

SOC_EFUSE_KEY_PURPOSE_FIELD

SOC_EFUSE_SUPPORTED

SOC_RTC_FAST_MEM_SUPPORTED

SOC_RTC_MEM_SUPPORTED

SOC_RMT_SUPPORTED

SOC_I2S_SUPPORTED

SOC_SDM_SUPPORTED

SOC_GPSPI_SUPPORTED

SOC_LEDC_SUPPORTED

SOC_ISP_SUPPORTED

SOC_I2C_SUPPORTED

SOC_SYSTIMER_SUPPORTED

SOC_AES_SUPPORTED

SOC_MPI_SUPPORTED

SOC_SHA_SUPPORTED

SOC_HMAC_SUPPORTED

SOC_DIG_SIGN_SUPPORTED

SOC_ECC_SUPPORTED

SOC_ECC_EXTENDED_MODES_SUPPORTED

SOC_ECDSA_SUPPORTED

SOC_KEY_MANAGER_SUPPORTED

SOC_HUK_SUPPORTED

SOC_FLASH_ENC_SUPPORTED

SOC_SECURE_BOOT_SUPPORTED

SOC_BOD_SUPPORTED

SOC_VBAT_SUPPORTED

SOC_APM_SUPPORTED

SOC_PMU_SUPPORTED

SOC_PMU_PVT_SUPPORTED

SOC_PVT_EN_WITH_SLEEP

SOC_PVT_RETENTION_BY_REGDMA

SOC_DCDC_SUPPORTED

SOC_PAU_SUPPORTED

SOC_RTC_TIMER_V2_SUPPORTED

SOC_ULP_LP_UART_SUPPORTED

SOC_LP_GPIO_MATRIX_SUPPORTED

SOC_LP_PERIPHERALS_SUPPORTED

SOC_LP_I2C_SUPPORTED

SOC_LP_I2S_SUPPORTED

SOC_LP_SPI_SUPPORTED

SOC_LP_ADC_SUPPORTED

SOC_LP_VAD_SUPPORTED

SOC_LP_MAILBOX_SUPPORTED

SOC_SPIRAM_SUPPORTED

SOC_PSRAM_DMA_CAPABLE

SOC_SDMMC_HOST_SUPPORTED

SOC_CLK_TREE_SUPPORTED

SOC_ASSIST_DEBUG_SUPPORTED

SOC_DEBUG_PROBE_SUPPORTED

SOC_WDT_SUPPORTED

SOC_SPI_FLASH_SUPPORTED

SOC_TOUCH_SENSOR_SUPPORTED

SOC_RNG_SUPPORTED

SOC_GP_LDO_SUPPORTED

SOC_PPA_SUPPORTED

SOC_LIGHT_SLEEP_SUPPORTED

SOC_DEEP_SLEEP_SUPPORTED

SOC_PM_SUPPORTED

SOC_BITSCRAMBLER_SUPPORTED

SOC_SIMD_INSTRUCTION_SUPPORTED

SOC_I3C_MASTER_SUPPORTED

SOC_XTAL_SUPPORT_40M

SOC_AES_SUPPORT_DMA

SOC_AES_SUPPORT_GCM

SOC_AES_GDMA

SOC_AES_SUPPORT_AES_128

SOC_AES_SUPPORT_AES_256

SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION

SOC_ADC_RTC_CTRL_SUPPORTED

  < SAR ADC Module

SOC_ADC_DIG_CTRL_SUPPORTED

SOC_ADC_DIG_SUPPORTED_UNIT(UNIT)

SOC_ADC_DMA_SUPPORTED

SOC_ADC_PERIPH_NUM

SOC_ADC_CHANNEL_NUM(PERIPH_NUM)

SOC_ADC_MAX_CHANNEL_NUM

SOC_ADC_ATTEN_NUM

  Digital

SOC_ADC_DIGI_CONTROLLER_NUM

SOC_ADC_PATT_LEN_MAX

  Four pattern tables, each contains 4 items. Each item takes 1 byte

SOC_ADC_DIGI_MAX_BITWIDTH

SOC_ADC_DIGI_MIN_BITWIDTH

SOC_ADC_DIGI_IIR_FILTER_NUM

SOC_ADC_DIGI_MONITOR_NUM

SOC_ADC_DIGI_RESULT_BYTES

SOC_ADC_DIGI_DATA_BYTES_PER_CONV

  F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095

SOC_ADC_SAMPLE_FREQ_THRES_HIGH

SOC_ADC_SAMPLE_FREQ_THRES_LOW

  RTC

SOC_ADC_RTC_MIN_BITWIDTH

SOC_ADC_RTC_MAX_BITWIDTH

  Calibration

SOC_ADC_CALIBRATION_V1_SUPPORTED

  support HW offset calibration version 1

SOC_ADC_SELF_HW_CALI_SUPPORTED

  support HW offset self calibration

SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED

  support channel compensation to the HW offset calibration ADC power control is shared by PWDET, TempSensor

SOC_ADC_SHARED_POWER

SOC_APB_BACKUP_DMA

SOC_BROWNOUT_RESET_SUPPORTED

SOC_SHARED_IDCACHE_SUPPORTED

SOC_CACHE_WRITEBACK_SUPPORTED

SOC_CACHE_FREEZE_SUPPORTED

SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE

SOC_CPU_CORES_NUM

SOC_CPU_INTR_NUM

SOC_CPU_HAS_FLEXIBLE_INTC

SOC_INT_CLIC_SUPPORTED

SOC_INT_HW_NESTED_SUPPORTED

SOC_BRANCH_PREDICTOR_SUPPORTED

SOC_CPU_COPROC_NUM

SOC_CPU_HAS_FPU

SOC_CPU_HAS_FPU_EXT_ILL_BUG

SOC_CPU_HAS_HWLOOP

SOC_CPU_HAS_HWLOOP_STATE_BUG

SOC_CPU_HAS_PIE

SOC_HP_CPU_HAS_MULTIPLE_CORES

SOC_CPU_BREAKPOINTS_NUM

SOC_CPU_WATCHPOINTS_NUM

SOC_CPU_WATCHPOINT_MAX_REGION_SIZE

SOC_CPU_HAS_PMA

SOC_CPU_IDRAM_SPLIT_USING_PMP

SOC_CPU_PMP_REGION_GRANULARITY

SOC_CPU_HAS_LOCKUP_RESET

SOC_CPU_HAS_ZC_EXTENSIONS

SOC_CPU_ZCMP_WORKAROUND

SOC_CPU_ZCMP_PUSH_REVERSED

SOC_CPU_ZCMP_POPRET_ISSUE

SOC_SIMD_PREFERRED_DATA_ALIGNMENT

SOC_DS_SIGNATURE_MAX_BIT_LEN

  The maximum length of a Digital Signature in bits.

SOC_DS_KEY_PARAM_MD_IV_LENGTH

  Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes.

SOC_DS_KEY_CHECK_MAX_WAIT_US

  Maximum wait time for DS parameter decryption key. If overdue, then key error. See TRM DS chapter for more details

SOC_DMA_CAN_ACCESS_FLASH

  DMA can access Flash memory

SOC_AHB_GDMA_VERSION

SOC_GDMA_SUPPORT_CRC

SOC_GDMA_SUPPORT_ETM

SOC_GDMA_SUPPORT_SLEEP_RETENTION

SOC_GDMA_EXT_MEM_ENC_ALIGNMENT

SOC_GPIO_PORT

SOC_GPIO_PIN_COUNT

SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER

SOC_GPIO_FLEX_GLITCH_FILTER_NUM

SOC_GPIO_SUPPORT_PIN_HYS_FILTER

SOC_GPIO_SUPPORT_ETM

SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP

SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP

SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE

SOC_LP_IO_CLOCK_IS_INDEPENDENT

SOC_GPIO_VALID_GPIO_MASK

SOC_GPIO_VALID_OUTPUT_GPIO_MASK

SOC_GPIO_IN_RANGE_MAX

SOC_GPIO_OUT_RANGE_MAX

SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK

SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT

SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK

SOC_GPIO_SUPPORT_FORCE_HOLD

SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP

SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX

SOC_GPIO_CLOCKOUT_CHANNEL_NUM

SOC_CLOCKOUT_SUPPORT_CHANNEL_DIVIDER

SOC_DEBUG_PROBE_NUM_UNIT

SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH

SOC_RTCIO_PIN_COUNT

SOC_RTCIO_INPUT_OUTPUT_SUPPORTED

SOC_RTCIO_HOLD_SUPPORTED

SOC_RTCIO_WAKE_SUPPORTED

SOC_SDM_SUPPORT_SLEEP_RETENTION

SOC_ETM_SUPPORT_SLEEP_RETENTION

SOC_ANA_CMPR_NUM

SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE

SOC_ANA_CMPR_SUPPORT_ETM

SOC_I2C_NUM

SOC_HP_I2C_NUM

SOC_LP_I2C_NUM

SOC_I2C_SUPPORT_XTAL

SOC_I2C_SUPPORT_RTC

SOC_I2C_SUPPORT_10BIT_ADDR

SOC_I2C_SUPPORT_SLAVE

SOC_I2C_SLAVE_SUPPORT_BROADCAST

SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE

SOC_I2C_SUPPORT_SLEEP_RETENTION

SOC_I2S_HW_VERSION_2

SOC_I2S_SUPPORTS_ETM

SOC_I2S_SUPPORTS_APLL

SOC_I2S_SUPPORTS_PCM

SOC_I2S_SUPPORTS_PDM

SOC_I2S_SUPPORTS_PDM_TX

SOC_I2S_SUPPORTS_PCM2PDM

SOC_I2S_SUPPORTS_PDM_RX

SOC_I2S_SUPPORTS_PDM2PCM

SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER

SOC_I2S_SUPPORTS_TX_SYNC_CNT

SOC_I2S_SUPPORTS_TDM

SOC_I2S_PDM_MAX_TX_LINES

SOC_I2S_PDM_MAX_RX_LINES

SOC_LP_I2S_NUM

SOC_ISP_BF_SUPPORTED

SOC_ISP_BLC_SUPPORTED

SOC_ISP_CCM_SUPPORTED

SOC_ISP_COLOR_SUPPORTED

SOC_ISP_CROP_SUPPORTED

SOC_ISP_DEMOSAIC_SUPPORTED

SOC_ISP_DVP_SUPPORTED

SOC_ISP_LSC_SUPPORTED

SOC_ISP_SHARPEN_SUPPORTED

SOC_ISP_WBG_SUPPORTED

SOC_ISP_SHARE_CSI_BRG

SOC_ISP_AE_BLOCK_X_NUMS

SOC_ISP_AE_BLOCK_Y_NUMS

SOC_ISP_AF_WINDOW_NUMS

SOC_ISP_AWB_WINDOW_X_NUMS

SOC_ISP_AWB_WINDOW_Y_NUMS

SOC_ISP_BF_TEMPLATE_X_NUMS

SOC_ISP_BF_TEMPLATE_Y_NUMS

SOC_ISP_CCM_DIMENSION

SOC_ISP_DEMOSAIC_GRAD_RATIO_INT_BITS

SOC_ISP_DEMOSAIC_GRAD_RATIO_DEC_BITS

SOC_ISP_DEMOSAIC_GRAD_RATIO_RES_BITS

SOC_ISP_SHARPEN_TEMPLATE_X_NUMS

SOC_ISP_SHARPEN_TEMPLATE_Y_NUMS

SOC_ISP_SHARPEN_H_FREQ_COEF_INT_BITS

SOC_ISP_SHARPEN_H_FREQ_COEF_DEC_BITS

SOC_ISP_SHARPEN_H_FREQ_COEF_RES_BITS

SOC_ISP_SHARPEN_M_FREQ_COEF_INT_BITS

SOC_ISP_SHARPEN_M_FREQ_COEF_DEC_BITS

SOC_ISP_SHARPEN_M_FREQ_COEF_RES_BITS

SOC_ISP_HIST_BLOCK_X_NUMS

SOC_ISP_HIST_BLOCK_Y_NUMS

SOC_ISP_HIST_SEGMENT_NUMS

SOC_ISP_HIST_INTERVAL_NUMS

SOC_ISP_LSC_GRAD_RATIO_INT_BITS

SOC_ISP_LSC_GRAD_RATIO_DEC_BITS

SOC_ISP_LSC_GRAD_RATIO_RES_BITS

SOC_LEDC_SUPPORT_PLL_DIV_CLOCK

SOC_LEDC_SUPPORT_XTAL_CLOCK

SOC_LEDC_TIMER_NUM

SOC_LEDC_CHANNEL_NUM

SOC_LEDC_TIMER_BIT_WIDTH

SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED

SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX

SOC_LEDC_SUPPORT_FADE_STOP

SOC_LEDC_FADE_PARAMS_BIT_WIDTH

SOC_LEDC_SUPPORT_SLEEP_RETENTION

SOC_LEDC_SUPPORT_ETM

SOC_MMU_PERIPH_NUM

SOC_MMU_LINEAR_ADDRESS_REGION_NUM

SOC_MMU_DI_VADDR_SHARED

  D/I vaddr are shared

SOC_MMU_PER_EXT_MEM_TARGET

  MMU is per physical external memory target (flash, psram)

SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED

SOC_MPU_MIN_REGION_SIZE

SOC_MPU_REGIONS_MAX_NUM

SOC_MPU_REGION_RO_SUPPORTED

SOC_MPU_REGION_WO_SUPPORTED

SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE

SOC_PCNT_SUPPORT_CLEAR_SIGNAL

  Support clear signal input

SOC_RMT_MEM_WORDS_PER_CHANNEL

  Each channel owns 48 words memory (1 word = 4 Bytes)

SOC_RMT_SUPPORT_RX_PINGPONG

  Support Ping-Pong mode on RX path

SOC_RMT_SUPPORT_TX_LOOP_COUNT

  Support transmit specified number of cycles in loop mode

SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP

  Hardware support of auto-stop in loop mode

SOC_RMT_SUPPORT_DMA

  RMT peripheral can connect to DMA channel

SOC_RMT_SUPPORT_SLEEP_RETENTION

  The sleep retention feature can help back up RMT registers before sleep

SOC_MCPWM_SWSYNC_CAN_PROPAGATE

  Software sync event can be routed to its output.

SOC_MCPWM_SUPPORT_ETM

  Support ETM (Event Task Matrix)

SOC_MCPWM_SUPPORT_EVENT_COMPARATOR

  Support event comparator (based on ETM)

SOC_MCPWM_CAPTURE_CLK_FROM_GROUP

  Capture timer shares clock with other PWM timers.

SOC_MCPWM_SUPPORT_SLEEP_RETENTION

  Support back up registers before sleep.

SOC_USB_OTG_PERIPH_NUM

SOC_USB_FSLS_PHY_NUM

SOC_USB_UTMI_PHY_NUM

SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO

SOC_PM_SUPPORT_USB_WAKEUP

SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH

  Number of data lines of the TX unit

SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH

  Number of data lines of the RX unit

SOC_PARLIO_TX_CLK_SUPPORT_GATING

  Support gating TX clock

SOC_PARLIO_RX_CLK_SUPPORT_GATING

  Support gating RX clock

SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION

  Support loop transmission

SOC_PARLIO_SUPPORT_SLEEP_RETENTION

  Support back up registers before sleep

SOC_PARLIO_SUPPORT_I80_LCD

  Support to drive I80 interfaced LCD

SOC_MPI_MEM_BLOCKS_NUM

SOC_MPI_OPERATIONS_NUM

SOC_RSA_MAX_BIT_LEN

SOC_SDMMC_USE_IOMUX

  Card detect, write protect, interrupt use GPIO Matrix on all chips. Slot 0 clock/cmd/data pins use IOMUX Slot 1 clock/cmd/data pins use GPIO Matrix

SOC_SDMMC_USE_GPIO_MATRIX

SOC_SDMMC_NUM_SLOTS

SOC_SDMMC_DATA_WIDTH_MAX

SOC_SDMMC_DELAY_PHASE_NUM

SOC_SDMMC_IO_POWER_EXTERNAL

  SDMMC IO power controlled by external power supply.

SOC_SDMMC_PSRAM_DMA_CAPABLE

  SDMMC peripheral can do DMA transfer to/from PSRAM.

SOC_SDMMC_UHS_I_SUPPORTED

SOC_SHA_DMA_MAX_BUFFER_SIZE

SOC_SHA_SUPPORT_DMA

SOC_SHA_SUPPORT_RESUME

SOC_SHA_GDMA

SOC_SHA_SUPPORT_SHA1

SOC_SHA_SUPPORT_SHA224

SOC_SHA_SUPPORT_SHA256

SOC_SHA_SUPPORT_SHA384

SOC_SHA_SUPPORT_SHA512

SOC_SHA_SUPPORT_SHA512_224

SOC_SHA_SUPPORT_SHA512_256

SOC_SHA_SUPPORT_SHA512_T

SOC_ECC_CONSTANT_TIME_POINT_MUL

SOC_ECC_SUPPORT_CURVE_P384

SOC_ECDSA_SUPPORT_EXPORT_PUBKEY

SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE

SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP

SOC_ECDSA_USES_MPI

SOC_ECDSA_SUPPORT_CURVE_P384

SOC_ECDSA_SUPPORT_CURVE_SPECIFIC_KEY_PURPOSES

  Support individual key purposes for different ECDSA curves (P192, P256, P384)

SOC_SPI_PERIPH_NUM

SOC_SPI_PERIPH_CS_NUM(i)

SOC_SPI_MAX_CS_NUM

SOC_SPI_MAXIMUM_BUFFER_SIZE

SOC_SPI_SUPPORT_SLEEP_RETENTION

SOC_SPI_SUPPORT_SLAVE_HD_VER2

SOC_SPI_SLAVE_SUPPORT_SEG_TRANS

SOC_SPI_SUPPORT_DDRCLK

SOC_SPI_SUPPORT_CD_SIG

SOC_SPI_SUPPORT_OCT

SOC_SPI_SUPPORT_CLK_XTAL

SOC_SPI_SUPPORT_CLK_RC_FAST

SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)

SOC_MSPI_HAS_INDEPENT_IOMUX

SOC_MEMSPI_IS_INDEPENDENT

SOC_SPI_MAX_PRE_DIVIDER

SOC_LP_SPI_MAXIMUM_BUFFER_SIZE

SOC_SPIRAM_XIP_SUPPORTED

SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE

SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND

SOC_SPI_MEM_SUPPORT_AUTO_RESUME

SOC_SPI_MEM_SUPPORT_IDLE_INTR

SOC_SPI_MEM_SUPPORT_SW_SUSPEND

SOC_SPI_MEM_SUPPORT_CHECK_SUS

SOC_SPI_MEM_SUPPORT_TIMING_TUNING

SOC_MEMSPI_TIMING_TUNING_BY_DQS

SOC_MEMSPI_TIMING_TUNING_BY_FLASH_DELAY

SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP

SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR

SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT

SOC_SPI_MEM_FLASH_SUPPORT_HPM

  Support High Performance Mode

SOC_MEMSPI_ENCRYPTION_ALIGNMENT

  16-byte alignment restriction to mem addr and size if encryption is enabled

SOC_SYSTIMER_COUNTER_NUM

SOC_SYSTIMER_ALARM_NUM

SOC_SYSTIMER_BIT_WIDTH_LO

SOC_SYSTIMER_BIT_WIDTH_HI

SOC_SYSTIMER_FIXED_DIVIDER

SOC_SYSTIMER_SUPPORT_RC_FAST

SOC_SYSTIMER_INT_LEVEL

SOC_SYSTIMER_ALARM_MISS_COMPENSATE

SOC_SYSTIMER_SUPPORT_ETM

SOC_LP_TIMER_BIT_WIDTH_LO

SOC_LP_TIMER_BIT_WIDTH_HI

SOC_RTC_TIMER_SUPPORTED

SOC_TIMER_SUPPORT_ETM

SOC_TIMER_SUPPORT_SLEEP_RETENTION

SOC_MWDT_SUPPORT_XTAL

SOC_MWDT_SUPPORT_SLEEP_RETENTION

SOC_TOUCH_SENSOR_VERSION

  Hardware version of touch sensor

SOC_TOUCH_MIN_CHAN_ID

  Touch minimum channel number

SOC_TOUCH_MAX_CHAN_ID

  Touch maximum channel number

SOC_TOUCH_SUPPORT_SLEEP_WAKEUP

  Touch sensor supports sleep awake

SOC_TOUCH_SUPPORT_BENCHMARK

  Touch sensor supports benchmark configuration

SOC_TOUCH_SUPPORT_WATERPROOF

  Touch sensor supports waterproof

SOC_TOUCH_SUPPORT_PROX_SENSING

  Touch sensor supports proximity sensing

SOC_TOUCH_PROXIMITY_CHANNEL_NUM

  Support touch proximity channel number.

SOC_TOUCH_SAMPLE_CFG_NUM

  The sample configurations number in total, each sampler can be used to sample on one frequency

SOC_TWAI_CONTROLLER_NUM

SOC_TWAI_MASK_FILTER_NUM

SOC_TWAI_SUPPORT_SLEEP_RETENTION

SOC_EFUSE_DIS_PAD_JTAG

SOC_EFUSE_DIS_USB_JTAG

SOC_EFUSE_DIS_DIRECT_BOOT

SOC_EFUSE_SOFT_DIS_JTAG

SOC_EFUSE_DIS_DOWNLOAD_MSPI

SOC_EFUSE_ECDSA_KEY

SOC_EFUSE_XTS_AES_KEY_128

SOC_EFUSE_XTS_AES_KEY_256

SOC_EFUSE_ECDSA_KEY_P192

SOC_EFUSE_ECDSA_KEY_P384

SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT

  Key manager supports key deployment

SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY

  Key manager responsible to deploy ECDSA key

SOC_KEY_MANAGER_FE_KEY_DEPLOY

  Key manager responsible to deploy Flash Encryption key

SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128

  Key manager responsible to deploy the XTS-AES-128 key

SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256

  Key manager responsible to deploy the XTS-AES-256 key

SOC_KEY_MANAGER_HMAC_KEY_DEPLOY

  Key manager responsible to deploy HMAC key

SOC_KEY_MANAGER_DS_KEY_DEPLOY

  Key manager responsible to deploy DS key

SOC_SECURE_BOOT_V2_RSA

SOC_SECURE_BOOT_V2_ECC

SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS

SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS

SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY

SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX

SOC_FLASH_ENCRYPTION_XTS_AES

SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS

SOC_FLASH_ENCRYPTION_XTS_AES_128

SOC_FLASH_ENCRYPTION_XTS_AES_256

SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND

  Only available in chip version above 3.0

SOC_FLASH_ENCRYPTION_PAGE_CONFIGURABLE

SOC_PSRAM_ENCRYPTION_SEPARATE_KEY

SOC_PSRAM_ENCRYPTION_PAGE_CONFIGURABLE

SOC_RECOVERY_BOOTLOADER_SUPPORTED

SOC_UART_NUM

SOC_UART_HP_NUM

SOC_UART_LP_NUM

SOC_UART_FIFO_LEN

  The UART hardware FIFO length

SOC_LP_UART_FIFO_LEN

  The LP UART hardware FIFO length

SOC_UART_BITRATE_MAX

  Max bit rate supported by UART

SOC_UART_SUPPORT_RTC_CLK

  Support RTC clock as the clock source

SOC_UART_SUPPORT_XTAL_CLK

  Support XTAL clock as the clock source

SOC_UART_SUPPORT_WAKEUP_INT

  Support UART wakeup interrupt

SOC_UART_HAS_LP_UART

  Support LP UART

SOC_UART_SUPPORT_SLEEP_RETENTION

  Support back up registers before sleep

SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN

SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE

SOC_UART_WAKEUP_SUPPORT_FIFO_THRESH_MODE

SOC_UART_WAKEUP_SUPPORT_START_BIT_MODE

SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE

SOC_LP_I2S_SUPPORT_VAD

SOC_UHCI_NUM

SOC_COEX_HW_PTI

SOC_PHY_DIG_REGS_MEM_SIZE

SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH

SOC_PM_SUPPORT_EXT1_WAKEUP

SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN

  Supports one bit per pin to configure the EXT1 trigger level

SOC_PM_EXT1_WAKEUP_BY_PMU

SOC_PM_SUPPORT_WIFI_WAKEUP

SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP

  Supports waking up from touch pad trigger

SOC_PM_SUPPORT_LP_UART_WAKEUP

SOC_PM_SUPPORT_CPU_PD

SOC_PM_SUPPORT_XTAL32K_PD

SOC_PM_SUPPORT_RC32K_PD

SOC_PM_SUPPORT_RC_FAST_PD

SOC_PM_SUPPORT_VDDSDIO_PD

SOC_PM_SUPPORT_TOP_PD

SOC_PM_SUPPORT_CNNT_PD

SOC_PM_SUPPORT_RTC_PERIPH_PD

SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY

  Supports CRC only the stub code in RTC memory

SOC_PM_CPU_RETENTION_BY_SW

SOC_PM_FPU_RETENTION_BY_SW

SOC_PM_CACHE_RETENTION_BY_PAU

SOC_PM_PAU_LINK_NUM

SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR

SOC_PAU_IN_TOP_DOMAIN

SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE

SOC_SLEEP_SYSTIMER_STALL_WORKAROUND

SOC_SLEEP_TGWDT_STOP_WORKAROUND

SOC_PM_RETENTION_MODULE_NUM

SOC_CLK_RC_FAST_SUPPORT_CALIBRATION

SOC_CLK_APLL_SUPPORTED

  Support Audio PLL

SOC_CLK_MPLL_SUPPORTED

  Support MSPI PLL

SOC_CLK_XTAL32K_SUPPORTED

  Support to connect an external low frequency crystal

SOC_CLK_RC32K_SUPPORTED

  Support an internal 32kHz RC oscillator

SOC_CLK_LP_FAST_SUPPORT_LP_PLL

  Support LP_PLL clock as the LP_FAST clock source

SOC_CLK_LP_FAST_SUPPORT_XTAL

  Support XTAL clock as the LP_FAST clock source

SOC_PERIPH_CLK_CTRL_SHARED

  Peripheral clock control (e.g. set clock source) is shared between various peripherals

SOC_TEMPERATURE_SENSOR_INTR_SUPPORT

SOC_TSENS_IS_INDEPENDENT_FROM_ADC

  Temperature sensor is a separate module, not share regs with ADC

SOC_TEMPERATURE_SENSOR_SUPPORT_ETM

SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION

SOC_MEM_SPM_SUPPORTED

SOC_ASYNCHRONOUS_BUS_ERROR_MODE

SOC_EMAC_IEEE1588V2_SUPPORTED

  EMAC Supports IEEE1588v2 time stamping

SOC_EMAC_USE_MULTI_IO_MUX

  Multiple GPIO pad options exist to connect EMAC signal via IO_MUX

SOC_EMAC_MII_USE_GPIO_MATRIX

  EMAC MII signals are connected to GPIO pads via GPIO Matrix

SOC_EMAC_SUPPORT_SLEEP_RETENTION

  EMAC supports register backup/restore in sleep mode

SOC_JPEG_CODEC_SUPPORTED

SOC_JPEG_DECODE_SUPPORTED

SOC_JPEG_ENCODE_SUPPORTED

SOC_H264_ENCODER_SUPPORTED

SOC_LCDCAM_CAM_SUPPORT_RGB_YUV_CONV

SOC_LCDCAM_LCD_SUPPORT_SLEEP_RETENTION

  Support back up registers before sleep

SOC_I3C_MASTER_PERIPH_NUM

SOC_I3C_MASTER_ADDRESS_TABLE_NUM

SOC_I3C_MASTER_COMMAND_TABLE_NUM

SOC_LP_CORE_SUPPORT_ETM

  LP Core supports ETM

SOC_LP_CORE_SUPPORT_LP_ADC

  LP ADC can be accessed from the LP-Core

SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS

  LP Core will raise exceptions if accessing invalid addresses

SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED

  LP UART wakeup source is kept triggered

SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE

  LP core requests sleep, PMU clears both HP and LP wakeup causes

### Header File

- components/soc/include/soc/soc_caps_eval.h

- This header file can be included with:

  >     #include "soc/soc_caps_eval.h"

### Macros

_SOC_CAPS_EVAL(_name)

  SOC Capability evaluation helpers

  These macros provide a standardized way to query SOC capabilities without directly accessing the macros in soc_caps.h.

  The main categories of macros are:

  - SOC_IS : Check if the SOC is a specific target (e.g., SOC_IS(ESP32S3))

  - SOC_MODULE_ATTR : Get a specific attribute of a module (e.g., SOC_MODULE_ATTR(GPTIMER, NUM))

  - SOC_MODULE_SUPPORT : Check if a module supports a feature (e.g., SOC_MODULE_SUPPORT(GPTIMER, ETM))

SOC_HAS(_module)

SOC_IS(_target)

SOC_MODULE_ATTR(_module, _attr)

SOC_MODULE_SUPPORT(_module, _feat)

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