# 时钟树

[English]

ESP32 的时钟子系统用于从一系列根时钟中提取并分配系统/模块时钟。时钟树驱动程序负责维护系统时钟的基本功能，并管理模块时钟间的复杂关系。

本文档首先介绍了根时钟和模块时钟，随后介绍了可供用户调用的时钟树 API，调用这些 API，可以监测模块时钟的运行状态。

## 简介

本节列出了 ESP32 支持的根时钟和模块时钟的定义，这些定义通常用于驱动程序配置，有助于为外设选择合适的时钟源。

### 根时钟

根时钟会产生可靠的时钟信号，经各种门、复用器、分频器或倍频器传递，这些时钟信号最终成为 CPU 内核、Wi-Fi、蓝牙、RTC 及外设等功能模块的时钟源。

ESP32 的根时钟列在 `soc_root_clk_t` 中：

> - 内部 8 MHz RC 振荡器 (RC_FAST)

>   > 此 RC 振荡器可产生约 8.5 MHz 的时钟信号输出，标识为 `RC_FAST_CLK`。

>   > 此约 8.5 MHz 的信号也会传入可配置的分频器，默认情况下，该分频器会将输入的时钟频率分频 256 倍，生成信号 `RC_FAST_D256_CLK`。

>   > 在运行时，通过在 `RC_FAST_D256_CLK` 上校准，可以计算 `RC_FAST_CLK` 的实际频率。

> - 外部 2 ~ 40 MHz 晶振 (XTAL)

> - 内部 150 kHz RC 振荡器 (RC_SLOW)

>   > 此 RC 振荡器产生约 150 kHz 的时钟信号输出，标识为 `RC_SLOW_CLK`。在运行时，通过校准，可以计算该时钟信号的实际频率。

> - 外部 32 kHz 晶振 - 可选 (XTAL32K)

>   > `XTAL32K_CLK` 的时钟源可以是连接到 `32K_XP` 和 `32K_XN` 管脚的 32 kHz 晶振，也可以是外部电路生成的 32 kHz 时钟信号。如果使用外部电路生成的时钟信号，该信号必须连接到 `32K_XN` 管脚，并且在 `32K_XP` 管脚和地之间连接一个 1 nF 的电容。此时，`32K_XP` 管脚不能用作 GPIO 管脚。

>   > 通过校准，可以计算 `XTAL32K_CLK` 的实际频率。

与晶振产生的信号相比，从 RC 振荡器电路产生的信号通常精度较低，且容易受环境影响。因此，ESP32 为 `RTC_SLOW_CLK` 提供了几种时钟源选项，可以根据对系统时间精度和对功耗的要求选择。更多详情，请参阅 RTC 定时器时钟源。

### 模块时钟

ESP32 的可用模块时钟在 `soc_module_clk_t` 中列出，每个模块时钟都有其唯一 ID。查阅文档中的枚举值，即可获取各模块时钟的详细信息。

## 使用 API

时钟树驱动程序提供了一个一体化接口，可以获取模块时钟的频率，即 `esp_clk_tree_src_get_freq_hz()`。通过该函数，你可以在任何时刻，通过提供时钟名称 `soc_module_clk_t` 和指定返回频率值的精度级别 `esp_clk_tree_src_freq_precision_t`，获取时钟频率。

## API 参考

### Header File

- components/soc/esp32/include/soc/clk_tree_defs.h

- This header file can be included with:

  >     #include "soc/clk_tree_defs.h"

### Macros

SOC_CLK_RC_FAST_FREQ_APPROX

  Approximate RC_FAST_CLK frequency in Hz

SOC_CLK_RC_SLOW_FREQ_APPROX

  Approximate RC_SLOW_CLK frequency in Hz

SOC_CLK_RC_FAST_D256_FREQ_APPROX

  Approximate RC_FAST_D256_CLK frequency in Hz

SOC_CLK_XTAL32K_FREQ_APPROX

  Approximate XTAL32K_CLK frequency in Hz

SOC_GPTIMER_CLKS

  Array initializer for all supported clock sources of GPTimer.

  The following code can be used to iterate all possible clocks:

      soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
      for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
          soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
      // Test GPTimer with the clock `clk`
      }

SOC_LCD_CLKS

  Array initializer for all supported clock sources of LCD.

SOC_RMT_CLKS

  Array initializer for all supported clock sources of RMT.

SOC_PCNT_CLKS

  Array initializer for all supported clock sources of PCNT.

SOC_UART_CLKS

  Array initializer for all supported clock sources of UART.

SOC_MCPWM_TIMER_CLKS

  Array initializer for all supported clock sources of MCPWM Timer.

SOC_MCPWM_CAPTURE_CLKS

  Array initializer for all supported clock sources of MCPWM Capture Timer.

SOC_MCPWM_CARRIER_CLKS

  Array initializer for all supported clock sources of MCPWM Carrier.

SOC_I2S_CLKS

  Array initializer for all supported clock sources of I2S.

SOC_I2C_CLKS

  Array initializer for all supported clock sources of I2C.

SOC_SPI_CLKS

  Array initializer for all supported clock sources of SPI.

SOC_SDM_CLKS

  Array initializer for all supported clock sources of SDM.

SOC_DAC_DIGI_CLKS

  Array initializer for all supported clock sources of DAC digital controller.

SOC_DAC_COSINE_CLKS

  Array initializer for all supported clock sources of DAC cosine wave generator.

SOC_TWAI_CLKS

  Array initializer for all supported clock sources of TWAI.

SOC_ADC_DIGI_CLKS

  Array initializer for all supported clock sources of ADC digital controller.

SOC_ADC_RTC_CLKS

  Array initializer for all supported clock sources of ADC RTC controller.

SOC_MWDT_CLKS

  Array initializer for all supported clock sources of MWDT.

SOC_LEDC_CLKS

  Array initializer for all supported clock sources of LEDC.

SOC_LEDC_CLK_STRS

SOC_SDMMC_CLKS

  Array initializer for all supported clock sources of SDMMC.

### Enumerations

enum soc_root_clk_t

  Root clock.

  Values:

  enumerator SOC_ROOT_CLK_INT_RC_FAST

    Internal 8MHz RC oscillator

  enumerator SOC_ROOT_CLK_INT_RC_SLOW

    Internal 150kHz RC oscillator

  enumerator SOC_ROOT_CLK_EXT_XTAL

    External 2~40MHz crystal

  enumerator SOC_ROOT_CLK_EXT_XTAL32K

    External 32kHz crystal/clock signal

enum soc_root_clk_circuit_t

  ROOT clock circuit, which requires explicitly enabling the targeting circuit to use.

  Values:

  enumerator SOC_ROOT_CIRCUIT_CLK_BBPLL

    BBPLL_CLK is the output of the BBPLL generator circuit

  enumerator SOC_ROOT_CIRCUIT_CLK_APLL

    APLL_CLK is the output of the APLL generator circuit

enum soc_cpu_clk_src_t

  CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK.

  备注

  Enum values are matched with the register field values on purpose

  Values:

  enumerator SOC_CPU_CLK_SRC_XTAL

    Select XTAL_CLK as CPU_CLK source

  enumerator SOC_CPU_CLK_SRC_PLL

    Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 480MHz or 320MHz)

  enumerator SOC_CPU_CLK_SRC_RC_FAST

    Select RC_FAST_CLK as CPU_CLK source

  enumerator SOC_CPU_CLK_SRC_APLL

    Select APLL_CLK as CPU_CLK source

  enumerator SOC_CPU_CLK_SRC_INVALID

    Invalid CPU_CLK source

enum soc_rtc_slow_clk_src_t

  RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK.

  备注

  Enum values are matched with the register field values on purpose

  Values:

  enumerator SOC_RTC_SLOW_CLK_SRC_RC_SLOW

    Select RC_SLOW_CLK as RTC_SLOW_CLK source

  enumerator SOC_RTC_SLOW_CLK_SRC_XTAL32K

    Select XTAL32K_CLK as RTC_SLOW_CLK source

  enumerator SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256

    Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source

  enumerator SOC_RTC_SLOW_CLK_SRC_INVALID

    Invalid RTC_SLOW_CLK source

  enumerator SOC_RTC_SLOW_CLK_SRC_DEFAULT

    RC_SLOW_CLK is the default clock source for RTC_SLOW_CLK

enum soc_rtc_fast_clk_src_t

  RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK.

  备注

  Enum values are matched with the register field values on purpose

  Values:

  enumerator SOC_RTC_FAST_CLK_SRC_XTAL_D4

    Select XTAL_D4_CLK (may referred as XTAL_CLK_DIV_4) as RTC_FAST_CLK source

  enumerator SOC_RTC_FAST_CLK_SRC_RC_FAST

    Select RC_FAST_CLK as RTC_FAST_CLK source

  enumerator SOC_RTC_FAST_CLK_SRC_INVALID

    Invalid RTC_FAST_CLK source

  enumerator SOC_RTC_FAST_CLK_SRC_DEFAULT

    XTAL_D4_CLK is the default clock source for RTC_FAST_CLK

  enumerator SOC_RTC_FAST_CLK_SRC_XTAL_DIV

    Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D4`

enum soc_xtal_freq_t

  Possible main XTAL frequency options on the target.

  备注

  Enum values equal to the frequency value in MHz

  备注

  Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for the supported ones.

  Values:

  enumerator SOC_XTAL_FREQ_AUTO

    Automatic XTAL frequency detention

  enumerator SOC_XTAL_FREQ_24M

    24MHz XTAL

  enumerator SOC_XTAL_FREQ_26M

    26MHz XTAL

  enumerator SOC_XTAL_FREQ_40M

    40MHz XTAL

enum soc_module_clk_t

  Supported clock sources for modules (CPU, peripherals, RTC, etc.)

  备注

  enum starts from 1, to save 0 for special purpose

  Values:

  enumerator SOC_MOD_CLK_CPU

    CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or APLL by configuring soc_cpu_clk_src_t

  enumerator SOC_MOD_CLK_RTC_FAST

    RTC_FAST_CLK can be sourced from XTAL_D4 or RC_FAST by configuring soc_rtc_fast_clk_src_t

  enumerator SOC_MOD_CLK_RTC_SLOW

    RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t

  enumerator SOC_MOD_CLK_APB

    APB_CLK is highly dependent on the CPU_CLK source

  enumerator SOC_MOD_CLK_PLL_D2

    PLL_D2_CLK is derived from PLL, it has a fixed divider of 2

  enumerator SOC_MOD_CLK_PLL_F160M

    PLL_F160M_CLK is derived from PLL, and has a fixed frequency of 160MHz

  enumerator SOC_MOD_CLK_XTAL32K

    XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals

  enumerator SOC_MOD_CLK_RC_FAST

    RC_FAST_CLK comes from the internal 8MHz rc oscillator, passing a clock gating to the peripherals

  enumerator SOC_MOD_CLK_RC_FAST_D256

    RC_FAST_D256_CLK comes from the internal 8MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals

  enumerator SOC_MOD_CLK_XTAL

    XTAL_CLK comes from the external crystal (2~40MHz)

  enumerator SOC_MOD_CLK_REF_TICK

    REF_TICK is derived from APB, it has a fixed frequency of 1MHz even when APB frequency changes

  enumerator SOC_MOD_CLK_APLL

    APLL is sourced from PLL, and its frequency is configurable through APLL configuration registers

  enumerator SOC_MOD_CLK_INVALID

    Indication of the end of the available module clock sources

enum soc_periph_systimer_clk_src_t

  Type of SYSTIMER clock source.

  Values:

  enumerator SYSTIMER_CLK_SRC_XTAL

    SYSTIMER source clock is XTAL

  enumerator SYSTIMER_CLK_SRC_DEFAULT

    SYSTIMER source clock default choice is XTAL

enum soc_periph_gptimer_clk_src_t

  Type of GPTimer clock source.

  Values:

  enumerator GPTIMER_CLK_SRC_APB

    Select APB as the source clock

  enumerator GPTIMER_CLK_SRC_DEFAULT

    Select APB as the default choice

enum soc_periph_lcd_clk_src_t

  Type of LCD clock source.

  Values:

  enumerator LCD_CLK_SRC_PLL160M

    Select PLL_160M as the source clock

  enumerator LCD_CLK_SRC_DEFAULT

    Select PLL_160M as the default choice

enum soc_periph_rmt_clk_src_t

  Type of RMT clock source.

  Values:

  enumerator RMT_CLK_SRC_APB

    Select APB as the source clock

  enumerator RMT_CLK_SRC_REF_TICK

    Select REF_TICK as the source clock

  enumerator RMT_CLK_SRC_DEFAULT

    Select APB as the default choice

enum soc_periph_pcnt_clk_src_t

  Type of PCNT clock source.

  Values:

  enumerator PCNT_CLK_SRC_APB

    Select APB as the source clock

  enumerator PCNT_CLK_SRC_DEFAULT

    Select APB as the default choice

enum soc_periph_uart_clk_src_legacy_t

  Type of UART clock source, reserved for the legacy UART driver.

  Values:

  enumerator UART_SCLK_APB

    UART source clock is APB CLK

  enumerator UART_SCLK_REF_TICK

    UART source clock is REF_TICK

  enumerator UART_SCLK_DEFAULT

    UART source clock default choice is APB

enum soc_periph_mcpwm_timer_clk_src_t

  Type of MCPWM timer clock source.

  Values:

  enumerator MCPWM_TIMER_CLK_SRC_PLL160M

    Select PLL_F160M as the source clock

  enumerator MCPWM_TIMER_CLK_SRC_DEFAULT

    Select PLL_F160M as the default clock choice

enum soc_periph_mcpwm_capture_clk_src_t

  Type of MCPWM capture clock source.

  Values:

  enumerator MCPWM_CAPTURE_CLK_SRC_APB

    Select APB as the source clock

  enumerator MCPWM_CAPTURE_CLK_SRC_DEFAULT

    Select APB as the default clock choice

enum soc_periph_mcpwm_carrier_clk_src_t

  Type of MCPWM carrier clock source.

  Values:

  enumerator MCPWM_CARRIER_CLK_SRC_PLL160M

    Select PLL_F160M as the source clock

  enumerator MCPWM_CARRIER_CLK_SRC_DEFAULT

    Select PLL_F160M as the default clock choice

enum soc_periph_i2s_clk_src_t

  I2S clock source enum.

  Values:

  enumerator I2S_CLK_SRC_DEFAULT

    Select PLL_F160M as the default source clock

  enumerator I2S_CLK_SRC_PLL_160M

    Select PLL_F160M as the source clock

  enumerator I2S_CLK_SRC_APLL

    Select APLL as the source clock

enum soc_periph_i2c_clk_src_t

  Type of I2C clock source.

  Values:

  enumerator I2C_CLK_SRC_APB
  enumerator I2C_CLK_SRC_DEFAULT

enum soc_periph_spi_clk_src_t

  Type of SPI clock source.

  Values:

  enumerator SPI_CLK_SRC_DEFAULT

    Select APB as SPI source clock

  enumerator SPI_CLK_SRC_APB

    Select APB as SPI source clock

enum soc_periph_sdm_clk_src_t

  Sigma Delta Modulator clock source.

  Values:

  enumerator SDM_CLK_SRC_APB

    Select APB as the source clock

  enumerator SDM_CLK_SRC_DEFAULT

    Select APB as the default clock choice

enum soc_periph_dac_digi_clk_src_t

  DAC digital controller clock source.

  Values:

  enumerator DAC_DIGI_CLK_SRC_PLLD2

    Select PLL_D2 as the source clock

  enumerator DAC_DIGI_CLK_SRC_APLL

    Select APLL as the source clock

  enumerator DAC_DIGI_CLK_SRC_DEFAULT

    Select PLL_D2 as the default source clock

enum soc_periph_dac_cosine_clk_src_t

  DAC cosine wave generator clock source.

  Values:

  enumerator DAC_COSINE_CLK_SRC_RTC_FAST

    Select RTC FAST as the source clock

  enumerator DAC_COSINE_CLK_SRC_DEFAULT

    Select RTC FAST as the default source clock

enum soc_periph_twai_clk_src_t

  TWAI clock source.

  Values:

  enumerator TWAI_CLK_SRC_APB

    Select APB as the source clock

  enumerator TWAI_CLK_SRC_DEFAULT

    Select APB as the default clock choice

enum soc_periph_adc_digi_clk_src_t

  ADC digital controller clock source.

  备注

  ADC DMA mode is clocked from I2S on ESP32, using `ADC_DIGI_` here for compatibility Its clock source is same as I2S

  Values:

  enumerator ADC_DIGI_CLK_SRC_PLL_F160M

    Select F160M as the source clock

  enumerator ADC_DIGI_CLK_SRC_APLL

    Select APLL as the source clock

  enumerator ADC_DIGI_CLK_SRC_DEFAULT

    Select F160M as the default clock choice

enum soc_periph_adc_rtc_clk_src_t

  ADC RTC controller clock source.

  Values:

  enumerator ADC_RTC_CLK_SRC_RC_FAST

    Select RC_FAST as the source clock

  enumerator ADC_RTC_CLK_SRC_DEFAULT

    Select RC_FAST as the default clock choice

enum soc_periph_mwdt_clk_src_t

  MWDT clock source.

  Values:

  enumerator MWDT_CLK_SRC_APB

    Select APB as the source clock

  enumerator MWDT_CLK_SRC_DEFAULT

    Select APB as the default clock choice

enum soc_periph_ledc_clk_src_legacy_t

  Type of LEDC clock source, reserved for the legacy LEDC driver.

  Values:

  enumerator LEDC_AUTO_CLK

    LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer

  enumerator LEDC_USE_APB_CLK

    Select APB as the source clock

  enumerator LEDC_USE_RC_FAST_CLK

    Select RC_FAST as the source clock

  enumerator LEDC_USE_REF_TICK

    Select REF_TICK as the source clock

enum soc_periph_sdmmc_clk_src_t

  Type of SDMMC clock source.

  Values:

  enumerator SDMMC_CLK_SRC_DEFAULT

    Select PLL_160M as the default choice

  enumerator SDMMC_CLK_SRC_PLL160M

    Select PLL_160M as the source clock

enum soc_clkout_sig_id_t

  Values:

  enumerator CLKOUT_SIG_I2S0

    I2S0 clock, depends on the i2s driver configuration

  enumerator CLKOUT_SIG_PLL

    PLL_CLK is the output of crystal oscillator frequency multiplier

  enumerator CLKOUT_SIG_RC_SLOW

    RC slow clock, depends on the RTC_CLK_SRC configuration

  enumerator CLKOUT_SIG_XTAL

    Main crystal oscillator clock

  enumerator CLKOUT_SIG_APLL

    Divided by PLL, frequency is configurable

  enumerator CLKOUT_SIG_REF_TICK

    Divided by APB clock, usually be 1MHz

  enumerator CLKOUT_SIG_PLL_F80M

    From PLL, usually be 80MHz

  enumerator CLKOUT_SIG_RC_FAST

    RC fast clock, about 8MHz

  enumerator CLKOUT_SIG_I2S1

    I2S1 clock, depends on the i2s driver configuration

  enumerator CLKOUT_SIG_INVALID

enum soc_clk_freq_calculation_src_t

  Clock frequency calculation source selection.

  Values:

  enumerator CLK_CAL_RTC_SLOW

    Select to calculate frequency of RTC_SLOW_CLK

  enumerator CLK_CAL_RC_FAST_D256

    Select to calculate frequency of RC_FAST_D256_CLK

  enumerator CLK_CAL_32K_XTAL

    Select to calculate frequency of XTAL32K_CLK

### Header File

- components/esp_hw_support/include/esp_clk_tree.h

- This header file can be included with:

  >     #include "esp_clk_tree.h"

### Functions

esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision, uint32_t *freq_value)

  Get frequency of module clock source.

  参数:

    - clk_src -- [in] Clock source available to modules, in soc_module_clk_t

    - precision -- [in] Degree of precision, one of esp_clk_tree_src_freq_precision_t values This arg only applies to the clock sources that their frequencies can vary: SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_RTC_SLOW, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_RC_FAST_D256, SOC_MOD_CLK_XTAL32K For other clock sources, this field is ignored.

    - freq_value -- [out] Frequency of the clock source, in Hz

  返回:

    - ESP_OK Success

    - ESP_ERR_INVALID_ARG Parameter error

    - ESP_FAIL Calibration failed

esp_err_t esp_clk_tree_src_set_freq_hz(soc_module_clk_t clk_src, uint32_t expt_freq_value, uint32_t *ret_freq_value)

  Set frequency of module clock source.

  参数:

    - clk_src -- [in] Clock source available to modules, in soc_module_clk_t

    - expt_freq_value -- [in] Expected frequency of the clock source, in Hz

    - ret_freq_value -- [out] Real frequency of the clock source, in Hz

  返回:

    - ESP_OK Success

    - ESP_ERR_INVALID_ARG Parameter error

    - ESP_ERR_NOT_SUPPORTED Unsupported clock source

### Enumerations

enum esp_clk_tree_src_freq_precision_t

  Degree of precision of frequency value to be returned by esp_clk_tree_src_get_freq_hz()

  Values:

  enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED
  enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX
  enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT
  enumerator ESP_CLK_TREE_SRC_FREQ_PRECISION_INVALID

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