Peripheral Description
Note
This document is automatically translated using AI. Please excuse any detailed errors. The official English version is still in progress.
Before developing peripherals for the ESP series chips, it is crucial to understand the core positioning of each peripheral, the rules for pin configuration, and the flexibility of pin functions (support for multiplexing/remapping). This ensures correct hardware connections and stable functionality.
This document will review the basic technical information of the peripherals built into the ESP32-P4, ESP32-C5, ESP32-C6, ESP32-C2, ESP32-H2, ESP32-S3, ESP32-S2, ESP32-C3, and ESP32 chip models, providing a technical reference for subsequent peripheral driver development. In these chips, most peripherals support pin remapping at the hardware level, with only a few peripherals having special restrictions due to hardware design architecture or functional logic characteristics. These restrictions will be individually marked in the specific description of each peripheral.
The information mentioned in the document is referenced from the datasheets of each chip. For further understanding, you can obtain the chip datasheets through the ESP Chip & Module Selector Tool.
LEDC
LEDC is a dedicated peripheral for Pulse Width Modulation (PWM), supporting multi-channel PWM signal output. It is used in scenarios that require analog signal simulation, such as adjusting LED brightness, controlling motor speed, etc. Some models, like the ESP32-C5, support high-frequency output (up to 40 MHz) and high-precision duty cycle configuration (up to 20-bit resolution). The specific frequency and precision can be flexibly chosen according to application requirements, adapting to more complex analog control needs.
Peripheral Feature Differences
Due to chip design, the peripheral features differ under different chips as follows:
Independent PWM Generators: i.e., the number of channels, usually 6~8, can output a corresponding number of independent PWM signals.
Independent Timers: usually 4, used to configure frequency and resolution, can be multiplexed by multiple PWM channels.
Duty Cycle Precision: supports up to 14~20 bits, the specific precision depends on the chip model and the used prescaler configuration.
Note
There is a trade-off between PWM frequency and precision. High-frequency output can reach hundreds of kHz, but the resolution will decrease; low-frequency output can achieve high-precision duty cycle.
Signal Lines and IO Ports
Each LEDC channel occupies one GPIO, used for PWM signal output.
Signal Line |
Function Description |
|---|---|
PWM Output |
Outputs PWM signal, drives related devices |
Pin Allocation
The pins of the LEDC peripheral can only be allocated to available GPIOs through remapping.
I2C
I2C is a dedicated peripheral for two-wire serial communication, supporting master-slave mode data transmission. It is used to connect various external devices such as sensors, memory, displays, etc., for data collection and control.
Peripheral Feature Differences
Due to chip design, the peripheral features differ under different chips as follows:
Controller Quantity: Up to two master system I2Cs, some chips may also have a low-power (LP) I2C controller.
Bus Clock Frequency: Supports standard mode (100 Kbit/s) and fast mode (400 Kbit/s), some chips can reach up to 800 Kbit/s, but it is limited by the pull-up strength on SCL and SDA.
Signal Lines and IO Ports
I2C has two signal lines, each signal line occupies one GPIO.
Signal Line |
Function Description |
|---|---|
SDA |
Data transmission, used for bidirectional communication between master and slave devices |
SCL |
Provides communication clock, controlled by the master device |
Pin Allocation
The pins of the I2C peripheral can only be assigned to available GPIOs through remapping.
SPI
SPI is a high-speed full-duplex serial communication dedicated peripheral, supporting master-slave mode data transmission, used to connect flash memory, displays, sensors and other external devices, achieving high-speed data exchange.
Peripheral Feature Differences
Due to chip design, the feature differences of peripherals under different chips are as follows:
Controller Mode: Supports memory mode, general mode, and low power mode, where memory mode is only for system use.
Number of Controllers: Up to four, including two memory SPIs (SPI0/1), some chips may also have a low power (LP) SPI controller.
Bus Clock Frequency: Supports 48MHz to 80MHz frequency in general host mode, supports 32MHz to 60MHz frequency in general slave mode, depending on the chip model and signal characteristics.
Signal Lines and IO Ports
SPI has up to 10 signal lines, each signal line occupies one GPIO. The number of GPIO pins occupied in different modes is as follows: 1-line mode occupies 2 GPIO pins, 2-line mode occupies 3 GPIO pins, 4-line mode occupies 4 GPIO pins, 8-line mode occupies 10 GPIO pins.
Note
The actual available mode depends on the specific SPI controller, some SPI peripherals do not support 8-line mode, please refer to the chip datasheet to confirm the supported modes.
Signal Line |
Function Description |
Applicable Mode |
|---|---|---|
MOSI |
Master device sends data, slave device receives |
2-line mode, 4-line mode; multiplexed with MISO in 1-line mode |
MISO |
Slave device sends data, master device receives |
2-line mode, 4-line mode; multiplexed with MISO in 1-line mode |
SCLK |
Provides communication clock, controlled by the master device |
1, 2, 4, 8-line mode |
CS |
Chip select signal, used to select the slave device |
4, 8-line mode |
IO0 to IO7 |
8 parallel data lines, each line transmits 1 bit data |
8-line mode |
Pin Allocation
The pin multiplexing and remapping of the SPI peripheral depends on the SPI mode. Memory SPI (SPI0/1), mainly used to connect Flash and PSRAM, is bound to specific IO ports by default; General SPI (SPI2 and above) on most chips supports both multiplexing and remapping for some signal lines, while some signal lines only support remapping.
UART
UART (Universal Asynchronous Receiver Transmitter) is a serial communication peripheral, supporting full-duplex data transmission, used to connect sensors, debugging terminals, external modules, etc., to achieve data transmission and control signal communication. UART can perform asynchronous communication between the host and peripherals through a standard serial protocol, supporting the configuration of baud rate, data bits, stop bits, and parity bits.
Peripheral Feature Differences
Due to chip design, the feature differences of peripherals under different chips are as follows:
Number of Controllers: Most chips provide 2 to 6 UART controllers, some chips may also support low power UART (LP UART).
Baud Rate Range: Most chips have a maximum baud rate of up to 5 MBaud, only the ESP32-C2 chip, the maximum baud rate is 2.5 MBaud. In actual applications, the baud rate may be limited by PCB wiring length, level matching, interference, and peripheral characteristics, and it may be necessary to appropriately reduce the baud rate to ensure communication stability.
Signal Lines and IO Ports
UART Depending on the chip hardware design, the number of data lines may be 2 (TX/RX) or 4 (TX/RX + RTS/CTS), occupying 2 or 4 GPIOs respectively.
Signal Line |
Function Description |
Applicable Mode |
|---|---|---|
TX |
Transmit data, sent by UART |
All UART controllers |
RX |
Receive data, received by UART |
All UART controllers |
RTS |
Request to send, used for hardware flow control |
UARTs that support hardware flow control |
CTS |
Clear to send, used for hardware flow control |
UARTs that support hardware flow control |
Pin Allocation
For UART peripherals, all signal lines support remapping, and some signal lines can also be multiplexed through IO MUX.
ADC
ADC (Analog-to-Digital Converter) is a dedicated peripheral for converting analog signals into digital signals, used for reading sensor outputs, voltage signals or other analog signals, to achieve digital processing and control. ESP series chips usually have a built-in 12-bit resolution ADC, which can optimize the measurement range and accuracy by configuring the sampling period, gain, and attenuation parameters.
Peripheral Feature Differences
Due to chip design, the feature differences of peripherals under different chips are as follows:
Number of controllers: Can be 1 or 2.
Number of channels: The differences between different chips are significant, ESP32-S3 supports analog input on 20 GPIOs, while ESP32-C2 only supports 5.
Signal Line and IO Port
Each ADC channel occupies one GPIO for analog signal input.
Signal Line |
Function Description |
|---|---|
ADCx |
Analog input signal of the corresponding channel, x represents the channel number of the ADC |
Pin Allocation
For ADC, signal pins can only be multiplexed through IO MUX and do not support remapping.
I2S
I2S (Inter-IC Sound) is a dedicated audio serial interface, used for transmitting digital audio data between the chip and audio codecs, microphones or speaker modules. I2S supports standard audio formats (such as PCM), and can achieve high-fidelity audio capture and output.
Peripheral Feature Differences
Due to chip design, the feature differences of peripherals under different chips are as follows:
Number of controllers: Most chips are only configured with 1 I2S peripheral; ESP32-S2/S3 are configured with 2; ESP32-P4 is configured with 3; while ESP32-C2 chip does not carry I2S peripheral.
Clock frequency: BCK clock is configurable, the frequency range is generally 10 kHz~40 MHz; some chips support APLL clock source (such as ESP32-P4), up to 240 MHz.
Signal Line and IO Port
There are 4 signal lines for I2S peripherals, each signal line occupies one GPIO port.
Signal Line |
Function Description |
|---|---|
WS |
Word synchronization signal, used to identify audio frames |
BCK |
Bit clock signal, provided by the master device |
DATA |
Audio data transmission |
MCLK |
Master clock signal, used for external audio device synchronization |
Pin Allocation
The pins of the I2S peripheral can only be allocated to available GPIOs through remapping.
LCD_CAM
LCD_CAM is a composite peripheral provided in the ESP series chips, offering both LCD interface and CAM interface functions through the same hardware module, sharing hardware resources.
LCD interface function: Used to drive parallel RGB LCD screens, realizing screen image refresh and display.
CAM interface function: Used to connect cameras, capture image data and transmit it to the internal memory of the chip for subsequent processing.
Peripheral feature differences
Due to chip design, the feature differences of peripherals under different chips are as follows:
Number of controllers: The ESP32-P4 and ESP32-S3 chips are equipped with the LCD_CAM peripheral, while the ESP32-S2 only has an LCD interface.
Signal lines and IO ports
The number of signal lines of the LCD_CAM peripheral depends on the selected data bit width mode, usually 14 to 30. Each signal line occupies a GPIO port.
Signal line |
Function description |
|---|---|
XCLK |
External clock input |
SDA (SCCB) |
Serial control data |
SCL (SCCB) |
Serial control clock |
IO0 to IO7 |
Camera data output, data bit width mode can be selected, here assumed to be 8-bit parallel data |
VSYNC |
Frame synchronization signal |
HREF |
Line valid signal |
PCLK |
Pixel clock, output by the camera |
Pin allocation
The pins of the LCD_CAM peripheral can only be allocated to available GPIOs through remapping.
RMT
RMT is a remote control dedicated peripheral provided by the ESP series chips, used to generate signals with precise time intervals or capture input pulses, widely used in infrared remote control, LED strip control, encoded signal analysis, and other scenarios.
Peripheral feature differences
Due to chip design, the feature differences of peripherals under different chips are as follows:
Peripheral support: Most ESP series chips provide 4 RMT channels, ESP32-P4 and ESP32-S3 provide 8 channels, ESP32-C2 does not carry RMT peripheral.
Transmit/Receive mode: RMT supports various transmission and reception modes, some channels of ESP32-P4 and ESP32-S3 can also access high-speed data through GDMA.
Signal lines and IO ports
Each RMT channel occupies a GPIO, used for transmitting or receiving pulse signals.
Signal line |
Function description |
|---|---|
CH0 to CHx |
RMT channel signals, open the corresponding number of channels according to needs |
Pin allocation
The pins of the RMT peripheral can only be allocated to available GPIOs through remapping.
USB-OTG
USB-OTG (On-The-Go) is a Universal Serial Bus peripheral provided by the ESP series chips, supporting USB device (Device) and host (Host) modes, widely used in USB peripheral connection, data transmission, peripheral charging, and other scenarios.
Peripheral feature differences
Due to chip design, the feature differences of peripherals under different chips are as follows:
Peripheral Support: Only ESP32-P4, ESP32-S2, and ESP32-S3 are equipped with USB-OTG peripherals.
Speed Mode: Most chips only support full-speed and low-speed modes, ESP32-P4 also supports high-speed OTG.
Channel Quantity: ESP32-P4 provides 15 additional endpoints in device mode and 16 host channels in host mode; ESP32-S3 provides 6 additional endpoints in device mode and 8 host channels in host mode.
Signal Line and IO Port
The USB-OTG peripheral uses 5 signal lines, each signal line occupies a GPIO. Physical connections are usually implemented through onboard Micro-USB or USB-C interfaces for data transmission and power detection.
Signal Line |
Function Description |
|---|---|
USB2 OTG PHY DP |
USB Data Positive (Differential Signal) |
USB2 OTG PHY DM |
USB Data Negative (Differential Signal) |
ID |
OTG Mode Identification, Determine Host/Device Role |
VBUS |
Power Detection or Provision, Depending on Mode |
GND |
Ground |
Pin Allocation
The differential signal pins (DP and DM) of the USB-OTG peripheral are multiplexed with IO MUX and other functions, or use dedicated pins, do not support remapping; the remaining control signals only support remapping. When the ESP32-S3 chip uses an external USB PHY, all signal lines are multiplexed through IO MUX and do not support remapping.
TWAI
TWAI is a CAN bus compatible communication interface provided by the ESP series chips, supporting vehicular and industrial bus communication, used for data exchange with sensors, controllers, and actuators on the CAN network.
Peripheral Feature Differences
Due to chip design, the feature differences of peripherals under different chips are as follows:
Number of Peripherals: Most chips usually provide 1 TWAI controller; ESP32-P4 can carry up to 3 TWAI controllers; a few chips, such as ESP32-C2, do not carry TWAI peripherals.
Signal Line and IO Port
The TWAI peripheral uses 2 signal lines, each signal line occupies a GPIO. Physical connections are usually made through the onboard CAN interface (2-pin or DB9 adapter) connected to the external CAN network to achieve bus communication.
Signal Line |
Function Description |
|---|---|
TWAI_H (CAN_H) |
CAN bus high-level signal line, used for differential transmission |
TWAI_L (CAN_L) |
CAN bus low-level signal line, forms a differential signal with TWAI_H |
Pin Allocation
The pins of the TWAI peripheral only support allocation to available GPIO through remapping.
PCNT
PCNT is a pulse counter provided by the ESP series chips, used to count the number of pulses of external signals, can be used for measuring rotary encoder pulses, key counting, or frequency statistics, etc.
Peripheral Feature Differences
Due to chip design, the feature differences of peripherals under different chips are as follows:
Number of Peripherals: ESP32-C2 and ESP32-C3 do not carry PCNT peripherals; other chips, such as ESP32-S3, provide 4 PCNT controllers.
Signal Line and IO Port
The PCNT peripheral uses 2 signal lines, each signal line occupies a GPIO.
Signal Line |
Function Description |
|---|---|
Pulse Input |
Used to receive count pulse signals |
Control Input |
Used to control the count direction or enable counting |
Pin Assignment
The pins of the PCNT peripheral can only be assigned to available GPIOs through remapping.
Touch
The Touch peripheral is a capacitive touch sensor interface provided by the ESP series chips, which can be used to detect touch or proximity signals, implementing key substitution, sliding gestures, or capacitive button applications.
Peripheral Feature Differences
Due to chip design, the feature differences of peripherals under different chips are as follows:
Number of Peripherals: 14 touch channels are provided on the ESP32, ESP32-P4, ESP32-S2, and ESP32-S3 chips.
Signal Lines and IO Ports
Each channel of the Touch peripheral occupies one GPIO, which is used for capacitive touch detection.
Signal Line |
Function Description |
|---|---|
CH0 to CHx |
Touch channel signals, open the corresponding number of channels according to needs |
Pin Allocation
The pins of the Touch peripheral only support multiplexing through IO MUX, and do not support remapping.
USB/JTAG
The USB/JTAG peripheral is a debugging and downloading interface provided by the ESP series chips, used for program downloading, debugging, and chip burning.
Peripheral Feature Differences
Due to chip design, the feature differences of peripherals under different chips are as follows:
Number of Peripherals: The ESP32-C2 and ESP32-S2 do not carry this peripheral, and the rest of the chips provide 1 USB/JTAG interface.
Signal Lines and IO Ports
The USB/JTAG peripheral uses 2 signal lines, each signal line occupies one GPIO. Physical connections are usually made through an onboard Micro-USB or a 10 to 20 pin JTAG debug header to connect to an external debugger, enabling program burning, debugging, and debugger communication.
Signal Line |
Function Description |
|---|---|
USB_D+ |
USB differential data positive |
USB_D- |
USB differential data negative |
Pin Allocation
The pins of the USB/JTAG peripheral only support multiplexing through IO MUX, and do not support remapping.