esp_hal/aes/
esp32cX.rs

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1use crate::aes::{Aes, Aes128, Aes256, AesFlavour, Mode, ALIGN_SIZE};
2
3impl Aes<'_> {
4    pub(super) fn init(&mut self) {
5        self.write_dma(false);
6    }
7
8    fn write_dma(&mut self, enable_dma: bool) {
9        self.regs()
10            .dma_enable()
11            .write(|w| w.dma_enable().bit(enable_dma));
12    }
13
14    pub(super) fn write_key(&mut self, key: &[u8]) {
15        debug_assert!(key.len() <= 8 * ALIGN_SIZE);
16        debug_assert_eq!(key.len() % ALIGN_SIZE, 0);
17        self.alignment_helper
18            .volatile_write_regset(self.regs().key(0).as_ptr(), key, 8);
19    }
20
21    pub(super) fn write_block(&mut self, block: &[u8]) {
22        debug_assert_eq!(block.len(), 4 * ALIGN_SIZE);
23        self.alignment_helper
24            .volatile_write_regset(self.regs().text_in(0).as_ptr(), block, 4);
25    }
26
27    pub(super) fn write_mode(&self, mode: Mode) {
28        self.regs().mode().write(|w| unsafe { w.bits(mode as _) });
29    }
30
31    pub(super) fn write_start(&self) {
32        self.regs().trigger().write(|w| w.trigger().set_bit());
33    }
34
35    pub(super) fn read_idle(&mut self) -> bool {
36        self.regs().state().read().state().bits() == 0
37    }
38
39    pub(super) fn read_block(&self, block: &mut [u8]) {
40        debug_assert_eq!(block.len(), 4 * ALIGN_SIZE);
41        self.alignment_helper
42            .volatile_read_regset(self.regs().text_out(0).as_ptr(), block, 4);
43    }
44}
45
46impl AesFlavour for Aes128 {
47    type KeyType<'b> = &'b [u8; 16];
48}
49
50impl AesFlavour for Aes256 {
51    type KeyType<'b> = &'b [u8; 32];
52}
esp_hal/aes/esp32cX.rs

esp_hal/aes/
esp32cX.rs
