esp_hal/soc/esp32c6/
gpio.rs

1//! # GPIO configuration module (ESP32-C6)
2//!
3//! ## Overview
4//!
5//! The `GPIO` module provides functions and configurations for controlling the
6//! `General Purpose Input/Output` pins on the `ESP32-C6` chip. It allows you to
7//! configure pins as inputs or outputs, set their state and read their state.
8//!
9//! Let's get through the functionality and configurations provided by this GPIO
10//! module:
11//!   - `io_mux_reg(gpio_num: u8) -> &'static
12//!     crate::peripherals::io_mux::GPIO0:`:
13//!       * Returns the IO_MUX register for the specified GPIO pin number.
14//!   - `gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8`:
15//!       * This function enables or disables GPIO interrupts and Non-Maskable
16//!         Interrupts (NMI). It takes two boolean arguments int_enable and
17//!         nmi_enable to control the interrupt and NMI enable settings. The
18//!         function returns an u8 value representing the interrupt enable
19//!         settings.
20//!   - `gpio` block:
21//!       * Defines the pin configurations for various GPIO pins. Each line
22//!         represents a pin and its associated options such as input/output
23//!         mode, analog capability, and corresponding functions.
24//!   - `analog` block:
25//!       * Block defines the analog capabilities of various GPIO pins. Each
26//!         line represents a pin and its associated options such as mux
27//!         selection, function selection, and input enable.
28//!   - `enum InputSignal`:
29//!       * This enumeration defines input signals for the GPIO mux. Each input
30//!         signal is assigned a specific value.
31//!   - `enum OutputSignal`:
32//!       * This enumeration defines output signals for the GPIO mux. Each
33//!         output signal is assigned a specific value.
34//!
35//! This trait provides functions to read the interrupt status and NMI status
36//! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
37//! `gpio` peripheral to access the appropriate registers.
38
39use crate::{
40    gpio::{AlternateFunction, GpioPin},
41    pac::io_mux,
42    peripherals::{GPIO, IO_MUX},
43};
44
45/// The total number of GPIO pins available.
46pub const NUM_PINS: usize = 31;
47
48pub(crate) const FUNC_IN_SEL_OFFSET: usize = 0;
49
50pub(crate) type InputSignalType = u8;
51pub(crate) type OutputSignalType = u8;
52pub(crate) const OUTPUT_SIGNAL_MAX: u8 = 128;
53pub(crate) const INPUT_SIGNAL_MAX: u8 = 124;
54
55pub(crate) const ONE_INPUT: u8 = 0x38;
56pub(crate) const ZERO_INPUT: u8 = 0x3c;
57
58pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::_1;
59
60pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static io_mux::GPIO {
61    IO_MUX::regs().gpio(gpio_num as usize)
62}
63
64pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 {
65    int_enable as u8 | ((nmi_enable as u8) << 1)
66}
67
68/// Peripheral input signals for the GPIO mux
69#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
70#[derive(Debug, PartialEq, Copy, Clone)]
71#[cfg_attr(feature = "defmt", derive(defmt::Format))]
72#[doc(hidden)]
73pub enum InputSignal {
74    EXT_ADC_START       = 0,
75    U0RXD               = 6,
76    U0CTS               = 7,
77    U0DSR               = 8,
78    U1RXD               = 9,
79    U1CTS               = 10,
80    U1DSR               = 11,
81    I2S_MCLK            = 12,
82    I2SO_BCK            = 13,
83    I2SO_WS             = 14,
84    I2SI_SD             = 15,
85    I2SI_BCK            = 16,
86    I2SI_WS             = 17,
87    USB_JTAG_TDO_BRIDGE = 19,
88    CPU_TESTBUS0        = 20,
89    CPU_TESTBUS1        = 21,
90    CPU_TESTBUS2        = 22,
91    CPU_TESTBUS3        = 23,
92    CPU_TESTBUS4        = 24,
93    CPU_TESTBUS5        = 25,
94    CPU_TESTBUS6        = 26,
95    CPU_TESTBUS7        = 27,
96    CPU_GPIO_IN0        = 28,
97    CPU_GPIO_IN1        = 29,
98    CPU_GPIO_IN2        = 30,
99    CPU_GPIO_IN3        = 31,
100    CPU_GPIO_IN4        = 32,
101    CPU_GPIO_IN5        = 33,
102    CPU_GPIO_IN6        = 34,
103    CPU_GPIO_IN7        = 35,
104    USB_JTAG_TMS        = 37,
105    USB_EXTPHY_OEN      = 40,
106    USB_EXTPHY_VM       = 41,
107    USB_EXTPHY_VPO      = 42,
108    I2CEXT0_SCL         = 45,
109    I2CEXT0_SDA         = 46,
110    PARL_RX_DATA0       = 47,
111    PARL_RX_DATA1       = 48,
112    PARL_RX_DATA2       = 49,
113    PARL_RX_DATA3       = 50,
114    PARL_RX_DATA4       = 51,
115    PARL_RX_DATA5       = 52,
116    PARL_RX_DATA6       = 53,
117    PARL_RX_DATA7       = 54,
118    PARL_RX_DATA8       = 55,
119    PARL_RX_DATA9       = 56,
120    PARL_RX_DATA10      = 57,
121    PARL_RX_DATA11      = 58,
122    PARL_RX_DATA12      = 59,
123    PARL_RX_DATA13      = 60,
124    PARL_RX_DATA14      = 61,
125    PARL_RX_DATA15      = 62,
126    FSPICLK             = 63,
127    FSPIQ               = 64,
128    FSPID               = 65,
129    FSPIHD              = 66,
130    FSPIWP              = 67,
131    FSPICS0             = 68,
132    PARL_RX_CLK         = 69,
133    PARL_TX_CLK         = 70,
134    RMT_SIG_0           = 71,
135    RMT_SIG_1           = 72,
136    TWAI0_RX            = 73,
137    TWAI1_RX            = 77,
138    PWM0_SYNC0          = 87,
139    PWM0_SYNC1          = 88,
140    PWM0_SYNC2          = 89,
141    PWM0_F0             = 90,
142    PWM0_F1             = 91,
143    PWM0_F2             = 92,
144    PWM0_CAP0           = 93,
145    PWM0_CAP1           = 94,
146    PWM0_CAP2           = 95,
147    SIG_IN_FUNC97       = 97,
148    SIG_IN_FUNC98       = 98,
149    SIG_IN_FUNC99       = 99,
150    SIG_IN_FUNC100      = 100,
151    PCNT0_SIG_CH0       = 101,
152    PCNT0_SIG_CH1       = 102,
153    PCNT0_CTRL_CH0      = 103,
154    PCNT0_CTRL_CH1      = 104,
155    PCNT1_SIG_CH0       = 105,
156    PCNT1_SIG_CH1       = 106,
157    PCNT1_CTRL_CH0      = 107,
158    PCNT1_CTRL_CH1      = 108,
159    PCNT2_SIG_CH0       = 109,
160    PCNT2_SIG_CH1       = 110,
161    PCNT2_CTRL_CH0      = 111,
162    PCNT2_CTRL_CH1      = 112,
163    PCNT3_SIG_CH0       = 113,
164    PCNT3_SIG_CH1       = 114,
165    PCNT3_CTRL_CH0      = 115,
166    PCNT3_CTRL_CH1      = 116,
167    SPIQ                = 121,
168    SPID                = 122,
169    SPIHD               = 123,
170    SPIWP               = 124,
171}
172
173/// Peripheral input signals for the GPIO mux
174#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
175#[derive(Debug, PartialEq, Copy, Clone)]
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[doc(hidden)]
178pub enum OutputSignal {
179    LEDC_LS_SIG0          = 0,
180    LEDC_LS_SIG1          = 1,
181    LEDC_LS_SIG2          = 2,
182    LEDC_LS_SIG3          = 3,
183    LEDC_LS_SIG4          = 4,
184    LEDC_LS_SIG5          = 5,
185    U0TXD                 = 6,
186    U0RTS                 = 7,
187    U0DTR                 = 8,
188    U1TXD                 = 9,
189    U1RTS                 = 10,
190    U1DTR                 = 11,
191    I2S_MCLK              = 12,
192    I2SO_BCK              = 13,
193    I2SO_WS               = 14,
194    I2SO_SD               = 15,
195    I2SI_BCK              = 16,
196    I2SI_WS               = 17,
197    I2SO_SD1              = 18,
198    USB_JTAG_TDO_BRIDGE   = 19,
199    CPU_TESTBUS0          = 20,
200    CPU_TESTBUS1          = 21,
201    CPU_TESTBUS2          = 22,
202    CPU_TESTBUS3          = 23,
203    CPU_TESTBUS4          = 24,
204    CPU_TESTBUS5          = 25,
205    CPU_TESTBUS6          = 26,
206    CPU_TESTBUS7          = 27,
207    CPU_GPIO_OUT0         = 28,
208    CPU_GPIO_OUT1         = 29,
209    CPU_GPIO_OUT2         = 30,
210    CPU_GPIO_OUT3         = 31,
211    CPU_GPIO_OUT4         = 32,
212    CPU_GPIO_OUT5         = 33,
213    CPU_GPIO_OUT6         = 34,
214    CPU_GPIO_OUT7         = 35,
215    USB_JTAG_TCK          = 36,
216    USB_JTAG_TMS          = 37,
217    USB_JTAG_TDI          = 38,
218    USB_JTAG_TDO          = 39,
219    I2CEXT0_SCL           = 45,
220    I2CEXT0_SDA           = 46,
221    PARL_TX_DATA0         = 47,
222    PARL_TX_DATA1         = 48,
223    PARL_TX_DATA2         = 49,
224    PARL_TX_DATA3         = 50,
225    PARL_TX_DATA4         = 51,
226    PARL_TX_DATA5         = 52,
227    PARL_TX_DATA6         = 53,
228    PARL_TX_DATA7         = 54,
229    PARL_TX_DATA8         = 55,
230    PARL_TX_DATA9         = 56,
231    PARL_TX_DATA10        = 57,
232    PARL_TX_DATA11        = 58,
233    PARL_TX_DATA12        = 59,
234    PARL_TX_DATA13        = 60,
235    PARL_TX_DATA14        = 61,
236    PARL_TX_DATA15        = 62,
237    FSPICLK_MUX           = 63,
238    FSPIQ                 = 64,
239    FSPID                 = 65,
240    FSPIHD                = 66,
241    FSPIWP                = 67,
242    FSPICS0               = 68,
243    SDIO_TOHOST_INT       = 69,
244    PARL_TX_CLK           = 70,
245    RMT_SIG_0             = 71,
246    RMT_SIG_1             = 72,
247    TWAI0_TX              = 73,
248    TWAI0_BUS_OFF_ON      = 74,
249    TWAI0_CLKOUT          = 75,
250    TWAI0_STANDBY         = 76,
251    TWAI1_TX              = 77,
252    TWAI1_BUS_OFF_ON      = 78,
253    TWAI1_CLKOUT          = 79,
254    TWAI1_STANDBY         = 80,
255    GPIO_SD0              = 83,
256    GPIO_SD1              = 84,
257    GPIO_SD2              = 85,
258    GPIO_SD3              = 86,
259    PWM0_0A               = 87,
260    PWM0_0B               = 88,
261    PWM0_1A               = 89,
262    PWM0_1B               = 90,
263    PWM0_2A               = 91,
264    PWM0_2B               = 92,
265    SIG_IN_FUNC97         = 97,
266    SIG_IN_FUNC98         = 98,
267    SIG_IN_FUNC99         = 99,
268    SIG_IN_FUNC100        = 100,
269    FSPICS1               = 101,
270    FSPICS2               = 102,
271    FSPICS3               = 103,
272    FSPICS4               = 104,
273    FSPICS5               = 105,
274    SPICLK_MUX            = 114,
275    SPICS0                = 115,
276    SPICS1                = 116,
277    GPIO_TASK_MATRIX_OUT0 = 117,
278    GPIO_TASK_MATRIX_OUT1 = 118,
279    GPIO_TASK_MATRIX_OUT2 = 119,
280    GPIO_TASK_MATRIX_OUT3 = 120,
281    SPIQ                  = 121,
282    SPID                  = 122,
283    SPIHD                 = 123,
284    SPIWP                 = 124,
285    CLK_OUT_OUT1          = 125,
286    CLK_OUT_OUT2          = 126,
287    CLK_OUT_OUT3          = 127,
288    GPIO                  = 128,
289}
290
291crate::gpio::lp_io::lp_gpio! {
292    0
293    1
294    2
295    3
296    4
297    5
298    6
299    7
300}
301
302#[derive(Clone, Copy)]
303pub(crate) enum InterruptStatusRegisterAccess {
304    Bank0,
305}
306
307impl InterruptStatusRegisterAccess {
308    pub(crate) fn interrupt_status_read(self) -> u32 {
309        GPIO::regs().pcpu_int().read().bits()
310    }
311}
esp_hal/soc/esp32c6/gpio.rs

esp_hal/soc/esp32c6/
gpio.rs
