#![doc = crate::before_snippet!()]
#![cfg_attr(any(esp32, esp32s2), doc = "let dma_channel = peripherals.DMA_I2S0;")]
#![cfg_attr(
not(any(esp32, esp32s2)),
doc = "let dma_channel = peripherals.DMA_CH0;"
)]
#![cfg_attr(not(esp32), doc = "let i2s = i2s.with_mclk(peripherals.GPIO0);")]
use enumset::{EnumSet, EnumSetType};
use private::*;
use crate::{
dma::{
dma_private::{DmaSupport, DmaSupportRx, DmaSupportTx},
Channel,
ChannelRx,
ChannelTx,
DescriptorChain,
DmaChannelFor,
DmaDescriptor,
DmaEligible,
DmaError,
DmaTransferRx,
DmaTransferRxCircular,
DmaTransferTx,
DmaTransferTxCircular,
PeripheralRxChannel,
PeripheralTxChannel,
ReadBuffer,
Rx,
Tx,
WriteBuffer,
},
gpio::interconnect::PeripheralOutput,
interrupt::{InterruptConfigurable, InterruptHandler},
peripheral::{Peripheral, PeripheralRef},
system::PeripheralGuard,
time::Rate,
Async,
Blocking,
DriverMode,
};
#[derive(Debug, EnumSetType)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum I2sInterrupt {
RxHung,
TxHung,
#[cfg(not(any(esp32, esp32s2)))]
RxDone,
#[cfg(not(any(esp32, esp32s2)))]
TxDone,
}
#[cfg(any(esp32, esp32s2, esp32s3))]
pub(crate) const I2S_LL_MCLK_DIVIDER_BIT_WIDTH: usize = 6;
#[cfg(any(esp32c3, esp32c6, esp32h2))]
pub(crate) const I2S_LL_MCLK_DIVIDER_BIT_WIDTH: usize = 9;
pub(crate) const I2S_LL_MCLK_DIVIDER_MAX: usize = (1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1;
pub trait AcceptedWord: crate::private::Sealed {}
impl AcceptedWord for u8 {}
impl AcceptedWord for u16 {}
impl AcceptedWord for u32 {}
impl AcceptedWord for i8 {}
impl AcceptedWord for i16 {}
impl AcceptedWord for i32 {}
#[derive(Debug, Clone, Copy, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[allow(clippy::enum_variant_names, reason = "peripheral is unstable")]
pub enum Error {
Unknown,
DmaError(DmaError),
IllegalArgument,
}
impl From<DmaError> for Error {
fn from(value: DmaError) -> Self {
Error::DmaError(value)
}
}
#[derive(Debug, Clone, Copy, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Standard {
Philips,
}
#[derive(Debug, Clone, Copy, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[cfg(not(any(esp32, esp32s2)))]
pub enum DataFormat {
Data32Channel32,
Data32Channel24,
Data32Channel16,
Data32Channel8,
Data16Channel16,
Data16Channel8,
Data8Channel8,
}
#[derive(Debug, Clone, Copy, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[cfg(any(esp32, esp32s2))]
pub enum DataFormat {
Data32Channel32,
Data16Channel16,
}
#[cfg(not(any(esp32, esp32s2)))]
impl DataFormat {
pub fn data_bits(&self) -> u8 {
match self {
DataFormat::Data32Channel32 => 32,
DataFormat::Data32Channel24 => 32,
DataFormat::Data32Channel16 => 32,
DataFormat::Data32Channel8 => 32,
DataFormat::Data16Channel16 => 16,
DataFormat::Data16Channel8 => 16,
DataFormat::Data8Channel8 => 8,
}
}
pub fn channel_bits(&self) -> u8 {
match self {
DataFormat::Data32Channel32 => 32,
DataFormat::Data32Channel24 => 24,
DataFormat::Data32Channel16 => 16,
DataFormat::Data32Channel8 => 8,
DataFormat::Data16Channel16 => 16,
DataFormat::Data16Channel8 => 8,
DataFormat::Data8Channel8 => 8,
}
}
}
#[cfg(any(esp32, esp32s2))]
impl DataFormat {
pub fn data_bits(&self) -> u8 {
match self {
DataFormat::Data32Channel32 => 32,
DataFormat::Data16Channel16 => 16,
}
}
pub fn channel_bits(&self) -> u8 {
match self {
DataFormat::Data32Channel32 => 32,
DataFormat::Data16Channel16 => 16,
}
}
}
#[non_exhaustive]
pub struct I2s<'d, Dm>
where
Dm: DriverMode,
{
pub i2s_rx: RxCreator<'d, Dm>,
pub i2s_tx: TxCreator<'d, Dm>,
}
impl<Dm> I2s<'_, Dm>
where
Dm: DriverMode,
{
#[cfg_attr(
not(multi_core),
doc = "Registers an interrupt handler for the peripheral."
)]
#[cfg_attr(
multi_core,
doc = "Registers an interrupt handler for the peripheral on the current core."
)]
#[doc = ""]
#[instability::unstable]
pub fn set_interrupt_handler(&mut self, handler: InterruptHandler) {
self.i2s_tx.i2s.set_interrupt_handler(handler);
}
#[instability::unstable]
pub fn listen(&mut self, interrupts: impl Into<EnumSet<I2sInterrupt>>) {
self.i2s_tx.i2s.enable_listen(interrupts.into(), true);
}
#[instability::unstable]
pub fn unlisten(&mut self, interrupts: impl Into<EnumSet<I2sInterrupt>>) {
self.i2s_tx.i2s.enable_listen(interrupts.into(), false);
}
#[instability::unstable]
pub fn interrupts(&mut self) -> EnumSet<I2sInterrupt> {
self.i2s_tx.i2s.interrupts()
}
#[instability::unstable]
pub fn clear_interrupts(&mut self, interrupts: impl Into<EnumSet<I2sInterrupt>>) {
self.i2s_tx.i2s.clear_interrupts(interrupts.into());
}
}
impl<Dm> crate::private::Sealed for I2s<'_, Dm> where Dm: DriverMode {}
impl<Dm> InterruptConfigurable for I2s<'_, Dm>
where
Dm: DriverMode,
{
fn set_interrupt_handler(&mut self, handler: crate::interrupt::InterruptHandler) {
I2s::set_interrupt_handler(self, handler);
}
}
impl<'d> I2s<'d, Blocking> {
#[allow(clippy::too_many_arguments)]
pub fn new<CH>(
i2s: impl Peripheral<P = impl RegisterAccess> + 'd,
standard: Standard,
data_format: DataFormat,
sample_rate: Rate,
channel: impl Peripheral<P = CH> + 'd,
rx_descriptors: &'static mut [DmaDescriptor],
tx_descriptors: &'static mut [DmaDescriptor],
) -> Self
where
CH: DmaChannelFor<AnyI2s>,
{
crate::into_ref!(i2s);
let channel = Channel::new(channel.map(|ch| ch.degrade()));
channel.runtime_ensure_compatible(&i2s);
let peripheral = i2s.peripheral();
let rx_guard = PeripheralGuard::new(peripheral);
let tx_guard = PeripheralGuard::new(peripheral);
i2s.set_clock(calculate_clock(sample_rate, 2, data_format.channel_bits()));
i2s.configure(&standard, &data_format);
i2s.set_master();
i2s.update();
let i2s = i2s.map_into();
Self {
i2s_rx: RxCreator {
i2s: unsafe { i2s.clone_unchecked() },
rx_channel: channel.rx,
descriptors: rx_descriptors,
guard: rx_guard,
},
i2s_tx: TxCreator {
i2s,
tx_channel: channel.tx,
descriptors: tx_descriptors,
guard: tx_guard,
},
}
}
pub fn into_async(self) -> I2s<'d, Async> {
I2s {
i2s_rx: RxCreator {
i2s: self.i2s_rx.i2s,
rx_channel: self.i2s_rx.rx_channel.into_async(),
descriptors: self.i2s_rx.descriptors,
guard: self.i2s_rx.guard,
},
i2s_tx: TxCreator {
i2s: self.i2s_tx.i2s,
tx_channel: self.i2s_tx.tx_channel.into_async(),
descriptors: self.i2s_tx.descriptors,
guard: self.i2s_tx.guard,
},
}
}
}
impl<'d, Dm> I2s<'d, Dm>
where
Dm: DriverMode,
{
pub fn with_mclk<P: PeripheralOutput>(self, pin: impl Peripheral<P = P> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output();
self.i2s_tx.i2s.mclk_signal().connect_to(pin);
self
}
}
pub struct I2sTx<'d, Dm>
where
Dm: DriverMode,
{
i2s: PeripheralRef<'d, AnyI2s>,
tx_channel: ChannelTx<'d, Dm, PeripheralTxChannel<AnyI2s>>,
tx_chain: DescriptorChain,
_guard: PeripheralGuard,
}
impl<Dm> core::fmt::Debug for I2sTx<'_, Dm>
where
Dm: DriverMode,
{
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
f.debug_struct("I2sTx").finish()
}
}
impl<Dm> DmaSupport for I2sTx<'_, Dm>
where
Dm: DriverMode,
{
fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) {
self.i2s.wait_for_tx_done();
}
fn peripheral_dma_stop(&mut self) {
self.i2s.tx_stop();
}
}
impl<'d, Dm> DmaSupportTx for I2sTx<'d, Dm>
where
Dm: DriverMode,
{
type TX = ChannelTx<'d, Dm, PeripheralTxChannel<AnyI2s>>;
fn tx(&mut self) -> &mut Self::TX {
&mut self.tx_channel
}
fn chain(&mut self) -> &mut DescriptorChain {
&mut self.tx_chain
}
}
impl<Dm> I2sTx<'_, Dm>
where
Dm: DriverMode,
{
fn write(&mut self, data: &[u8]) -> Result<(), Error> {
self.start_tx_transfer(&data, false)?;
self.i2s.wait_for_tx_done();
Ok(())
}
fn start_tx_transfer<'t, TXBUF>(
&'t mut self,
words: &'t TXBUF,
circular: bool,
) -> Result<(), Error>
where
TXBUF: ReadBuffer,
Dm: DriverMode,
{
let (ptr, len) = unsafe { words.read_buffer() };
self.i2s.reset_tx();
unsafe {
self.tx_chain.fill_for_tx(circular, ptr, len)?;
self.tx_channel
.prepare_transfer_without_start(self.i2s.dma_peripheral(), &self.tx_chain)
.and_then(|_| self.tx_channel.start_transfer())?;
}
self.i2s.tx_start();
Ok(())
}
pub fn write_words(&mut self, words: &[impl AcceptedWord]) -> Result<(), Error> {
self.write(unsafe {
core::slice::from_raw_parts(words.as_ptr().cast::<u8>(), core::mem::size_of_val(words))
})
}
pub fn write_dma<'t>(
&'t mut self,
words: &'t impl ReadBuffer,
) -> Result<DmaTransferTx<'t, Self>, Error>
where
Self: DmaSupportTx,
{
self.start_tx_transfer(words, false)?;
Ok(DmaTransferTx::new(self))
}
pub fn write_dma_circular<'t>(
&'t mut self,
words: &'t impl ReadBuffer,
) -> Result<DmaTransferTxCircular<'t, Self>, Error>
where
Self: DmaSupportTx,
{
self.start_tx_transfer(words, true)?;
Ok(DmaTransferTxCircular::new(self))
}
}
pub struct I2sRx<'d, Dm>
where
Dm: DriverMode,
{
i2s: PeripheralRef<'d, AnyI2s>,
rx_channel: ChannelRx<'d, Dm, PeripheralRxChannel<AnyI2s>>,
rx_chain: DescriptorChain,
_guard: PeripheralGuard,
}
impl<Dm> core::fmt::Debug for I2sRx<'_, Dm>
where
Dm: DriverMode,
{
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
f.debug_struct("I2sRx").finish()
}
}
impl<Dm> DmaSupport for I2sRx<'_, Dm>
where
Dm: DriverMode,
{
fn peripheral_wait_dma(&mut self, _is_rx: bool, _is_tx: bool) {
self.i2s.wait_for_rx_done();
}
fn peripheral_dma_stop(&mut self) {
self.i2s.reset_rx();
}
}
impl<'d, Dm> DmaSupportRx for I2sRx<'d, Dm>
where
Dm: DriverMode,
{
type RX = ChannelRx<'d, Dm, PeripheralRxChannel<AnyI2s>>;
fn rx(&mut self) -> &mut Self::RX {
&mut self.rx_channel
}
fn chain(&mut self) -> &mut DescriptorChain {
&mut self.rx_chain
}
}
impl<Dm> I2sRx<'_, Dm>
where
Dm: DriverMode,
{
fn read(&mut self, mut data: &mut [u8]) -> Result<(), Error> {
self.start_rx_transfer(&mut data, false)?;
self.i2s.wait_for_rx_done();
Ok(())
}
fn start_rx_transfer<'t, RXBUF>(
&'t mut self,
words: &'t mut RXBUF,
circular: bool,
) -> Result<(), Error>
where
RXBUF: WriteBuffer,
{
let (ptr, len) = unsafe { words.write_buffer() };
if len % 4 != 0 {
return Err(Error::IllegalArgument);
}
self.i2s.reset_rx();
unsafe {
self.rx_chain.fill_for_rx(circular, ptr, len)?;
self.rx_channel
.prepare_transfer_without_start(self.i2s.dma_peripheral(), &self.rx_chain)
.and_then(|_| self.rx_channel.start_transfer())?;
}
self.i2s.rx_start(len);
Ok(())
}
pub fn read_words(&mut self, words: &mut [impl AcceptedWord]) -> Result<(), Error> {
if core::mem::size_of_val(words) > 4096 || words.is_empty() {
return Err(Error::IllegalArgument);
}
self.read(unsafe {
core::slice::from_raw_parts_mut(
words.as_mut_ptr().cast::<u8>(),
core::mem::size_of_val(words),
)
})
}
pub fn read_dma<'t>(
&'t mut self,
words: &'t mut impl WriteBuffer,
) -> Result<DmaTransferRx<'t, Self>, Error>
where
Self: DmaSupportRx,
{
self.start_rx_transfer(words, false)?;
Ok(DmaTransferRx::new(self))
}
pub fn read_dma_circular<'t>(
&'t mut self,
words: &'t mut impl WriteBuffer,
) -> Result<DmaTransferRxCircular<'t, Self>, Error>
where
Self: DmaSupportRx,
{
self.start_rx_transfer(words, true)?;
Ok(DmaTransferRxCircular::new(self))
}
}
pub trait RegisterAccess: RegisterAccessPrivate {}
impl<T> RegisterAccess for T where T: RegisterAccessPrivate {}
mod private {
use enumset::EnumSet;
use super::*;
#[cfg(not(i2s1))]
use crate::pac::i2s0::RegisterBlock;
use crate::{
dma::{ChannelRx, ChannelTx, DescriptorChain, DmaDescriptor, DmaEligible},
gpio::{
interconnect::{PeripheralInput, PeripheralOutput},
InputSignal,
OutputSignal,
},
interrupt::InterruptHandler,
peripheral::{Peripheral, PeripheralRef},
peripherals::{Interrupt, I2S0},
DriverMode,
};
#[cfg(i2s1)]
use crate::{pac::i2s1::RegisterBlock, peripherals::I2S1};
pub struct TxCreator<'d, Dm>
where
Dm: DriverMode,
{
pub i2s: PeripheralRef<'d, AnyI2s>,
pub tx_channel: ChannelTx<'d, Dm, PeripheralTxChannel<AnyI2s>>,
pub descriptors: &'static mut [DmaDescriptor],
pub(crate) guard: PeripheralGuard,
}
impl<'d, Dm> TxCreator<'d, Dm>
where
Dm: DriverMode,
{
pub fn build(self) -> I2sTx<'d, Dm> {
let peripheral = self.i2s.peripheral();
I2sTx {
i2s: self.i2s,
tx_channel: self.tx_channel,
tx_chain: DescriptorChain::new(self.descriptors),
_guard: PeripheralGuard::new(peripheral),
}
}
pub fn with_bclk<P>(self, pin: impl Peripheral<P = P> + 'd) -> Self
where
P: PeripheralOutput,
{
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output();
self.i2s.bclk_signal().connect_to(pin);
self
}
pub fn with_ws<P>(self, pin: impl Peripheral<P = P> + 'd) -> Self
where
P: PeripheralOutput,
{
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output();
self.i2s.ws_signal().connect_to(pin);
self
}
pub fn with_dout<P>(self, pin: impl Peripheral<P = P> + 'd) -> Self
where
P: PeripheralOutput,
{
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output();
self.i2s.dout_signal().connect_to(pin);
self
}
}
pub struct RxCreator<'d, Dm>
where
Dm: DriverMode,
{
pub i2s: PeripheralRef<'d, AnyI2s>,
pub rx_channel: ChannelRx<'d, Dm, PeripheralRxChannel<AnyI2s>>,
pub descriptors: &'static mut [DmaDescriptor],
pub(crate) guard: PeripheralGuard,
}
impl<'d, Dm> RxCreator<'d, Dm>
where
Dm: DriverMode,
{
pub fn build(self) -> I2sRx<'d, Dm> {
let peripheral = self.i2s.peripheral();
I2sRx {
i2s: self.i2s,
rx_channel: self.rx_channel,
rx_chain: DescriptorChain::new(self.descriptors),
_guard: PeripheralGuard::new(peripheral),
}
}
pub fn with_bclk<P>(self, pin: impl Peripheral<P = P> + 'd) -> Self
where
P: PeripheralOutput,
{
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output();
self.i2s.bclk_rx_signal().connect_to(pin);
self
}
pub fn with_ws<P>(self, pin: impl Peripheral<P = P> + 'd) -> Self
where
P: PeripheralOutput,
{
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output();
self.i2s.ws_rx_signal().connect_to(pin);
self
}
pub fn with_din<P>(self, pin: impl Peripheral<P = P> + 'd) -> Self
where
P: PeripheralInput,
{
crate::into_mapped_ref!(pin);
pin.init_input(crate::gpio::Pull::None);
self.i2s.din_signal().connect_to(pin);
self
}
}
pub trait RegBlock: Peripheral<P = Self> + DmaEligible + Into<super::AnyI2s> + 'static {
fn regs(&self) -> &RegisterBlock;
fn peripheral(&self) -> crate::system::Peripheral;
}
pub trait Signals: RegBlock {
fn mclk_signal(&self) -> OutputSignal;
fn bclk_signal(&self) -> OutputSignal;
fn ws_signal(&self) -> OutputSignal;
fn dout_signal(&self) -> OutputSignal;
fn bclk_rx_signal(&self) -> OutputSignal;
fn ws_rx_signal(&self) -> OutputSignal;
fn din_signal(&self) -> InputSignal;
}
#[cfg(any(esp32, esp32s2))]
pub trait RegisterAccessPrivate: Signals + RegBlock {
fn set_interrupt_handler(&self, handler: InterruptHandler);
fn enable_listen(&self, interrupts: EnumSet<I2sInterrupt>, enable: bool) {
self.regs().int_ena().modify(|_, w| {
for interrupt in interrupts {
match interrupt {
I2sInterrupt::RxHung => w.rx_hung().bit(enable),
I2sInterrupt::TxHung => w.tx_hung().bit(enable),
};
}
w
});
}
fn interrupts(&self) -> EnumSet<I2sInterrupt> {
let mut res = EnumSet::new();
let ints = self.regs().int_st().read();
if ints.rx_hung().bit() {
res.insert(I2sInterrupt::RxHung);
}
if ints.tx_hung().bit() {
res.insert(I2sInterrupt::TxHung);
}
res
}
fn clear_interrupts(&self, interrupts: EnumSet<I2sInterrupt>) {
self.regs().int_clr().write(|w| {
for interrupt in interrupts {
match interrupt {
I2sInterrupt::RxHung => w.rx_hung().clear_bit_by_one(),
I2sInterrupt::TxHung => w.tx_hung().clear_bit_by_one(),
};
}
w
});
}
fn set_clock(&self, clock_settings: I2sClockDividers) {
self.regs().clkm_conf().modify(|r, w| unsafe {
w.bits(r.bits() | (crate::soc::constants::I2S_DEFAULT_CLK_SRC << 21))
});
#[cfg(esp32)]
self.regs()
.clkm_conf()
.modify(|_, w| w.clka_ena().clear_bit());
self.regs().clkm_conf().modify(|_, w| unsafe {
w.clk_en().set_bit();
w.clkm_div_num().bits(clock_settings.mclk_divider as u8);
w.clkm_div_a().bits(clock_settings.denominator as u8);
w.clkm_div_b().bits(clock_settings.numerator as u8)
});
self.regs().sample_rate_conf().modify(|_, w| unsafe {
w.tx_bck_div_num().bits(clock_settings.bclk_divider as u8);
w.rx_bck_div_num().bits(clock_settings.bclk_divider as u8)
});
}
fn configure(&self, _standard: &Standard, data_format: &DataFormat) {
let fifo_mod = match data_format {
DataFormat::Data32Channel32 => 2,
DataFormat::Data16Channel16 => 0,
};
self.regs().sample_rate_conf().modify(|_, w| unsafe {
w.tx_bits_mod().bits(data_format.channel_bits());
w.rx_bits_mod().bits(data_format.channel_bits())
});
self.regs().conf().modify(|_, w| {
w.tx_slave_mod().clear_bit();
w.rx_slave_mod().clear_bit();
w.tx_msb_shift().set_bit();
w.rx_msb_shift().set_bit();
w.tx_short_sync().bit(false);
w.rx_short_sync().bit(false);
w.tx_msb_right().set_bit();
w.rx_msb_right().set_bit();
w.tx_right_first().set_bit();
w.rx_right_first().set_bit();
w.tx_mono().clear_bit();
w.rx_mono().clear_bit();
w.sig_loopback().clear_bit()
});
self.regs().fifo_conf().modify(|_, w| unsafe {
w.tx_fifo_mod().bits(fifo_mod);
w.tx_fifo_mod_force_en().set_bit();
w.dscr_en().set_bit();
w.rx_fifo_mod().bits(fifo_mod);
w.rx_fifo_mod_force_en().set_bit()
});
self.regs().conf_chan().modify(|_, w| unsafe {
w.tx_chan_mod().bits(0);
w.rx_chan_mod().bits(0)
});
self.regs().conf1().modify(|_, w| {
w.tx_pcm_bypass().set_bit();
w.rx_pcm_bypass().set_bit()
});
self.regs().pd_conf().modify(|_, w| {
w.fifo_force_pu().set_bit();
w.fifo_force_pd().clear_bit()
});
self.regs().conf2().modify(|_, w| {
w.camera_en().clear_bit();
w.lcd_en().clear_bit()
});
}
fn set_master(&self) {
self.regs().conf().modify(|_, w| {
w.rx_slave_mod().clear_bit();
w.tx_slave_mod().clear_bit()
});
}
fn update(&self) {
}
fn reset_tx(&self) {
self.regs().conf().modify(|_, w| {
w.tx_reset().set_bit();
w.tx_fifo_reset().set_bit()
});
self.regs().conf().modify(|_, w| {
w.tx_reset().clear_bit();
w.tx_fifo_reset().clear_bit()
});
self.regs().lc_conf().modify(|_, w| w.out_rst().set_bit());
self.regs().lc_conf().modify(|_, w| w.out_rst().clear_bit());
self.regs().int_clr().write(|w| {
w.out_done().clear_bit_by_one();
w.out_total_eof().clear_bit_by_one()
});
}
fn tx_start(&self) {
self.regs().conf().modify(|_, w| w.tx_start().set_bit());
while self.regs().state().read().tx_idle().bit_is_set() {
}
}
fn tx_stop(&self) {
self.regs().conf().modify(|_, w| w.tx_start().clear_bit());
}
fn wait_for_tx_done(&self) {
while self.regs().state().read().tx_idle().bit_is_clear() {
}
self.regs().conf().modify(|_, w| w.tx_start().clear_bit());
}
fn reset_rx(&self) {
self.regs().conf().modify(|_, w| {
w.rx_reset().set_bit();
w.rx_fifo_reset().set_bit()
});
self.regs().conf().modify(|_, w| {
w.rx_reset().clear_bit();
w.rx_fifo_reset().clear_bit()
});
self.regs().lc_conf().modify(|_, w| w.in_rst().set_bit());
self.regs().lc_conf().modify(|_, w| w.in_rst().clear_bit());
self.regs().int_clr().write(|w| {
w.in_done().clear_bit_by_one();
w.in_suc_eof().clear_bit_by_one()
});
}
fn rx_start(&self, len: usize) {
self.regs()
.int_clr()
.write(|w| w.in_suc_eof().clear_bit_by_one());
cfg_if::cfg_if! {
if #[cfg(esp32)] {
let eof_num = len / 4;
} else {
let eof_num = len - 1;
}
}
self.regs()
.rxeof_num()
.modify(|_, w| unsafe { w.rx_eof_num().bits(eof_num as u32) });
self.regs().conf().modify(|_, w| w.rx_start().set_bit());
}
fn wait_for_rx_done(&self) {
while self.regs().int_raw().read().in_suc_eof().bit_is_clear() {
}
self.regs()
.int_clr()
.write(|w| w.in_suc_eof().clear_bit_by_one());
}
}
#[cfg(any(esp32c3, esp32c6, esp32h2, esp32s3))]
pub trait RegisterAccessPrivate: Signals + RegBlock {
fn set_interrupt_handler(&self, handler: InterruptHandler);
fn enable_listen(&self, interrupts: EnumSet<I2sInterrupt>, enable: bool) {
self.regs().int_ena().modify(|_, w| {
for interrupt in interrupts {
match interrupt {
I2sInterrupt::RxHung => w.rx_hung().bit(enable),
I2sInterrupt::TxHung => w.tx_hung().bit(enable),
I2sInterrupt::RxDone => w.rx_done().bit(enable),
I2sInterrupt::TxDone => w.tx_done().bit(enable),
};
}
w
});
}
fn listen(&self, interrupts: impl Into<EnumSet<I2sInterrupt>>) {
self.enable_listen(interrupts.into(), true);
}
fn unlisten(&self, interrupts: impl Into<EnumSet<I2sInterrupt>>) {
self.enable_listen(interrupts.into(), false);
}
fn interrupts(&self) -> EnumSet<I2sInterrupt> {
let mut res = EnumSet::new();
let ints = self.regs().int_st().read();
if ints.rx_hung().bit() {
res.insert(I2sInterrupt::RxHung);
}
if ints.tx_hung().bit() {
res.insert(I2sInterrupt::TxHung);
}
if ints.rx_done().bit() {
res.insert(I2sInterrupt::RxDone);
}
if ints.tx_done().bit() {
res.insert(I2sInterrupt::TxDone);
}
res
}
fn clear_interrupts(&self, interrupts: EnumSet<I2sInterrupt>) {
self.regs().int_clr().write(|w| {
for interrupt in interrupts {
match interrupt {
I2sInterrupt::RxHung => w.rx_hung().clear_bit_by_one(),
I2sInterrupt::TxHung => w.tx_hung().clear_bit_by_one(),
I2sInterrupt::RxDone => w.rx_done().clear_bit_by_one(),
I2sInterrupt::TxDone => w.tx_done().clear_bit_by_one(),
};
}
w
});
}
#[cfg(any(esp32c3, esp32s3))]
fn set_clock(&self, clock_settings: I2sClockDividers) {
let clkm_div_x: u32;
let clkm_div_y: u32;
let clkm_div_z: u32;
let clkm_div_yn1: u32;
if clock_settings.denominator == 0 || clock_settings.numerator == 0 {
clkm_div_x = 0;
clkm_div_y = 0;
clkm_div_z = 0;
clkm_div_yn1 = 1;
} else if clock_settings.numerator > clock_settings.denominator / 2 {
clkm_div_x = clock_settings
.denominator
.overflowing_div(
clock_settings
.denominator
.overflowing_sub(clock_settings.numerator)
.0,
)
.0
.overflowing_sub(1)
.0;
clkm_div_y = clock_settings.denominator
% (clock_settings
.denominator
.overflowing_sub(clock_settings.numerator)
.0);
clkm_div_z = clock_settings
.denominator
.overflowing_sub(clock_settings.numerator)
.0;
clkm_div_yn1 = 1;
} else {
clkm_div_x = clock_settings.denominator / clock_settings.numerator - 1;
clkm_div_y = clock_settings.denominator % clock_settings.numerator;
clkm_div_z = clock_settings.numerator;
clkm_div_yn1 = 0;
}
self.regs().tx_clkm_div_conf().modify(|_, w| unsafe {
w.tx_clkm_div_x().bits(clkm_div_x as u16);
w.tx_clkm_div_y().bits(clkm_div_y as u16);
w.tx_clkm_div_yn1().bit(clkm_div_yn1 != 0);
w.tx_clkm_div_z().bits(clkm_div_z as u16)
});
self.regs().tx_clkm_conf().modify(|_, w| unsafe {
w.clk_en().set_bit();
w.tx_clk_active().set_bit();
w.tx_clk_sel()
.bits(crate::soc::constants::I2S_DEFAULT_CLK_SRC) ;
w.tx_clkm_div_num().bits(clock_settings.mclk_divider as u8)
});
self.regs().tx_conf1().modify(|_, w| unsafe {
w.tx_bck_div_num()
.bits((clock_settings.bclk_divider - 1) as u8)
});
self.regs().rx_clkm_div_conf().modify(|_, w| unsafe {
w.rx_clkm_div_x().bits(clkm_div_x as u16);
w.rx_clkm_div_y().bits(clkm_div_y as u16);
w.rx_clkm_div_yn1().bit(clkm_div_yn1 != 0);
w.rx_clkm_div_z().bits(clkm_div_z as u16)
});
self.regs().rx_clkm_conf().modify(|_, w| unsafe {
w.rx_clk_active().set_bit();
w.rx_clk_sel()
.bits(crate::soc::constants::I2S_DEFAULT_CLK_SRC);
w.rx_clkm_div_num().bits(clock_settings.mclk_divider as u8);
w.mclk_sel().bit(true)
});
self.regs().rx_conf1().modify(|_, w| unsafe {
w.rx_bck_div_num()
.bits((clock_settings.bclk_divider - 1) as u8)
});
}
#[cfg(any(esp32c6, esp32h2))]
fn set_clock(&self, clock_settings: I2sClockDividers) {
use crate::peripherals::PCR;
let clkm_div_x: u32;
let clkm_div_y: u32;
let clkm_div_z: u32;
let clkm_div_yn1: u32;
if clock_settings.denominator == 0 || clock_settings.numerator == 0 {
clkm_div_x = 0;
clkm_div_y = 0;
clkm_div_z = 0;
clkm_div_yn1 = 1;
} else if clock_settings.numerator > clock_settings.denominator / 2 {
clkm_div_x = clock_settings
.denominator
.overflowing_div(
clock_settings
.denominator
.overflowing_sub(clock_settings.numerator)
.0,
)
.0
.overflowing_sub(1)
.0;
clkm_div_y = clock_settings.denominator
% (clock_settings
.denominator
.overflowing_sub(clock_settings.numerator)
.0);
clkm_div_z = clock_settings
.denominator
.overflowing_sub(clock_settings.numerator)
.0;
clkm_div_yn1 = 1;
} else {
clkm_div_x = clock_settings.denominator / clock_settings.numerator - 1;
clkm_div_y = clock_settings.denominator % clock_settings.numerator;
clkm_div_z = clock_settings.numerator;
clkm_div_yn1 = 0;
}
PCR::regs().i2s_tx_clkm_div_conf().modify(|_, w| unsafe {
w.i2s_tx_clkm_div_x().bits(clkm_div_x as u16);
w.i2s_tx_clkm_div_y().bits(clkm_div_y as u16);
w.i2s_tx_clkm_div_yn1().bit(clkm_div_yn1 != 0);
w.i2s_tx_clkm_div_z().bits(clkm_div_z as u16)
});
PCR::regs().i2s_tx_clkm_conf().modify(|_, w| unsafe {
w.i2s_tx_clkm_en().set_bit();
w.i2s_tx_clkm_sel()
.bits(crate::soc::constants::I2S_DEFAULT_CLK_SRC);
w.i2s_tx_clkm_div_num()
.bits(clock_settings.mclk_divider as u8)
});
#[cfg(not(esp32h2))]
self.regs().tx_conf1().modify(|_, w| unsafe {
w.tx_bck_div_num()
.bits((clock_settings.bclk_divider - 1) as u8)
});
#[cfg(esp32h2)]
self.regs().tx_conf().modify(|_, w| unsafe {
w.tx_bck_div_num()
.bits((clock_settings.bclk_divider - 1) as u8)
});
PCR::regs().i2s_rx_clkm_div_conf().modify(|_, w| unsafe {
w.i2s_rx_clkm_div_x().bits(clkm_div_x as u16);
w.i2s_rx_clkm_div_y().bits(clkm_div_y as u16);
w.i2s_rx_clkm_div_yn1().bit(clkm_div_yn1 != 0);
w.i2s_rx_clkm_div_z().bits(clkm_div_z as u16)
});
PCR::regs().i2s_rx_clkm_conf().modify(|_, w| unsafe {
w.i2s_rx_clkm_en().set_bit();
w.i2s_rx_clkm_sel()
.bits(crate::soc::constants::I2S_DEFAULT_CLK_SRC);
w.i2s_rx_clkm_div_num()
.bits(clock_settings.mclk_divider as u8);
w.i2s_mclk_sel().bit(true)
});
#[cfg(not(esp32h2))]
self.regs().rx_conf1().modify(|_, w| unsafe {
w.rx_bck_div_num()
.bits((clock_settings.bclk_divider - 1) as u8)
});
#[cfg(esp32h2)]
self.regs().rx_conf().modify(|_, w| unsafe {
w.rx_bck_div_num()
.bits((clock_settings.bclk_divider - 1) as u8)
});
}
fn configure(&self, _standard: &Standard, data_format: &DataFormat) {
#[allow(clippy::useless_conversion)]
self.regs().tx_conf1().modify(|_, w| unsafe {
w.tx_tdm_ws_width()
.bits((data_format.channel_bits() - 1).into());
w.tx_bits_mod().bits(data_format.data_bits() - 1);
w.tx_tdm_chan_bits().bits(data_format.channel_bits() - 1);
w.tx_half_sample_bits().bits(data_format.channel_bits() - 1)
});
#[cfg(not(esp32h2))]
self.regs()
.tx_conf1()
.modify(|_, w| w.tx_msb_shift().set_bit());
#[cfg(esp32h2)]
self.regs()
.tx_conf()
.modify(|_, w| w.tx_msb_shift().set_bit());
self.regs().tx_conf().modify(|_, w| unsafe {
w.tx_mono().clear_bit();
w.tx_mono_fst_vld().set_bit();
w.tx_stop_en().set_bit();
w.tx_chan_equal().clear_bit();
w.tx_tdm_en().set_bit();
w.tx_pdm_en().clear_bit();
w.tx_pcm_bypass().set_bit();
w.tx_big_endian().clear_bit();
w.tx_bit_order().clear_bit();
w.tx_chan_mod().bits(0)
});
self.regs().tx_tdm_ctrl().modify(|_, w| unsafe {
w.tx_tdm_tot_chan_num().bits(1);
w.tx_tdm_chan0_en().set_bit();
w.tx_tdm_chan1_en().set_bit();
w.tx_tdm_chan2_en().clear_bit();
w.tx_tdm_chan3_en().clear_bit();
w.tx_tdm_chan4_en().clear_bit();
w.tx_tdm_chan5_en().clear_bit();
w.tx_tdm_chan6_en().clear_bit();
w.tx_tdm_chan7_en().clear_bit();
w.tx_tdm_chan8_en().clear_bit();
w.tx_tdm_chan9_en().clear_bit();
w.tx_tdm_chan10_en().clear_bit();
w.tx_tdm_chan11_en().clear_bit();
w.tx_tdm_chan12_en().clear_bit();
w.tx_tdm_chan13_en().clear_bit();
w.tx_tdm_chan14_en().clear_bit();
w.tx_tdm_chan15_en().clear_bit()
});
#[allow(clippy::useless_conversion)]
self.regs().rx_conf1().modify(|_, w| unsafe {
w.rx_tdm_ws_width()
.bits((data_format.channel_bits() - 1).into());
w.rx_bits_mod().bits(data_format.data_bits() - 1);
w.rx_tdm_chan_bits().bits(data_format.channel_bits() - 1);
w.rx_half_sample_bits().bits(data_format.channel_bits() - 1)
});
#[cfg(not(esp32h2))]
self.regs()
.rx_conf1()
.modify(|_, w| w.rx_msb_shift().set_bit());
#[cfg(esp32h2)]
self.regs()
.rx_conf()
.modify(|_, w| w.rx_msb_shift().set_bit());
self.regs().rx_conf().modify(|_, w| unsafe {
w.rx_mono().clear_bit();
w.rx_mono_fst_vld().set_bit();
w.rx_stop_mode().bits(2);
w.rx_tdm_en().set_bit();
w.rx_pdm_en().clear_bit();
w.rx_pcm_bypass().set_bit();
w.rx_big_endian().clear_bit();
w.rx_bit_order().clear_bit()
});
self.regs().rx_tdm_ctrl().modify(|_, w| unsafe {
w.rx_tdm_tot_chan_num().bits(1);
w.rx_tdm_pdm_chan0_en().set_bit();
w.rx_tdm_pdm_chan1_en().set_bit();
w.rx_tdm_pdm_chan2_en().clear_bit();
w.rx_tdm_pdm_chan3_en().clear_bit();
w.rx_tdm_pdm_chan4_en().clear_bit();
w.rx_tdm_pdm_chan5_en().clear_bit();
w.rx_tdm_pdm_chan6_en().clear_bit();
w.rx_tdm_pdm_chan7_en().clear_bit();
w.rx_tdm_chan8_en().clear_bit();
w.rx_tdm_chan9_en().clear_bit();
w.rx_tdm_chan10_en().clear_bit();
w.rx_tdm_chan11_en().clear_bit();
w.rx_tdm_chan12_en().clear_bit();
w.rx_tdm_chan13_en().clear_bit();
w.rx_tdm_chan14_en().clear_bit();
w.rx_tdm_chan15_en().clear_bit()
});
}
fn set_master(&self) {
self.regs()
.tx_conf()
.modify(|_, w| w.tx_slave_mod().clear_bit());
self.regs()
.rx_conf()
.modify(|_, w| w.rx_slave_mod().clear_bit());
}
fn update(&self) {
self.regs()
.tx_conf()
.modify(|_, w| w.tx_update().clear_bit());
self.regs().tx_conf().modify(|_, w| w.tx_update().set_bit());
self.regs()
.rx_conf()
.modify(|_, w| w.rx_update().clear_bit());
self.regs().rx_conf().modify(|_, w| w.rx_update().set_bit());
}
fn reset_tx(&self) {
self.regs().tx_conf().modify(|_, w| {
w.tx_reset().set_bit();
w.tx_fifo_reset().set_bit()
});
self.regs().tx_conf().modify(|_, w| {
w.tx_reset().clear_bit();
w.tx_fifo_reset().clear_bit()
});
self.regs().int_clr().write(|w| {
w.tx_done().clear_bit_by_one();
w.tx_hung().clear_bit_by_one()
});
}
fn tx_start(&self) {
self.regs().tx_conf().modify(|_, w| w.tx_start().set_bit());
}
fn tx_stop(&self) {
self.regs()
.tx_conf()
.modify(|_, w| w.tx_start().clear_bit());
}
fn wait_for_tx_done(&self) {
while self.regs().state().read().tx_idle().bit_is_clear() {
}
self.regs()
.tx_conf()
.modify(|_, w| w.tx_start().clear_bit());
}
fn reset_rx(&self) {
self.regs()
.rx_conf()
.modify(|_, w| w.rx_start().clear_bit());
self.regs().rx_conf().modify(|_, w| {
w.rx_reset().set_bit();
w.rx_fifo_reset().set_bit()
});
self.regs().rx_conf().modify(|_, w| {
w.rx_reset().clear_bit();
w.rx_fifo_reset().clear_bit()
});
self.regs().int_clr().write(|w| {
w.rx_done().clear_bit_by_one();
w.rx_hung().clear_bit_by_one()
});
}
fn rx_start(&self, len: usize) {
let len = len - 1;
self.regs()
.rxeof_num()
.write(|w| unsafe { w.rx_eof_num().bits(len as u16) });
self.regs().rx_conf().modify(|_, w| w.rx_start().set_bit());
}
fn wait_for_rx_done(&self) {
while self.regs().int_raw().read().rx_done().bit_is_clear() {
}
self.regs()
.int_clr()
.write(|w| w.rx_done().clear_bit_by_one());
}
}
impl RegBlock for I2S0 {
fn regs(&self) -> &RegisterBlock {
unsafe { &*I2S0::PTR.cast::<RegisterBlock>() }
}
fn peripheral(&self) -> crate::system::Peripheral {
crate::system::Peripheral::I2s0
}
}
impl RegisterAccessPrivate for I2S0 {
fn set_interrupt_handler(&self, handler: InterruptHandler) {
for core in crate::system::Cpu::other() {
crate::interrupt::disable(core, Interrupt::I2S0);
}
unsafe { crate::peripherals::I2S0::steal() }.bind_i2s0_interrupt(handler.handler());
unwrap!(crate::interrupt::enable(
Interrupt::I2S0,
handler.priority()
));
}
}
impl Signals for crate::peripherals::I2S0 {
fn mclk_signal(&self) -> OutputSignal {
cfg_if::cfg_if! {
if #[cfg(esp32)] {
panic!("MCLK currently not supported on ESP32");
} else if #[cfg(esp32s2)] {
OutputSignal::CLK_I2S
} else if #[cfg(esp32s3)] {
OutputSignal::I2S0_MCLK
} else {
OutputSignal::I2S_MCLK
}
}
}
fn bclk_signal(&self) -> OutputSignal {
cfg_if::cfg_if! {
if #[cfg(any(esp32, esp32s2, esp32s3))] {
OutputSignal::I2S0O_BCK
} else {
OutputSignal::I2SO_BCK
}
}
}
fn ws_signal(&self) -> OutputSignal {
cfg_if::cfg_if! {
if #[cfg(any(esp32, esp32s2, esp32s3))] {
OutputSignal::I2S0O_WS
} else {
OutputSignal::I2SO_WS
}
}
}
fn dout_signal(&self) -> OutputSignal {
cfg_if::cfg_if! {
if #[cfg(esp32)] {
OutputSignal::I2S0O_DATA_23
} else if #[cfg(esp32s2)] {
OutputSignal::I2S0O_DATA_OUT23
} else if #[cfg(esp32s3)] {
OutputSignal::I2S0O_SD
} else {
OutputSignal::I2SO_SD
}
}
}
fn bclk_rx_signal(&self) -> OutputSignal {
cfg_if::cfg_if! {
if #[cfg(any(esp32, esp32s2, esp32s3))] {
OutputSignal::I2S0I_BCK
} else {
OutputSignal::I2SI_BCK
}
}
}
fn ws_rx_signal(&self) -> OutputSignal {
cfg_if::cfg_if! {
if #[cfg(any(esp32, esp32s2, esp32s3))] {
OutputSignal::I2S0I_WS
} else {
OutputSignal::I2SI_WS
}
}
}
fn din_signal(&self) -> InputSignal {
cfg_if::cfg_if! {
if #[cfg(esp32)] {
InputSignal::I2S0I_DATA_15
} else if #[cfg(esp32s2)] {
InputSignal::I2S0I_DATA_IN15
} else if #[cfg(esp32s3)] {
InputSignal::I2S0I_SD
} else {
InputSignal::I2SI_SD
}
}
}
}
#[cfg(i2s1)]
impl RegBlock for I2S1 {
fn regs(&self) -> &RegisterBlock {
unsafe { &*I2S1::PTR.cast::<RegisterBlock>() }
}
fn peripheral(&self) -> crate::system::Peripheral {
crate::system::Peripheral::I2s1
}
}
#[cfg(i2s1)]
impl RegisterAccessPrivate for I2S1 {
fn set_interrupt_handler(&self, handler: InterruptHandler) {
for core in crate::system::Cpu::other() {
crate::interrupt::disable(core, Interrupt::I2S1);
}
unsafe { crate::peripherals::I2S1::steal() }.bind_i2s1_interrupt(handler.handler());
unwrap!(crate::interrupt::enable(
Interrupt::I2S1,
handler.priority()
));
}
}
#[cfg(i2s1)]
impl Signals for crate::peripherals::I2S1 {
fn mclk_signal(&self) -> OutputSignal {
cfg_if::cfg_if! {
if #[cfg(esp32)] {
panic!("MCLK currently not supported on ESP32");
} else {
OutputSignal::I2S1_MCLK
}
}
}
fn bclk_signal(&self) -> OutputSignal {
OutputSignal::I2S1O_BCK
}
fn ws_signal(&self) -> OutputSignal {
OutputSignal::I2S1O_WS
}
fn dout_signal(&self) -> OutputSignal {
cfg_if::cfg_if! {
if #[cfg(esp32)] {
OutputSignal::I2S1O_DATA_23
} else {
OutputSignal::I2S1O_SD
}
}
}
fn bclk_rx_signal(&self) -> OutputSignal {
OutputSignal::I2S1I_BCK
}
fn ws_rx_signal(&self) -> OutputSignal {
OutputSignal::I2S1I_WS
}
fn din_signal(&self) -> InputSignal {
cfg_if::cfg_if! {
if #[cfg(esp32)] {
InputSignal::I2S1I_DATA_15
} else {
InputSignal::I2S1I_SD
}
}
}
}
impl RegBlock for super::AnyI2s {
fn regs(&self) -> &RegisterBlock {
match &self.0 {
super::AnyI2sInner::I2s0(i2s) => RegBlock::regs(i2s),
#[cfg(i2s1)]
super::AnyI2sInner::I2s1(i2s) => RegBlock::regs(i2s),
}
}
delegate::delegate! {
to match &self.0 {
super::AnyI2sInner::I2s0(i2s) => i2s,
#[cfg(i2s1)]
super::AnyI2sInner::I2s1(i2s) => i2s,
} {
fn peripheral(&self) -> crate::system::Peripheral;
}
}
}
impl RegisterAccessPrivate for super::AnyI2s {
delegate::delegate! {
to match &self.0 {
super::AnyI2sInner::I2s0(i2s) => i2s,
#[cfg(i2s1)]
super::AnyI2sInner::I2s1(i2s) => i2s,
} {
fn set_interrupt_handler(&self, handler: InterruptHandler);
}
}
}
impl Signals for super::AnyI2s {
delegate::delegate! {
to match &self.0 {
super::AnyI2sInner::I2s0(i2s) => i2s,
#[cfg(i2s1)]
super::AnyI2sInner::I2s1(i2s) => i2s,
} {
fn mclk_signal(&self) -> OutputSignal;
fn bclk_signal(&self) -> OutputSignal;
fn ws_signal(&self) -> OutputSignal;
fn dout_signal(&self) -> OutputSignal;
fn bclk_rx_signal(&self) -> OutputSignal;
fn ws_rx_signal(&self) -> OutputSignal;
fn din_signal(&self) -> InputSignal;
}
}
}
pub struct I2sClockDividers {
mclk_divider: u32,
bclk_divider: u32,
denominator: u32,
numerator: u32,
}
pub fn calculate_clock(sample_rate: Rate, channels: u8, data_bits: u8) -> I2sClockDividers {
let mclk_multiple = if data_bits == 24 { 192 } else { 256 };
let sclk = crate::soc::constants::I2S_SCLK; let rate = sample_rate.as_hz();
let bclk = rate * channels as u32 * data_bits as u32;
let mclk = rate * mclk_multiple;
let bclk_divider = mclk / bclk;
let mut mclk_divider = sclk / mclk;
let mut ma: u32;
let mut mb: u32;
let mut denominator: u32 = 0;
let mut numerator: u32 = 0;
let freq_diff = sclk.abs_diff(mclk * mclk_divider);
if freq_diff != 0 {
let decimal = freq_diff as u64 * 10000 / mclk as u64;
if decimal > 1250000 / 126 {
mclk_divider += 1;
} else {
let mut min: u32 = !0;
for a in 2..=I2S_LL_MCLK_DIVIDER_MAX {
let b = (a as u64) * (freq_diff as u64 * 10000u64 / mclk as u64) + 5000;
ma = ((freq_diff as u64 * 10000u64 * a as u64) / 10000) as u32;
mb = (mclk as u64 * (b / 10000)) as u32;
if ma == mb {
denominator = a as u32;
numerator = (b / 10000) as u32;
break;
}
if mb.abs_diff(ma) < min {
denominator = a as u32;
numerator = b as u32;
min = mb.abs_diff(ma);
}
}
}
}
I2sClockDividers {
mclk_divider,
bclk_divider,
denominator,
numerator,
}
}
}
pub mod asynch {
use super::{Error, I2sRx, I2sTx, RegisterAccessPrivate};
use crate::{
dma::{
asynch::{DmaRxDoneChFuture, DmaRxFuture, DmaTxDoneChFuture, DmaTxFuture},
DmaEligible,
ReadBuffer,
Rx,
RxCircularState,
Tx,
TxCircularState,
WriteBuffer,
},
Async,
};
impl<'d> I2sTx<'d, Async> {
pub async fn write_dma_async(&mut self, words: &mut [u8]) -> Result<(), Error> {
let (ptr, len) = (words.as_ptr(), words.len());
self.i2s.reset_tx();
let future = DmaTxFuture::new(&mut self.tx_channel);
unsafe {
self.tx_chain.fill_for_tx(false, ptr, len)?;
future
.tx
.prepare_transfer_without_start(self.i2s.dma_peripheral(), &self.tx_chain)
.and_then(|_| future.tx.start_transfer())?;
}
self.i2s.tx_start();
future.await?;
Ok(())
}
pub fn write_dma_circular_async<TXBUF: ReadBuffer>(
mut self,
words: TXBUF,
) -> Result<I2sWriteDmaTransferAsync<'d, TXBUF>, Error> {
let (ptr, len) = unsafe { words.read_buffer() };
self.i2s.reset_tx();
unsafe {
self.tx_chain.fill_for_tx(true, ptr, len)?;
self.tx_channel
.prepare_transfer_without_start(self.i2s.dma_peripheral(), &self.tx_chain)
.and_then(|_| self.tx_channel.start_transfer())?;
}
self.i2s.tx_start();
let state = TxCircularState::new(&mut self.tx_chain);
Ok(I2sWriteDmaTransferAsync {
i2s_tx: self,
state,
_buffer: words,
})
}
}
pub struct I2sWriteDmaTransferAsync<'d, BUFFER> {
i2s_tx: I2sTx<'d, Async>,
state: TxCircularState,
_buffer: BUFFER,
}
impl<BUFFER> I2sWriteDmaTransferAsync<'_, BUFFER> {
pub async fn available(&mut self) -> Result<usize, Error> {
loop {
self.state.update(&self.i2s_tx.tx_channel)?;
let res = self.state.available;
if res != 0 {
break Ok(res);
}
DmaTxDoneChFuture::new(&mut self.i2s_tx.tx_channel).await?
}
}
pub async fn push(&mut self, data: &[u8]) -> Result<usize, Error> {
let avail = self.available().await?;
let to_send = usize::min(avail, data.len());
Ok(self.state.push(&data[..to_send])?)
}
pub async fn push_with(
&mut self,
f: impl FnOnce(&mut [u8]) -> usize,
) -> Result<usize, Error> {
let _avail = self.available().await;
Ok(self.state.push_with(f)?)
}
}
impl<'d> I2sRx<'d, Async> {
pub async fn read_dma_async(&mut self, words: &mut [u8]) -> Result<(), Error> {
let (ptr, len) = (words.as_mut_ptr(), words.len());
if len % 4 != 0 {
return Err(Error::IllegalArgument);
}
self.i2s.reset_rx();
let future = DmaRxFuture::new(&mut self.rx_channel);
unsafe {
self.rx_chain.fill_for_rx(false, ptr, len)?;
future
.rx
.prepare_transfer_without_start(self.i2s.dma_peripheral(), &self.rx_chain)
.and_then(|_| future.rx.start_transfer())?;
}
self.i2s.rx_start(len);
future.await?;
Ok(())
}
pub fn read_dma_circular_async<RXBUF>(
mut self,
mut words: RXBUF,
) -> Result<I2sReadDmaTransferAsync<'d, RXBUF>, Error>
where
RXBUF: WriteBuffer,
{
let (ptr, len) = unsafe { words.write_buffer() };
if len % 4 != 0 {
return Err(Error::IllegalArgument);
}
self.i2s.reset_rx();
unsafe {
self.rx_chain.fill_for_rx(true, ptr, len)?;
self.rx_channel
.prepare_transfer_without_start(self.i2s.dma_peripheral(), &self.rx_chain)
.and_then(|_| self.rx_channel.start_transfer())?;
}
self.i2s.rx_start(len);
let state = RxCircularState::new(&mut self.rx_chain);
Ok(I2sReadDmaTransferAsync {
i2s_rx: self,
state,
_buffer: words,
})
}
}
pub struct I2sReadDmaTransferAsync<'d, BUFFER> {
i2s_rx: I2sRx<'d, Async>,
state: RxCircularState,
_buffer: BUFFER,
}
impl<BUFFER> I2sReadDmaTransferAsync<'_, BUFFER> {
pub async fn available(&mut self) -> Result<usize, Error> {
loop {
self.state.update()?;
let res = self.state.available;
if res != 0 {
break Ok(res);
}
DmaRxDoneChFuture::new(&mut self.i2s_rx.rx_channel).await?;
}
}
pub async fn pop(&mut self, data: &mut [u8]) -> Result<usize, Error> {
let avail = self.available().await?;
let to_rcv = usize::min(avail, data.len());
Ok(self.state.pop(&mut data[..to_rcv])?)
}
}
}
crate::any_peripheral! {
pub peripheral AnyI2s {
#[cfg(i2s0)]
I2s0(crate::peripherals::I2S0),
#[cfg(i2s1)]
I2s1(crate::peripherals::I2S1),
}
}
impl DmaEligible for AnyI2s {
#[cfg(gdma)]
type Dma = crate::dma::AnyGdmaChannel;
#[cfg(pdma)]
type Dma = crate::dma::AnyI2sDmaChannel;
fn dma_peripheral(&self) -> crate::dma::DmaPeripheral {
match &self.0 {
AnyI2sInner::I2s0(_) => crate::dma::DmaPeripheral::I2s0,
#[cfg(i2s1)]
AnyI2sInner::I2s1(_) => crate::dma::DmaPeripheral::I2s1,
}
}
}