Available on crate feature
unstable
only.Expand description
§Stability
This API is marked as unstable and is only available when the unstable
crate feature is enabled. This comes with no stability guarantees, and could be changed
or removed at any time.
§Reading of eFuses (ESP32-S3)
§Overview
The efuse
module provides functionality for reading eFuse data
from the ESP32-S3
chip, allowing access to various chip-specific
information such as:
- MAC address
- Chip revision
and more. It is useful for retrieving chip-specific configuration and identification data during runtime.
The Efuse
struct represents the eFuse peripheral and is responsible for
reading various eFuse fields and values.
§Examples
§Read data from the eFuse storage.
let mac_address = Efuse::read_base_mac_address();
println!(
"MAC: {:#X}:{:#X}:{:#X}:{:#X}:{:#X}:{:#X}",
mac_address[0],
mac_address[1],
mac_address[2],
mac_address[3],
mac_address[4],
mac_address[5]
);
println!("MAC address {:02x?}", Efuse::mac_address());
println!("Flash Encryption {:?}", Efuse::flash_encryption());
Structs§
- A struct representing the eFuse functionality of the chip.
Constants§
[]
ADC1 calibration voltage at atten0[]
ADC1 calibration voltage at atten1[]
ADC1 calibration voltage at atten2[]
ADC1 calibration voltage at atten3[]
ADC1 init code at atten0[]
ADC1 init code at atten1[]
ADC1 init code at atten2[]
ADC1 init code at atten3[]
ADC2 calibration voltage at atten0[]
ADC2 calibration voltage at atten1[]
ADC2 calibration voltage at atten2[]
ADC2 calibration voltage at atten3[]
ADC2 init code at atten0[]
ADC2 init code at atten1[]
ADC2 init code at atten2[]
ADC2 init code at atten3[]
BLK_VERSION_MAJOR of BLOCK2 {0: “No calib”; 1: “ADC calib V1”}[]
BLK_VERSION_MINOR[]
BLOCK1 digital dbias when hvt[]
Disables check of blk version major[]
Disables check of wafer version major[]
Disable app cpu[]
Set this bit to disable Dcache[DIS_LEGACY_SPI_BOOT]
Disable direct boot mode[]
Set this bit to disable Dcache in download mode ( boot_mode[3:0]
is 0; 1; 2; 3; 6; 7)[]
Set this bit to disable Icache in download mode (boot_mode[3:0]
is 0; 1; 2; 3; 6; 7)[]
Set this bit to disable flash encryption when in download boot modes[]
Set this bit to disable download mode (boot_mode[3:0]
= 0; 1; 2; 3; 6; 7)[]
Set this bit to disable the function that forces chip into download mode[]
Set this bit to disable Icache[HARD_DIS_JTAG]
Set this bit to disable JTAG in the hard way. JTAG is disabled permanently[DIS_CAN]
Set this bit to disable TWAI function[]
Set this bit to disable function of usb switch to jtag in module of usb device[DIS_USB]
Set this bit to disable USB function[]
Set this bit to disable download through USB-OTG[DIS_USB_DEVICE]
Set this bit to disable usb device[DIS_USB_DOWNLOAD_MODE]
Set this bit to disable UART download mode through USB[UART_PRINT_CHANNEL]
USB printing {0: “Enable”; 1: “Disable”}[]
Set this bit to enable secure UART download mode[]
Flash capacity {0: “None”; 1: “8M”; 2: “4M”}[]
Set 1 to enable ECC for flash boot[]
Flash ECC mode in ROM {0: “16to18 byte”; 1: “16to17 byte”}[]
Set Flash page size[]
Flash temperature {0: “None”; 1: “105C”; 2: “85C”}[]
Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value[]
SPI flash type {0: “4 data lines”; 1: “8 data lines”}[]
Flash vendor {0: “None”; 1: “XMC”; 2: “GD”; 3: “FM”; 4: “TT”; 5: “BY”}[]
Set this bit to force ROM code to send a resume command during SPI boot[BLOCK_KEY0]
Key0 or user data[BLOCK_KEY1]
Key1 or user data[BLOCK_KEY2]
Key2 or user data[BLOCK_KEY3]
Key3 or user data[BLOCK_KEY4]
Key4 or user data[BLOCK_KEY5]
Key5 or user data[KEY0_PURPOSE]
Purpose of Key0[KEY1_PURPOSE]
Purpose of Key1[KEY2_PURPOSE]
Purpose of Key2[KEY3_PURPOSE]
Purpose of Key3[KEY4_PURPOSE]
Purpose of Key4[KEY5_PURPOSE]
Purpose of Key5[]
BLOCK1 K_DIG_LDO[]
BLOCK1 K_RTC_LDO[MAC_FACTORY]
MAC address[]
ADC OCode[]
Optional unique 128-bit ID[]
Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: “VDD3P3_CPU”; 1: “VDD_SPI”}[]
Package version[]
PSRAM capacity {0: “None”; 1: “8M”; 2: “2M”}[]
PSRAM temperature {0: “None”; 1: “105C”; 2: “85C”}[]
PSRAM vendor {0: “None”; 1: “AP_3v3”; 2: “AP_1v8”}[]
Disable reading from BlOCK4-10[RD_DIS.KEY0]
rd_dis of BLOCK_KEY0[RD_DIS.KEY1]
rd_dis of BLOCK_KEY1[RD_DIS.KEY2]
rd_dis of BLOCK_KEY2[RD_DIS.KEY3]
rd_dis of BLOCK_KEY3[RD_DIS.KEY4]
rd_dis of BLOCK_KEY4[RD_DIS.KEY5]
rd_dis of BLOCK_KEY5[RD_DIS.SYS_DATA_PART2]
rd_dis of BLOCK_SYS_DATA2[]
Set this bit to enable revoking aggressive secure boot[]
Set this bit to enable secure boot[]
Revoke 1st secure boot key[]
Revoke 2nd secure boot key[]
Revoke 3rd secure boot key[]
Secure version (used by ESP-IDF anti-rollback feature)[]
Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module[]
Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: “Disable”; 1: “Enable”; 3: “Disable”; 7: “Enable”}[]
SPI_PAD_configure CLK[]
SPI_PAD_configure CS[]
SPI_PAD_configure D(D0)[]
SPI_PAD_configure D4[]
SPI_PAD_configure D5[]
SPI_PAD_configure D6[]
SPI_PAD_configure D7[]
SPI_PAD_configure DQS[]
SPI_PAD_configure HD(D3)[]
SPI_PAD_configure Q(D1)[]
SPI_PAD_configure WP(D2)[]
Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0[BLOCK_SYS_DATA2]
System data part 2 (reserved)[]
Temperature calibration data[]
Set the default UART boot message output mode {0: “Enable”; 1: “Enable when GPIO46 is low at reset”; 2: “Enable when GPIO46 is high at reset”; 3: “Disable”}[]
Set this bit to exchange USB D+ and D- pins[EXT_PHY_ENABLE]
Set this bit to enable external PHY[]
This bit is used to switch internal PHY and external PHY for USB OTG and USB Device {0: “internal PHY is assigned to USB Device while external PHY is assigned to USB OTG”; 1: “internal PHY is assigned to USB OTG while external PHY is assigned to USB Device”}[BLOCK_USR_DATA]
User data[MAC_CUSTOM CUSTOM_MAC]
Custom MAC[]
Set this bit and force to use the configuration of eFuse to configure VDD_SPI[]
If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: “VDD_SPI connects to 1.8 V LDO”; 1: “VDD_SPI connects to VDD3P3_RTC_IO”}[]
SPI regulator power up signal[]
BLOCK1 voltage of digital dbias20[]
BLOCK1 voltage of rtc dbias20[]
WAFER_VERSION_MAJOR[]
WAFER_VERSION_MINOR most significant bit[]
WAFER_VERSION_MINOR least significant bits[]
RTC watchdog timeout threshold; in unit of slow clock cycle {0: “40000”; 1: “80000”; 2: “160000”; 3: “320000”}[]
Disable programming of individual eFuses[]
wr_dis of ADC1_CAL_VOL_ATTEN0[]
wr_dis of ADC1_CAL_VOL_ATTEN1[]
wr_dis of ADC1_CAL_VOL_ATTEN2[]
wr_dis of ADC1_CAL_VOL_ATTEN3[]
wr_dis of ADC1_INIT_CODE_ATTEN0[]
wr_dis of ADC1_INIT_CODE_ATTEN1[]
wr_dis of ADC1_INIT_CODE_ATTEN2[]
wr_dis of ADC1_INIT_CODE_ATTEN3[]
wr_dis of ADC2_CAL_VOL_ATTEN0[]
wr_dis of ADC2_CAL_VOL_ATTEN1[]
wr_dis of ADC2_CAL_VOL_ATTEN2[]
wr_dis of ADC2_CAL_VOL_ATTEN3[]
wr_dis of ADC2_INIT_CODE_ATTEN0[]
wr_dis of ADC2_INIT_CODE_ATTEN1[]
wr_dis of ADC2_INIT_CODE_ATTEN2[]
wr_dis of ADC2_INIT_CODE_ATTEN3[]
wr_dis of BLOCK1[]
wr_dis of BLK_VERSION_MAJOR[]
wr_dis of BLK_VERSION_MINOR[WR_DIS.KEY0]
wr_dis of BLOCK_KEY0[WR_DIS.KEY1]
wr_dis of BLOCK_KEY1[WR_DIS.KEY2]
wr_dis of BLOCK_KEY2[WR_DIS.KEY3]
wr_dis of BLOCK_KEY3[WR_DIS.KEY4]
wr_dis of BLOCK_KEY4[WR_DIS.KEY5]
wr_dis of BLOCK_KEY5[WR_DIS.SYS_DATA_PART2]
wr_dis of BLOCK_SYS_DATA2[WR_DIS.USER_DATA]
wr_dis of BLOCK_USR_DATA[WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM]
wr_dis of CUSTOM_MAC[]
wr_dis of DIG_DBIAS_HVT[]
wr_dis of DISABLE_BLK_VERSION_MAJOR[]
wr_dis of DISABLE_WAFER_VERSION_MAJOR[]
wr_dis of DIS_APP_CPU[]
wr_dis of DIS_DCACHE[WR_DIS.DIS_LEGACY_SPI_BOOT]
wr_dis of DIS_DIRECT_BOOT[]
wr_dis of DIS_DOWNLOAD_DCACHE[]
wr_dis of DIS_DOWNLOAD_ICACHE[]
wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT[]
wr_dis of DIS_DOWNLOAD_MODE[]
wr_dis of DIS_FORCE_DOWNLOAD[]
wr_dis of DIS_ICACHE[WR_DIS.HARD_DIS_JTAG]
wr_dis of DIS_PAD_JTAG[WR_DIS.DIS_CAN]
wr_dis of DIS_TWAI[]
wr_dis of DIS_USB_JTAG[WR_DIS.DIS_USB]
wr_dis of DIS_USB_OTG[]
wr_dis of DIS_USB_OTG_DOWNLOAD_MODE[WR_DIS.DIS_USB_DEVICE]
wr_dis of DIS_USB_SERIAL_JTAG[WR_DIS.DIS_USB_DOWNLOAD_MODE]
wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[WR_DIS.UART_PRINT_CHANNEL]
wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT[]
wr_dis of ENABLE_SECURITY_DOWNLOAD[]
wr_dis of FLASH_CAP[]
wr_dis of FLASH_ECC_EN[]
wr_dis of FLASH_ECC_MODE[]
wr_dis of FLASH_PAGE_SIZE[]
wr_dis of FLASH_TEMP[]
wr_dis of FLASH_TPUW[]
wr_dis of FLASH_TYPE[]
wr_dis of FLASH_VENDOR[]
wr_dis of FORCE_SEND_RESUME[WR_DIS.KEY0_PURPOSE]
wr_dis of KEY_PURPOSE_0[WR_DIS.KEY1_PURPOSE]
wr_dis of KEY_PURPOSE_1[WR_DIS.KEY2_PURPOSE]
wr_dis of KEY_PURPOSE_2[WR_DIS.KEY3_PURPOSE]
wr_dis of KEY_PURPOSE_3[WR_DIS.KEY4_PURPOSE]
wr_dis of KEY_PURPOSE_4[WR_DIS.KEY5_PURPOSE]
wr_dis of KEY_PURPOSE_5[]
wr_dis of K_DIG_LDO[]
wr_dis of K_RTC_LDO[WR_DIS.MAC_FACTORY]
wr_dis of MAC[]
wr_dis of OCODE[]
wr_dis of OPTIONAL_UNIQUE_ID[]
wr_dis of PIN_POWER_SELECTION[]
wr_dis of PKG_VERSION[]
wr_dis of PSRAM_CAP[]
wr_dis of PSRAM_TEMP[]
wr_dis of PSRAM_VENDOR[]
wr_dis of RD_DIS[]
wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE[]
wr_dis of SECURE_BOOT_EN[]
wr_dis of SECURE_BOOT_KEY_REVOKE0[]
wr_dis of SECURE_BOOT_KEY_REVOKE1[]
wr_dis of SECURE_BOOT_KEY_REVOKE2[]
wr_dis of SECURE_VERSION[]
wr_dis of SOFT_DIS_JTAG[]
wr_dis of SPI_BOOT_CRYPT_CNT[]
wr_dis of SPI_PAD_CONFIG_CLK[]
wr_dis of SPI_PAD_CONFIG_CS[]
wr_dis of SPI_PAD_CONFIG_D[]
wr_dis of SPI_PAD_CONFIG_D4[]
wr_dis of SPI_PAD_CONFIG_D5[]
wr_dis of SPI_PAD_CONFIG_D6[]
wr_dis of SPI_PAD_CONFIG_D7[]
wr_dis of SPI_PAD_CONFIG_DQS[]
wr_dis of SPI_PAD_CONFIG_HD[]
wr_dis of SPI_PAD_CONFIG_Q[]
wr_dis of SPI_PAD_CONFIG_WP[]
wr_dis of STRAP_JTAG_SEL[]
wr_dis of BLOCK2[]
wr_dis of TEMP_CALIB[]
wr_dis of UART_PRINT_CONTROL[]
wr_dis of USB_EXCHG_PINS[WR_DIS.EXT_PHY_ENABLE]
wr_dis of USB_EXT_PHY_ENABLE[]
wr_dis of USB_PHY_SEL[]
wr_dis of VDD_SPI_FORCE[]
wr_dis of VDD_SPI_TIEH[]
wr_dis of VDD_SPI_XPD[]
wr_dis of V_DIG_DBIAS20[]
wr_dis of V_RTC_DBIAS20[]
wr_dis of WAFER_VERSION_MAJOR[]
wr_dis of WAFER_VERSION_MINOR_HI[]
wr_dis of WAFER_VERSION_MINOR_LO[]
wr_dis of WDT_DELAY_SEL