esp_hal/soc/esp32/
gpio.rs

1//! # GPIO configuration module (ESP32)
2//!
3//! ## Overview
4//!
5//! The `GPIO` module provides functions and configurations for controlling the
6//! `General Purpose Input/Output` pins on the `ESP32` chip. It allows you to
7//! configure pins as inputs or outputs, set their state and read their state.
8//!
9//! Let's get through the functionality and configurations provided by this GPIO
10//! module:
11//!   - `io_mux_reg(gpio_num: u8) -> &'static io_mux::GPIO0:`:
12//!       * This function returns a reference to the GPIO register associated
13//!         with the given GPIO number. It uses unsafe code and transmutation to
14//!         access the GPIO registers based on the provided GPIO number.
15//!   - `gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8`:
16//!       * This function enables or disables GPIO interrupts and Non-Maskable
17//!         Interrupts (NMI). It takes two boolean arguments int_enable and
18//!         nmi_enable to control the interrupt and NMI enable settings. The
19//!         function returns an u8 value representing the interrupt enable
20//!         settings.
21//!   - `errata36(pin_num: u8, pull_up: bool, pull_down: bool)`:
22//!       * Handles the configuration of pull-up and pull-down resistors for
23//!         specific GPIO pins
24//!   - `gpio` block:
25//!       * Defines the pin configurations for various GPIO pins. Each line
26//!         represents a pin and its associated options such as input/output
27//!         mode, analog capability, and corresponding functions.
28//!   - `analog` block:
29//!       * Block defines the analog capabilities of various GPIO pins. Each
30//!         line represents a pin and its associated options such as mux
31//!         selection, function selection, and input enable.
32//!   - `enum InputSignal`:
33//!       * This enumeration defines input signals for the GPIO mux. Each input
34//!         signal is assigned a specific value.
35//!   - `enum OutputSignal`:
36//!       * This enumeration defines output signals for the GPIO mux. Each
37//!         output signal is assigned a specific value.
38//!
39//! This trait provides functions to read the interrupt status and NMI status
40//! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
41//! `gpio` peripheral to access the appropriate registers.
42
43use core::mem::transmute;
44
45use crate::{
46    gpio::AlternateFunction,
47    pac::io_mux,
48    peripherals::{GPIO, IO_MUX},
49    system::Cpu,
50};
51
52/// The total number of GPIO pins available.
53pub const NUM_PINS: usize = 40;
54
55pub(crate) const FUNC_IN_SEL_OFFSET: usize = 0;
56
57pub(crate) type InputSignalType = u16;
58pub(crate) type OutputSignalType = u16;
59pub(crate) const OUTPUT_SIGNAL_MAX: u16 = 548;
60pub(crate) const INPUT_SIGNAL_MAX: u16 = 539;
61
62pub(crate) const ONE_INPUT: u8 = 0x38;
63pub(crate) const ZERO_INPUT: u8 = 0x30;
64
65pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::_2;
66
67pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static io_mux::GPIO0 {
68    let iomux = IO_MUX::regs();
69
70    unsafe {
71        match gpio_num {
72            0 => transmute::<&'static io_mux::GPIO0, &'static io_mux::GPIO0>(iomux.gpio0()),
73            1 => transmute::<&'static io_mux::GPIO1, &'static io_mux::GPIO0>(iomux.gpio1()),
74            2 => transmute::<&'static io_mux::GPIO2, &'static io_mux::GPIO0>(iomux.gpio2()),
75            3 => transmute::<&'static io_mux::GPIO3, &'static io_mux::GPIO0>(iomux.gpio3()),
76            4 => transmute::<&'static io_mux::GPIO4, &'static io_mux::GPIO0>(iomux.gpio4()),
77            5 => transmute::<&'static io_mux::GPIO5, &'static io_mux::GPIO0>(iomux.gpio5()),
78            6 => transmute::<&'static io_mux::GPIO6, &'static io_mux::GPIO0>(iomux.gpio6()),
79            7 => transmute::<&'static io_mux::GPIO7, &'static io_mux::GPIO0>(iomux.gpio7()),
80            8 => transmute::<&'static io_mux::GPIO8, &'static io_mux::GPIO0>(iomux.gpio8()),
81            9 => transmute::<&'static io_mux::GPIO9, &'static io_mux::GPIO0>(iomux.gpio9()),
82            10 => transmute::<&'static io_mux::GPIO10, &'static io_mux::GPIO0>(iomux.gpio10()),
83            11 => transmute::<&'static io_mux::GPIO11, &'static io_mux::GPIO0>(iomux.gpio11()),
84            12 => transmute::<&'static io_mux::GPIO12, &'static io_mux::GPIO0>(iomux.gpio12()),
85            13 => transmute::<&'static io_mux::GPIO13, &'static io_mux::GPIO0>(iomux.gpio13()),
86            14 => transmute::<&'static io_mux::GPIO14, &'static io_mux::GPIO0>(iomux.gpio14()),
87            15 => transmute::<&'static io_mux::GPIO15, &'static io_mux::GPIO0>(iomux.gpio15()),
88            16 => transmute::<&'static io_mux::GPIO16, &'static io_mux::GPIO0>(iomux.gpio16()),
89            17 => transmute::<&'static io_mux::GPIO17, &'static io_mux::GPIO0>(iomux.gpio17()),
90            18 => transmute::<&'static io_mux::GPIO18, &'static io_mux::GPIO0>(iomux.gpio18()),
91            19 => transmute::<&'static io_mux::GPIO19, &'static io_mux::GPIO0>(iomux.gpio19()),
92            20 => transmute::<&'static io_mux::GPIO20, &'static io_mux::GPIO0>(iomux.gpio20()),
93            21 => transmute::<&'static io_mux::GPIO21, &'static io_mux::GPIO0>(iomux.gpio21()),
94            22 => transmute::<&'static io_mux::GPIO22, &'static io_mux::GPIO0>(iomux.gpio22()),
95            23 => transmute::<&'static io_mux::GPIO23, &'static io_mux::GPIO0>(iomux.gpio23()),
96            24 => transmute::<&'static io_mux::GPIO24, &'static io_mux::GPIO0>(iomux.gpio24()),
97            25 => transmute::<&'static io_mux::GPIO25, &'static io_mux::GPIO0>(iomux.gpio25()),
98            26 => transmute::<&'static io_mux::GPIO26, &'static io_mux::GPIO0>(iomux.gpio26()),
99            27 => transmute::<&'static io_mux::GPIO27, &'static io_mux::GPIO0>(iomux.gpio27()),
100            32 => transmute::<&'static io_mux::GPIO32, &'static io_mux::GPIO0>(iomux.gpio32()),
101            33 => transmute::<&'static io_mux::GPIO33, &'static io_mux::GPIO0>(iomux.gpio33()),
102            34 => transmute::<&'static io_mux::GPIO34, &'static io_mux::GPIO0>(iomux.gpio34()),
103            35 => transmute::<&'static io_mux::GPIO35, &'static io_mux::GPIO0>(iomux.gpio35()),
104            36 => transmute::<&'static io_mux::GPIO36, &'static io_mux::GPIO0>(iomux.gpio36()),
105            37 => transmute::<&'static io_mux::GPIO37, &'static io_mux::GPIO0>(iomux.gpio37()),
106            38 => transmute::<&'static io_mux::GPIO38, &'static io_mux::GPIO0>(iomux.gpio38()),
107            39 => transmute::<&'static io_mux::GPIO39, &'static io_mux::GPIO0>(iomux.gpio39()),
108            other => panic!("GPIO {} does not exist", other),
109        }
110    }
111}
112
113pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 {
114    match Cpu::current() {
115        Cpu::AppCpu => int_enable as u8 | ((nmi_enable as u8) << 1),
116        Cpu::ProCpu => ((int_enable as u8) << 2) | ((nmi_enable as u8) << 3),
117    }
118}
119
120/// Peripheral input signals for the GPIO mux
121#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
122#[derive(Debug, PartialEq, Copy, Clone)]
123#[cfg_attr(feature = "defmt", derive(defmt::Format))]
124#[doc(hidden)]
125pub enum InputSignal {
126    SPICLK                = 0,
127    SPIQ                  = 1,
128    SPID                  = 2,
129    SPIHD                 = 3,
130    SPIWP                 = 4,
131    SPICS0                = 5,
132    SPICS1                = 6,
133    SPICS2                = 7,
134    HSPICLK               = 8,
135    HSPIQ                 = 9,
136    HSPID                 = 10,
137    HSPICS0               = 11,
138    HSPIHD                = 12,
139    HSPIWP                = 13,
140    U0RXD                 = 14,
141    U0CTS                 = 15,
142    U0DSR                 = 16,
143    U1RXD                 = 17,
144    U1CTS                 = 18,
145    I2S0O_BCK             = 23,
146    I2S1O_BCK             = 24,
147    I2S0O_WS              = 25,
148    I2S1O_WS              = 26,
149    I2S0I_BCK             = 27,
150    I2S0I_WS              = 28,
151    I2CEXT0_SCL           = 29,
152    I2CEXT0_SDA           = 30,
153    PWM0_SYNC0            = 31,
154    PWM0_SYNC1            = 32,
155    PWM0_SYNC2            = 33,
156    PWM0_F0               = 34,
157    PWM0_F1               = 35,
158    PWM0_F2               = 36,
159    PCNT0_SIG_CH0         = 39,
160    PCNT0_SIG_CH1         = 40,
161    PCNT0_CTRL_CH0        = 41,
162    PCNT0_CTRL_CH1        = 42,
163    PCNT1_SIG_CH0         = 43,
164    PCNT1_SIG_CH1         = 44,
165    PCNT1_CTRL_CH0        = 45,
166    PCNT1_CTRL_CH1        = 46,
167    PCNT2_SIG_CH0         = 47,
168    PCNT2_SIG_CH1         = 48,
169    PCNT2_CTRL_CH0        = 49,
170    PCNT2_CTRL_CH1        = 50,
171    PCNT3_SIG_CH0         = 51,
172    PCNT3_SIG_CH1         = 52,
173    PCNT3_CTRL_CH0        = 53,
174    PCNT3_CTRL_CH1        = 54,
175    PCNT4_SIG_CH0         = 55,
176    PCNT4_SIG_CH1         = 56,
177    PCNT4_CTRL_CH0        = 57,
178    PCNT4_CTRL_CH1        = 58,
179    HSPICS1               = 61,
180    HSPICS2               = 62,
181    VSPICLK               = 63,
182    VSPIQ                 = 64,
183    VSPID                 = 65,
184    VSPIHD                = 66,
185    VSPIWP                = 67,
186    VSPICS0               = 68,
187    VSPICS1               = 69,
188    VSPICS2               = 70,
189    PCNT5_SIG_CH0         = 71,
190    PCNT5_SIG_CH1         = 72,
191    PCNT5_CTRL_CH0        = 73,
192    PCNT5_CTRL_CH1        = 74,
193    PCNT6_SIG_CH0         = 75,
194    PCNT6_SIG_CH1         = 76,
195    PCNT6_CTRL_CH0        = 77,
196    PCNT6_CTRL_CH1        = 78,
197    PCNT7_SIG_CH0         = 79,
198    PCNT7_SIG_CH1         = 80,
199    PCNT7_CTRL_CH0        = 81,
200    PCNT7_CTRL_CH1        = 82,
201    RMT_SIG_0             = 83,
202    RMT_SIG_1             = 84,
203    RMT_SIG_2             = 85,
204    RMT_SIG_3             = 86,
205    RMT_SIG_4             = 87,
206    RMT_SIG_5             = 88,
207    RMT_SIG_6             = 89,
208    RMT_SIG_7             = 90,
209    TWAI_RX               = 94,
210    I2CEXT1_SCL           = 95,
211    I2CEXT1_SDA           = 96,
212    HOST_CARD_DETECT_N_1  = 97,
213    HOST_CARD_DETECT_N_2  = 98,
214    HOST_CARD_WRITE_PRT_1 = 99,
215    HOST_CARD_WRITE_PRT_2 = 100,
216    HOST_CARD_INT_N_1     = 101,
217    HOST_CARD_INT_N_2     = 102,
218    PWM1_SYNC0            = 103,
219    PWM1_SYNC1            = 104,
220    PWM1_SYNC2            = 105,
221    PWM1_F0               = 106,
222    PWM1_F1               = 107,
223    PWM1_F2               = 108,
224    PWM0_CAP0             = 109,
225    PWM0_CAP1             = 110,
226    PWM0_CAP2             = 111,
227    PWM1_CAP0             = 112,
228    PWM1_CAP1             = 113,
229    PWM1_CAP2             = 114,
230    I2S0I_DATA_0          = 140,
231    I2S0I_DATA_1          = 141,
232    I2S0I_DATA_2          = 142,
233    I2S0I_DATA_3          = 143,
234    I2S0I_DATA_4          = 144,
235    I2S0I_DATA_5          = 145,
236    I2S0I_DATA_6          = 146,
237    I2S0I_DATA_7          = 147,
238    I2S0I_DATA_8          = 148,
239    I2S0I_DATA_9          = 149,
240    I2S0I_DATA_10         = 150,
241    I2S0I_DATA_11         = 151,
242    I2S0I_DATA_12         = 152,
243    I2S0I_DATA_13         = 153,
244    I2S0I_DATA_14         = 154,
245    I2S0I_DATA_15         = 155,
246    I2S1I_BCK             = 164,
247    I2S1I_WS              = 165,
248    I2S1I_DATA_0          = 166,
249    I2S1I_DATA_1          = 167,
250    I2S1I_DATA_2          = 168,
251    I2S1I_DATA_3          = 169,
252    I2S1I_DATA_4          = 170,
253    I2S1I_DATA_5          = 171,
254    I2S1I_DATA_6          = 172,
255    I2S1I_DATA_7          = 173,
256    I2S1I_DATA_8          = 174,
257    I2S1I_DATA_9          = 175,
258    I2S1I_DATA_10         = 176,
259    I2S1I_DATA_11         = 177,
260    I2S1I_DATA_12         = 178,
261    I2S1I_DATA_13         = 179,
262    I2S1I_DATA_14         = 180,
263    I2S1I_DATA_15         = 181,
264    I2S0I_H_SYNC          = 190,
265    I2S0I_V_SYNC          = 191,
266    I2S0I_H_ENABLE        = 192,
267    I2S1I_H_SYNC          = 193,
268    I2S1I_V_SYNC          = 194,
269    I2S1I_H_ENABLE        = 195,
270    U2RXD                 = 198,
271    U2CTS                 = 199,
272    EMAC_MDC              = 200,
273    EMAC_MDI              = 201,
274    EMAC_CRS              = 202,
275    EMAC_COL              = 203,
276    PCMFSYNC              = 204,
277    PCMCLK                = 205,
278    PCMDIN                = 206,
279
280    SD_DATA0              = 512,
281    SD_DATA1,
282    SD_DATA2,
283    SD_DATA3,
284    HS1_DATA0,
285    HS1_DATA1,
286    HS1_DATA2,
287    HS1_DATA3,
288    HS1_DATA4,
289    HS1_DATA5,
290    HS1_DATA6,
291    HS1_DATA7,
292    HS2_DATA0,
293    HS2_DATA1,
294    HS2_DATA2,
295    HS2_DATA3,
296
297    EMAC_TX_CLK,
298    EMAC_RXD2,
299    EMAC_TX_ER,
300    EMAC_RX_CLK,
301    EMAC_RX_ER,
302    EMAC_RXD3,
303    EMAC_RXD0,
304    EMAC_RXD1,
305    EMAC_RX_DV,
306
307    MTDI,
308    MTCK,
309    MTMS,
310}
311
312/// Peripheral output signals for the GPIO mux
313#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
314#[derive(Debug, PartialEq, Copy, Clone)]
315#[cfg_attr(feature = "defmt", derive(defmt::Format))]
316#[doc(hidden)]
317pub enum OutputSignal {
318    SPICLK                   = 0,
319    SPIQ                     = 1,
320    SPID                     = 2,
321    SPIHD                    = 3,
322    SPIWP                    = 4,
323    SPICS0                   = 5,
324    SPICS1                   = 6,
325    SPICS2                   = 7,
326    HSPICLK                  = 8,
327    HSPIQ                    = 9,
328    HSPID                    = 10,
329    HSPICS0                  = 11,
330    HSPIHD                   = 12,
331    HSPIWP                   = 13,
332    U0TXD                    = 14,
333    U0RTS                    = 15,
334    U0DTR                    = 16,
335    U1TXD                    = 17,
336    U1RTS                    = 18,
337    I2S0O_BCK                = 23,
338    I2S1O_BCK                = 24,
339    I2S0O_WS                 = 25,
340    I2S1O_WS                 = 26,
341    I2S0I_BCK                = 27,
342    I2S0I_WS                 = 28,
343    I2CEXT0_SCL              = 29,
344    I2CEXT0_SDA              = 30,
345    SDIO_TOHOSTT             = 31,
346    PWM0_0A                  = 32,
347    PWM0_0B                  = 33,
348    PWM0_1A                  = 34,
349    PWM0_1B                  = 35,
350    PWM0_2A                  = 36,
351    PWM0_2B                  = 37,
352    HSPICS1                  = 61,
353    HSPICS2                  = 62,
354    VSPICLK                  = 63,
355    VSPIQ                    = 64,
356    VSPID                    = 65,
357    VSPIHD                   = 66,
358    VSPIWP                   = 67,
359    VSPICS0                  = 68,
360    VSPICS1                  = 69,
361    VSPICS2                  = 70,
362    LEDC_HS_SIG0             = 71,
363    LEDC_HS_SIG1             = 72,
364    LEDC_HS_SIG2             = 73,
365    LEDC_HS_SIG3             = 74,
366    LEDC_HS_SIG4             = 75,
367    LEDC_HS_SIG5             = 76,
368    LEDC_HS_SIG6             = 77,
369    LEDC_HS_SIG7             = 78,
370    LEDC_LS_SIG0             = 79,
371    LEDC_LS_SIG1             = 80,
372    LEDC_LS_SIG2             = 81,
373    LEDC_LS_SIG3             = 82,
374    LEDC_LS_SIG4             = 83,
375    LEDC_LS_SIG5             = 84,
376    LEDC_LS_SIG6             = 85,
377    LEDC_LS_SIG7             = 86,
378    RMT_SIG_0                = 87,
379    RMT_SIG_1                = 88,
380    RMT_SIG_2                = 89,
381    RMT_SIG_3                = 90,
382    RMT_SIG_4                = 91,
383    RMT_SIG_5                = 92,
384    RMT_SIG_6                = 93,
385    RMT_SIG_7                = 94,
386    I2CEXT1_SCL              = 95,
387    I2CEXT1_SDA              = 96,
388    HOST_CCMD_OD_PULLUP_EN_N = 97,
389    HOST_RST_N_1             = 98,
390    HOST_RST_N_2             = 99,
391    GPIO_SD0                 = 100,
392    GPIO_SD1                 = 101,
393    GPIO_SD2                 = 102,
394    GPIO_SD3                 = 103,
395    GPIO_SD4                 = 104,
396    GPIO_SD5                 = 105,
397    GPIO_SD6                 = 106,
398    GPIO_SD7                 = 107,
399    PWM1_0A                  = 108,
400    PWM1_0B                  = 109,
401    PWM1_1A                  = 110,
402    PWM1_1B                  = 111,
403    PWM1_2A                  = 112,
404    PWM1_2B                  = 113,
405    TWAI_TX                  = 123,
406    TWAI_BUS_OFF_ON          = 124,
407    TWAI_CLKOUT              = 125,
408    I2S0O_DATA_0             = 140,
409    I2S0O_DATA_1             = 141,
410    I2S0O_DATA_2             = 142,
411    I2S0O_DATA_3             = 143,
412    I2S0O_DATA_4             = 144,
413    I2S0O_DATA_5             = 145,
414    I2S0O_DATA_6             = 146,
415    I2S0O_DATA_7             = 147,
416    I2S0O_DATA_8             = 148,
417    I2S0O_DATA_9             = 149,
418    I2S0O_DATA_10            = 150,
419    I2S0O_DATA_11            = 151,
420    I2S0O_DATA_12            = 152,
421    I2S0O_DATA_13            = 153,
422    I2S0O_DATA_14            = 154,
423    I2S0O_DATA_15            = 155,
424    I2S0O_DATA_16            = 156,
425    I2S0O_DATA_17            = 157,
426    I2S0O_DATA_18            = 158,
427    I2S0O_DATA_19            = 159,
428    I2S0O_DATA_20            = 160,
429    I2S0O_DATA_21            = 161,
430    I2S0O_DATA_22            = 162,
431    I2S0O_DATA_23            = 163,
432    I2S1I_BCK                = 164,
433    I2S1I_WS                 = 165,
434    I2S1O_DATA_0             = 166,
435    I2S1O_DATA_1             = 167,
436    I2S1O_DATA_2             = 168,
437    I2S1O_DATA_3             = 169,
438    I2S1O_DATA_4             = 170,
439    I2S1O_DATA_5             = 171,
440    I2S1O_DATA_6             = 172,
441    I2S1O_DATA_7             = 173,
442    I2S1O_DATA_8             = 174,
443    I2S1O_DATA_9             = 175,
444    I2S1O_DATA_10            = 176,
445    I2S1O_DATA_11            = 177,
446    I2S1O_DATA_12            = 178,
447    I2S1O_DATA_13            = 179,
448    I2S1O_DATA_14            = 180,
449    I2S1O_DATA_15            = 181,
450    I2S1O_DATA_16            = 182,
451    I2S1O_DATA_17            = 183,
452    I2S1O_DATA_18            = 184,
453    I2S1O_DATA_19            = 185,
454    I2S1O_DATA_20            = 186,
455    I2S1O_DATA_21            = 187,
456    I2S1O_DATA_22            = 188,
457    I2S1O_DATA_23            = 189,
458    U2TXD                    = 198,
459    U2RTS                    = 199,
460    EMAC_MDC                 = 200,
461    EMAC_MDO                 = 201,
462    EMAC_CRS                 = 202,
463    EMAC_COL                 = 203,
464    BT_AUDIO0RQ              = 204,
465    BT_AUDIO1RQ              = 205,
466    BT_AUDIO2RQ              = 206,
467    BLE_AUDIO0RQ             = 207,
468    BLE_AUDIO1RQ             = 208,
469    BLE_AUDIO2RQ             = 209,
470    PCMFSYNC                 = 210,
471    PCMCLK                   = 211,
472    PCMDOUT                  = 212,
473    BLE_AUDIO_SYNC0_P        = 213,
474    BLE_AUDIO_SYNC1_P        = 214,
475    BLE_AUDIO_SYNC2_P        = 215,
476    ANT_SEL0                 = 216,
477    ANT_SEL1                 = 217,
478    ANT_SEL2                 = 218,
479    ANT_SEL3                 = 219,
480    ANT_SEL4                 = 220,
481    ANT_SEL5                 = 221,
482    ANT_SEL6                 = 222,
483    ANT_SEL7                 = 223,
484    SIGNAL_224               = 224,
485    SIGNAL_225               = 225,
486    SIGNAL_226               = 226,
487    SIGNAL_227               = 227,
488    SIGNAL_228               = 228,
489    GPIO                     = 256,
490
491    CLK_OUT1                 = 512,
492    CLK_OUT2,
493    CLK_OUT3,
494    SD_CLK,
495    SD_CMD,
496    SD_DATA0,
497    SD_DATA1,
498    SD_DATA2,
499    SD_DATA3,
500    HS1_CLK,
501    HS1_CMD,
502    HS1_DATA0,
503    HS1_DATA1,
504    HS1_DATA2,
505    HS1_DATA3,
506    HS1_DATA4,
507    HS1_DATA5,
508    HS1_DATA6,
509    HS1_DATA7,
510    HS1_STROBE,
511    HS2_CLK,
512    HS2_CMD,
513    HS2_DATA0,
514    HS2_DATA1,
515    HS2_DATA2,
516    HS2_DATA3,
517
518    EMAC_TX_CLK,
519    EMAC_TX_ER,
520    EMAC_TXD3,
521    EMAC_RX_ER,
522    EMAC_TXD2,
523    EMAC_CLK_OUT,
524    EMAC_CLK_180,
525    EMAC_TXD0,
526    EMAC_TX_EN,
527    EMAC_TXD1,
528
529    MTDO,
530}
531
532macro_rules! rtcio_analog {
533    (
534        $pin_num:expr, $rtc_pin:expr, $pin_reg:expr, $prefix:pat, $hold:ident $(, $rue:literal)?
535    ) => {
536        paste::paste! {
537            impl $crate::gpio::RtcPin for $crate::peripherals::[<GPIO $pin_num>]<'_> {
538                fn rtc_number(&self) -> u8 {
539                    $rtc_pin
540                }
541
542                /// Set the RTC properties of the pin. If `mux` is true then then pin is
543                /// routed to RTC, when false it is routed to IO_MUX.
544                fn rtc_set_config(&self, input_enable: bool, mux: bool, func: $crate::gpio::RtcFunction) {
545                    // disable input
546                    $crate::peripherals::RTC_IO::regs()
547                        .$pin_reg.modify(|_,w| unsafe {
548                            w.[<$prefix fun_ie>]().bit(input_enable);
549                            w.[<$prefix mux_sel>]().bit(mux);
550                            w.[<$prefix fun_sel>]().bits(func as u8)
551                        });
552                }
553
554                fn rtcio_pad_hold(&self, enable: bool) {
555                    $crate::peripherals::LPWR::regs()
556                        .hold_force()
557                        .modify(|_, w| w.$hold().bit(enable));
558                }
559            }
560
561            $(
562                // FIXME: replace with $(ignore($rue)) once stable
563                $crate::ignore!($rue);
564                impl $crate::gpio::RtcPinWithResistors for $crate::peripherals::[<GPIO $pin_num>]<'_> {
565                    fn rtcio_pullup(&self, enable: bool) {
566                        $crate::peripherals::RTC_IO::regs()
567                            .$pin_reg.modify(|_, w| w.[< $prefix rue >]().bit(enable));
568                    }
569
570                    fn rtcio_pulldown(&self, enable: bool) {
571                        $crate::peripherals::RTC_IO::regs()
572                            .$pin_reg.modify(|_, w| w.[< $prefix rde >]().bit(enable));
573                    }
574                }
575            )?
576
577            impl $crate::gpio::AnalogPin for $crate::peripherals::[<GPIO $pin_num>]<'_> {
578                /// Configures the pin for analog mode.
579                fn set_analog(&self, _: $crate::private::Internal) {
580                    use $crate::gpio::RtcPin;
581                    let rtcio = $crate::peripherals::RTC_IO::regs();
582
583                    // disable output
584                    rtcio.enable_w1tc().write(|w| unsafe { w.enable_w1tc().bits(1 << self.rtc_number()) });
585
586                    // disable open drain
587                    rtcio.pin(self.rtc_number() as usize).modify(|_,w| w.pad_driver().bit(false));
588
589                    rtcio.$pin_reg.modify(|_,w| {
590                        w.[<$prefix fun_ie>]().clear_bit();
591
592                        // Connect pin to analog / RTC module instead of standard GPIO
593                        w.[<$prefix mux_sel>]().set_bit();
594
595                        // Select function "RTC function 1" (GPIO) for analog use
596                        unsafe { w.[<$prefix fun_sel>]().bits(0b00) };
597
598                        // Disable pull-up and pull-down resistors on the pin, if it has them
599                        $(
600                            // FIXME: replace with $(ignore($rue)) once stable
601                            $crate::ignore!($rue);
602                            w.[<$prefix rue>]().bit(false);
603                            w.[<$prefix rde>]().bit(false);
604                        )?
605
606                        w
607                    });
608                }
609            }
610        }
611    };
612
613    (
614        $( ( $pin_num:expr, $rtc_pin:expr, $pin_reg:expr, $prefix:pat, $hold:ident $(, $rue:literal )? ) )+
615    ) => {
616        $(
617            rtcio_analog!($pin_num, $rtc_pin, $pin_reg, $prefix, $hold $(, $rue )?);
618        )+
619
620        pub(crate) fn errata36(pin: $crate::gpio::AnyPin<'_>, pull_up: bool, pull_down: bool) {
621            use $crate::gpio::{Pin, RtcPinWithResistors};
622
623            let has_pullups = match pin.number() {
624                $(
625                    $( $pin_num => $rue, )?
626                )+
627                _ => false,
628            };
629
630            if has_pullups {
631                pin.rtcio_pullup(pull_up);
632                pin.rtcio_pulldown(pull_down);
633            }
634        }
635    };
636}
637
638/// Common functionality for all touch pads
639macro_rules! touch {
640    (@pin_specific $touch_num:expr, true) => {
641        paste::paste! {
642            RTC_IO::regs().[< touch_pad $touch_num >]().write(|w| unsafe {
643                w.xpd().set_bit();
644                // clear input_enable
645                w.fun_ie().clear_bit();
646                // Connect pin to analog / RTC module instead of standard GPIO
647                w.mux_sel().set_bit();
648                // Disable pull-up and pull-down resistors on the pin
649                w.rue().clear_bit();
650                w.rde().clear_bit();
651                w.tie_opt().clear_bit();
652                // Select function "RTC function 1" (GPIO) for analog use
653                w.fun_sel().bits(0b00)
654            });
655        }
656    };
657
658    (@pin_specific $touch_num:expr, false) => {
659        paste::paste! {
660            RTC_IO::regs().[< touch_pad $touch_num >]().write(|w| {
661                w.xpd().set_bit();
662                w.tie_opt().clear_bit()
663            });
664        }
665    };
666
667    (
668        $(
669            (
670                $touch_num:literal, $pin_num:literal, $touch_out_reg:expr, $touch_thres_reg:expr, $normal_pin:literal
671            )
672        )+
673    ) => {
674        $(
675        impl $crate::gpio::TouchPin for paste::paste!($crate::peripherals::[<GPIO $pin_num>]<'_>) {
676            fn set_touch(&self, _: $crate::private::Internal) {
677                use $crate::peripherals::{GPIO, RTC_IO, SENS};
678                use $crate::gpio::RtcPin;
679
680                let gpio = GPIO::regs();
681                let rtcio = RTC_IO::regs();
682                let sens = SENS::regs();
683
684                // Pad to normal mode (not open-drain)
685                gpio.pin(self.rtc_number() as usize).write(|w| w.pad_driver().clear_bit());
686
687                // clear output
688                rtcio
689                    .enable_w1tc()
690                    .write(|w| unsafe { w.enable_w1tc().bits(1 << self.rtc_number()) });
691                paste::paste! {
692                    sens . $touch_thres_reg ()
693                        .write(|w| unsafe {
694                            w. [<touch_out_th $touch_num>] ().bits(
695                                0b0 // Default: 0 for esp32 gets overridden later anyway.
696                            )
697                        });
698
699                    touch!( @pin_specific $touch_num, $normal_pin );
700
701                    // enable the pin
702                    sens.sar_touch_enable().modify(|r, w| unsafe {
703                        w.touch_pad_worken().bits(
704                            r.touch_pad_worken().bits() | ( 1 << $touch_num )
705                        )
706                    });
707                }
708            }
709
710            fn touch_measurement(&self, _: $crate::private::Internal) -> u16 {
711                paste::paste! {
712                    $crate::peripherals::SENS::regs() . $touch_out_reg ().read()
713                        . [<touch_meas_out $touch_num>] ().bits()
714                }
715            }
716
717            fn touch_nr(&self, _: $crate::private::Internal) -> u8 {
718                $touch_num
719            }
720
721            fn set_threshold(&self, threshold: u16, _: $crate::private::Internal) {
722                paste::paste! {
723                    $crate::peripherals::SENS::regs() . $touch_thres_reg ()
724                        .write(|w| unsafe {
725                            w. [<touch_out_th $touch_num>] ().bits(threshold)
726                        });
727                }
728            }
729        })+
730    };
731}
732
733rtcio_analog! {
734    (36, 0,  sensor_pads(),    sense1_, sense1          )
735    (37, 1,  sensor_pads(),    sense2_, sense2          )
736    (38, 2,  sensor_pads(),    sense3_, sense3          )
737    (39, 3,  sensor_pads(),    sense4_, sense4          )
738    (34, 4,  adc_pad(),        adc1_,   adc1            )
739    (35, 5,  adc_pad(),        adc2_,   adc2            )
740    (25, 6,  pad_dac1(),       "",      pdac1,      true)
741    (26, 7,  pad_dac2(),       "",      pdac2,      true)
742    (33, 8,  xtal_32k_pad(),   x32n_,   x32n,       true)
743    (32, 9,  xtal_32k_pad(),   x32p_,   x32p,       true)
744    (4,  10, touch_pad0(),     "",      touch_pad0, true)
745    (0,  11, touch_pad1(),     "",      touch_pad1, true)
746    (2,  12, touch_pad2(),     "",      touch_pad2, true)
747    (15, 13, touch_pad3(),     "",      touch_pad3, true)
748    (13, 14, touch_pad4(),     "",      touch_pad4, true)
749    (12, 15, touch_pad5(),     "",      touch_pad5, true)
750    (14, 16, touch_pad6(),     "",      touch_pad6, true)
751    (27, 17, touch_pad7(),     "",      touch_pad7, true)
752}
753
754touch! {
755    // touch_nr, pin_nr, touch_out_reg, touch_thres_reg, normal_pin
756    (0, 4,  sar_touch_out1, sar_touch_thres1, true)
757    (1, 0,  sar_touch_out1, sar_touch_thres1, true)
758    (2, 2,  sar_touch_out2, sar_touch_thres2, true)
759    (3, 15, sar_touch_out2, sar_touch_thres2, true)
760    (4, 13, sar_touch_out3, sar_touch_thres3, true)
761    (5, 12, sar_touch_out3, sar_touch_thres3, true)
762    (6, 14, sar_touch_out4, sar_touch_thres4, true)
763    (7, 27, sar_touch_out4, sar_touch_thres4, true)
764    // ---
765    (8, 33, sar_touch_out5, sar_touch_thres5, false)
766    (9, 32, sar_touch_out5, sar_touch_thres5, false)
767}
768
769#[derive(Clone, Copy)]
770pub(crate) enum InterruptStatusRegisterAccess {
771    Bank0,
772    Bank1,
773}
774
775impl InterruptStatusRegisterAccess {
776    pub(crate) fn interrupt_status_read(self) -> u32 {
777        match self {
778            Self::Bank0 => GPIO::regs().status().read().bits(),
779            Self::Bank1 => GPIO::regs().status1().read().bits(),
780        }
781    }
782}
esp_hal/soc/esp32/gpio.rs

esp_hal/soc/esp32/
gpio.rs
