Module efuse

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Available on crate feature unstable only.

Expand description

§Stability

This API is marked as unstable and is only available when the unstable crate feature is enabled. This comes with no stability guarantees, and could be changed or removed at any time.

§Reading of eFuses (ESP32-S3)

§Overview

The efuse module provides functionality for reading eFuse data from the ESP32-S3 chip, allowing access to various chip-specific information such as:

MAC address
Chip revision

and more. It is useful for retrieving chip-specific configuration and identification data during runtime.

The Efuse struct represents the eFuse peripheral and is responsible for reading various eFuse fields and values.

§Examples

§Read data from the eFuse storage.


let mac_address = Efuse::read_base_mac_address();

println!(
    "MAC: {:#X}:{:#X}:{:#X}:{:#X}:{:#X}:{:#X}",
    mac_address[0],
    mac_address[1],
    mac_address[2],
    mac_address[3],
    mac_address[4],
    mac_address[5]
);

println!("MAC address {:02x?}", Efuse::mac_address());
println!("Flash Encryption {:?}", Efuse::flash_encryption());

Structs§

Efuse: A struct representing the eFuse functionality of the chip.

Constants§

ADC1_CAL_VOL_ATTEN0: ADC1 calibration voltage at atten0
ADC1_CAL_VOL_ATTEN1: ADC1 calibration voltage at atten1
ADC1_CAL_VOL_ATTEN2: ADC1 calibration voltage at atten2
ADC1_CAL_VOL_ATTEN3: ADC1 calibration voltage at atten3
ADC1_INIT_CODE_ATTEN0: ADC1 init code at atten0
ADC1_INIT_CODE_ATTEN1: ADC1 init code at atten1
ADC1_INIT_CODE_ATTEN2: ADC1 init code at atten2
ADC1_INIT_CODE_ATTEN3: ADC1 init code at atten3
ADC2_CAL_VOL_ATTEN0: ADC2 calibration voltage at atten0
ADC2_CAL_VOL_ATTEN1: ADC2 calibration voltage at atten1
ADC2_CAL_VOL_ATTEN2: ADC2 calibration voltage at atten2
ADC2_CAL_VOL_ATTEN3: ADC2 calibration voltage at atten3
ADC2_INIT_CODE_ATTEN0: ADC2 init code at atten0
ADC2_INIT_CODE_ATTEN1: ADC2 init code at atten1
ADC2_INIT_CODE_ATTEN2: ADC2 init code at atten2
ADC2_INIT_CODE_ATTEN3: ADC2 init code at atten3
BLK_VERSION_MAJOR: BLK_VERSION_MAJOR of BLOCK2
BLK_VERSION_MINOR: BLK_VERSION_MINOR
BLOCK_KEY0: Key0 or user data
BLOCK_KEY1: Key1 or user data
BLOCK_KEY2: Key2 or user data
BLOCK_KEY3: Key3 or user data
BLOCK_KEY4: Key4 or user data
BLOCK_KEY5: Key5 or user data
BLOCK_SYS_DATA2: System data part 2 (reserved)
BLOCK_USR_DATA: User data
BTLC_GPIO_ENABLE: Bluetooth GPIO signal output security level control
CUSTOM_MAC: Custom MAC
DIG_DBIAS_HVT: BLOCK1 digital dbias when hvt
DISABLE_BLK_VERSION_MAJOR: Disables check of blk version major
DISABLE_WAFER_VERSION_MAJOR: Disables check of wafer version major
DIS_APP_CPU: Disable app cpu
DIS_DCACHE: Set this bit to disable Dcache
DIS_DIRECT_BOOT: Disable direct boot mode
DIS_DOWNLOAD_DCACHE: Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0; 1; 2; 3; 6; 7)
DIS_DOWNLOAD_ICACHE: Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7)
DIS_DOWNLOAD_MANUAL_ENCRYPT: Set this bit to disable flash encryption when in download boot modes
DIS_DOWNLOAD_MODE: Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7)
DIS_FORCE_DOWNLOAD: Set this bit to disable the function that forces chip into download mode
DIS_ICACHE: Set this bit to disable Icache
DIS_PAD_JTAG: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently
DIS_RTC_RAM_BOOT: Set this bit to disable boot from RTC RAM
DIS_TWAI: Set this bit to disable CAN function
DIS_USB_JTAG: Set this bit to disable function of usb switch to jtag in module of usb device
DIS_USB_OTG: Set this bit to disable USB function
DIS_USB_OTG_DOWNLOAD_MODE: Set this bit to disable download through USB-OTG
DIS_USB_SERIAL_JTAG: Set this bit to disable usb device
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE: Set this bit to disable UART download mode through USB
DIS_USB_SERIAL_JTAG_ROM_PRINT: USB printing
ENABLE_SECURITY_DOWNLOAD: Set this bit to enable secure UART download mode
FLASH_CAP: Flash capacity
FLASH_ECC_EN: Set 1 to enable ECC for flash boot
FLASH_ECC_MODE: Flash ECC mode in ROM
FLASH_PAGE_SIZE: Set Flash page size
FLASH_TEMP: Flash temperature
FLASH_TPUW: Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value
FLASH_TYPE: SPI flash type
FLASH_VENDOR: Flash vendor
FORCE_SEND_RESUME: Set this bit to force ROM code to send a resume command during SPI boot
KEY_PURPOSE_0: Purpose of Key0
KEY_PURPOSE_1: Purpose of Key1
KEY_PURPOSE_2: Purpose of Key2
KEY_PURPOSE_3: Purpose of Key3
KEY_PURPOSE_4: Purpose of Key4
KEY_PURPOSE_5: Purpose of Key5
K_DIG_LDO: BLOCK1 K_DIG_LDO
K_RTC_LDO: BLOCK1 K_RTC_LDO
MAC0: MAC address
MAC1: MAC address
OCODE: ADC OCode
OPTIONAL_UNIQUE_ID: Optional unique 128-bit ID
PIN_POWER_SELECTION: Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized
PKG_VERSION: Package version
POWERGLITCH_EN: Set this bit to enable power glitch function
POWER_GLITCH_DSENSE: Sample delay configuration of power glitch
PSRAM_CAP: PSRAM capacity
PSRAM_CAP_3: PSRAM capacity bit 3
PSRAM_TEMP: PSRAM temperature
PSRAM_VENDOR: PSRAM vendor
RD_DIS: Disable reading from BlOCK4-10
RESERVED_0_162: reserved
RESERVED_1_137: reserved
RESERVED_1_176: reserved
RESERVED_1_180: reserved
RESERVED_2_130: reserved
RESERVED_2_255: reserved
RESERVED_3_192: reserved
RESERVED_3_248: reserved
RPT4_RESERVED0: Reserved (used for four backups method)
SECURE_BOOT_AGGRESSIVE_REVOKE: Set this bit to enable revoking aggressive secure boot
SECURE_BOOT_EN: Set this bit to enable secure boot
SECURE_BOOT_KEY_REVOKE0: Revoke 1st secure boot key
SECURE_BOOT_KEY_REVOKE1: Revoke 2nd secure boot key
SECURE_BOOT_KEY_REVOKE2: Revoke 3rd secure boot key
SECURE_VERSION: Secure version (used by ESP-IDF anti-rollback feature)
SOFT_DIS_JTAG: Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module
SPI_BOOT_CRYPT_CNT: Enables flash encryption when 1 or 3 bits are set and disabled otherwise
SPI_PAD_CONFIG_CLK: SPI_PAD_configure CLK
SPI_PAD_CONFIG_CS: SPI_PAD_configure CS
SPI_PAD_CONFIG_D: SPI_PAD_configure D(D0)
SPI_PAD_CONFIG_D4: SPI_PAD_configure D4
SPI_PAD_CONFIG_D5: SPI_PAD_configure D5
SPI_PAD_CONFIG_D6: SPI_PAD_configure D6
SPI_PAD_CONFIG_D7: SPI_PAD_configure D7
SPI_PAD_CONFIG_DQS: SPI_PAD_configure DQS
SPI_PAD_CONFIG_HD: SPI_PAD_configure HD(D3)
SPI_PAD_CONFIG_Q: SPI_PAD_configure Q(D1)
SPI_PAD_CONFIG_WP: SPI_PAD_configure WP(D2)
STRAP_JTAG_SEL: Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio3 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0
TEMP_CALIB: Temperature calibration data
UART_PRINT_CONTROL: Set the default UART boot message output mode
USB_DREFH: Controls single-end input threshold vrefh; 1.76 V to 2 V with step of 80 mV; stored in eFuse
USB_DREFL: Controls single-end input threshold vrefl; 0.8 V to 1.04 V with step of 80 mV; stored in eFuse
USB_EXCHG_PINS: Set this bit to exchange USB D+ and D- pins
USB_EXT_PHY_ENABLE: Set this bit to enable external PHY
USB_PHY_SEL: This bit is used to switch internal PHY and external PHY for USB OTG and USB Device
VDD_SPI_DCAP: Prevents SPI regulator from overshoot
VDD_SPI_DCURLIM: Tunes the current limit threshold of SPI regulator when tieh=0; about 800 mA/(8+d)
VDD_SPI_DREFH: SPI regulator high voltage reference
VDD_SPI_DREFL: SPI regulator low voltage reference
VDD_SPI_DREFM: SPI regulator medium voltage reference
VDD_SPI_ENCURLIM: Set SPI regulator to 1 to enable output current limit
VDD_SPI_EN_INIT: Set SPI regulator to 0 to configure init[1:0]=0
VDD_SPI_FORCE: Set this bit and force to use the configuration of eFuse to configure VDD_SPI
VDD_SPI_INIT: Adds resistor from LDO output to ground
VDD_SPI_MODECURLIM: SPI regulator switches current limit mode
VDD_SPI_TIEH: If VDD_SPI_FORCE is 1; determines VDD_SPI voltage
VDD_SPI_XPD: SPI regulator power up signal
V_DIG_DBIAS20: BLOCK1 voltage of digital dbias20
V_RTC_DBIAS20: BLOCK1 voltage of rtc dbias20
WAFER_VERSION_MAJOR: WAFER_VERSION_MAJOR
WAFER_VERSION_MINOR_HI: WAFER_VERSION_MINOR most significant bit
WAFER_VERSION_MINOR_LO: WAFER_VERSION_MINOR least significant bits
WDT_DELAY_SEL: RTC watchdog timeout threshold; in unit of slow clock cycle
WR_DIS: Disable programming of individual eFuses

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