esp_hal/aes/
esp32s3.rs

1use crate::aes::{ALIGN_SIZE, Aes, Aes128, Aes256, AesFlavour, Mode};
2
3impl Aes<'_> {
4    pub(super) fn init(&mut self) {
5        self.write_dma(false);
6    }
7
8    fn write_dma(&mut self, enable_dma: bool) {
9        self.regs()
10            .dma_enable()
11            .write(|w| w.dma_enable().bit(enable_dma));
12    }
13
14    pub(super) fn write_key(&mut self, key: &[u8]) {
15        let key_len = self.regs().key_iter().count();
16        debug_assert!(key.len() <= key_len * ALIGN_SIZE);
17        debug_assert_eq!(key.len() % ALIGN_SIZE, 0);
18        self.alignment_helper
19            .volatile_write_regset(self.regs().key(0).as_ptr(), key, key_len);
20    }
21
22    pub(super) fn write_block(&mut self, block: &[u8]) {
23        let text_in_len = self.regs().text_in_iter().count();
24        debug_assert_eq!(block.len(), text_in_len * ALIGN_SIZE);
25        self.alignment_helper.volatile_write_regset(
26            self.regs().text_in(0).as_ptr(),
27            block,
28            text_in_len,
29        );
30    }
31
32    pub(super) fn write_mode(&self, mode: Mode) {
33        self.regs().mode().write(|w| unsafe { w.bits(mode as _) });
34    }
35
36    pub(super) fn write_start(&self) {
37        self.regs().trigger().write(|w| w.trigger().set_bit());
38    }
39
40    pub(super) fn read_idle(&mut self) -> bool {
41        self.regs().state().read().state().bits() == 0
42    }
43
44    pub(super) fn read_block(&self, block: &mut [u8]) {
45        let text_out_len = self.regs().text_out_iter().count();
46        debug_assert_eq!(block.len(), text_out_len * ALIGN_SIZE);
47        self.alignment_helper.volatile_read_regset(
48            self.regs().text_out(0).as_ptr(),
49            block,
50            text_out_len,
51        );
52    }
53}
54
55impl AesFlavour for Aes128 {
56    type KeyType<'b> = &'b [u8; 16];
57}
58
59impl AesFlavour for Aes256 {
60    type KeyType<'b> = &'b [u8; 32];
61}
esp_hal/aes/esp32s3.rs

esp_hal/aes/
esp32s3.rs
