esp_hal/lcd_cam/lcd/
mod.rs

1//! LCD
2//!
3//! ## Overview
4//! The LCD module is designed to send parallel video data signals, and its bus
5//! supports RGB, MOTO6800, and I8080 interface timing.
6//!
7//! For more information on these modes, please refer to the documentation in
8//! their respective modules.
9
10use super::GenericPeripheralGuard;
11use crate::{peripherals::LCD_CAM, system};
12
13pub mod dpi;
14pub mod i8080;
15
16/// Represents an LCD interface.
17pub struct Lcd<'d, Dm: crate::DriverMode> {
18    /// The `LCD_CAM` peripheral reference for managing the LCD functionality.
19    pub(crate) lcd_cam: LCD_CAM<'d>,
20
21    /// A marker for the mode of operation (blocking or asynchronous).
22    pub(crate) _mode: core::marker::PhantomData<Dm>,
23
24    pub(super) _guard: GenericPeripheralGuard<{ system::Peripheral::LcdCam as u8 }>,
25}
26
27#[derive(Debug, Clone, Copy, PartialEq, Default)]
28#[cfg_attr(feature = "defmt", derive(defmt::Format))]
29/// Represents the clock mode configuration for the LCD interface.
30pub struct ClockMode {
31    /// The polarity of the clock signal (idle high or low).
32    pub polarity: Polarity,
33
34    /// The phase of the clock signal (shift on the rising or falling edge).
35    pub phase: Phase,
36}
37
38#[derive(Debug, Clone, Copy, PartialEq, Default)]
39#[cfg_attr(feature = "defmt", derive(defmt::Format))]
40/// Represents the polarity of the clock signal for the LCD interface.
41pub enum Polarity {
42    /// The clock signal is low when idle.
43    #[default]
44    IdleLow,
45
46    /// The clock signal is high when idle.
47    IdleHigh,
48}
49
50#[derive(Debug, Clone, Copy, PartialEq, Default)]
51#[cfg_attr(feature = "defmt", derive(defmt::Format))]
52/// Represents the phase of the clock signal for the LCD interface.
53pub enum Phase {
54    /// Data is shifted on the low (falling) edge of the clock signal.
55    #[default]
56    ShiftLow,
57
58    /// Data is shifted on the high (rising) edge of the clock signal.
59    ShiftHigh,
60}
61
62#[derive(Debug, Clone, Copy, PartialEq, Default)]
63#[cfg_attr(feature = "defmt", derive(defmt::Format))]
64/// Represents the delay mode for the LCD signal output.
65pub enum DelayMode {
66    /// Output without delay.
67    #[default]
68    None        = 0,
69    /// Delayed by the rising edge of LCD_CLK.
70    RaisingEdge = 1,
71    /// Delayed by the falling edge of LCD_CLK.
72    FallingEdge = 2,
73}
esp_hal/lcd_cam/lcd/mod.rs

esp_hal/lcd_cam/lcd/
mod.rs
