esp_hal/rtc_cntl/rtc/
esp32s3.rs

1use strum::FromRepr;
2
3use crate::{
4    clock::XtalClock,
5    peripherals::LPWR,
6    rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock},
7};
8
9pub(crate) fn init() {}
10
11pub(crate) fn configure_clock() {
12    assert!(matches!(RtcClock::xtal_freq(), XtalClock::_40M));
13
14    RtcClock::set_fast_freq(RtcFastClock::RtcFastClock8m);
15
16    let cal_val = loop {
17        RtcClock::set_slow_freq(RtcSlowClock::RtcSlowClockRtc);
18
19        let res = RtcClock::calibrate(RtcCalSel::RtcCalRtcMux, 1024);
20        if res != 0 {
21            break res;
22        }
23    };
24
25    LPWR::regs().store1().write(|w| unsafe { w.bits(cal_val) });
26}
27
28// Terminology:
29//
30// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
31//               reset vector
32// Core Reset:   Reset the whole digital system except RTC sub-system
33// System Reset: Reset the whole digital system, including RTC sub-system
34// Chip Reset:   Reset the whole chip, including the analog part
35
36/// SOC Reset Reason.
37#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
38pub enum SocResetReason {
39    /// Power on reset
40    ///
41    /// In ESP-IDF this value (0x01) can *also* be `ChipBrownOut` or
42    /// `ChipSuperWdt`, however that is not really compatible with Rust-style
43    /// enums.
44    ChipPowerOn   = 0x01,
45    /// Software resets the digital core by RTC_CNTL_SW_SYS_RST
46    CoreSw        = 0x03,
47    /// Deep sleep reset the digital core
48    CoreDeepSleep = 0x05,
49    /// Main watch dog 0 resets digital core
50    CoreMwdt0     = 0x07,
51    /// Main watch dog 1 resets digital core
52    CoreMwdt1     = 0x08,
53    /// RTC watch dog resets digital core
54    CoreRtcWdt    = 0x09,
55    /// Main watch dog 0 resets CPU
56    ///
57    /// In ESP-IDF there are `Cpu0Mwdt0` and `Cpu1Mwdt0`, however they have the
58    /// same values.
59    CpuMwdt0      = 0x0B,
60    /// Software resets CPU by RTC_CNTL_SW_(PRO|APP)CPU_RST
61    ///
62    /// In ESP-IDF there are `Cpu0Sw` and `Cpu1Sw`, however they have the same
63    /// values.
64    CpuSw         = 0x0C,
65    /// RTC watch dog resets CPU
66    ///
67    /// In ESP-IDF there are `Cpu0RtcWdt` and `Cpu1RtcWdt`, however they have
68    /// the same values.
69    CpuRtcWdt     = 0x0D,
70    /// VDD voltage is not stable and resets the digital core
71    SysBrownOut   = 0x0F,
72    /// RTC watch dog resets digital core and rtc module
73    SysRtcWdt     = 0x10,
74    /// Main watch dog 1 resets CPU
75    ///
76    /// In ESP-IDF there are `Cpu0Mwdt1` and `Cpu1Mwdt1`, however they have the
77    /// same values.
78    CpuMwdt1      = 0x11,
79    /// Super watch dog resets the digital core and rtc module
80    SysSuperWdt   = 0x12,
81    /// Glitch on clock resets the digital core and rtc module
82    SysClkGlitch  = 0x13,
83    /// eFuse CRC error resets the digital core
84    CoreEfuseCrc  = 0x14,
85    /// USB UART resets the digital core
86    CoreUsbUart   = 0x15,
87    /// USB JTAG resets the digital core
88    CoreUsbJtag   = 0x16,
89    /// Glitch on power resets the digital core
90    CorePwrGlitch = 0x17,
91}
esp_hal/rtc_cntl/rtc/esp32s3.rs

esp_hal/rtc_cntl/rtc/
esp32s3.rs
