esp_hal/rtc_cntl/rtc/
esp32.rs

1use strum::FromRepr;
2
3use crate::{
4    peripherals::LPWR,
5    rtc_cntl::{RtcCalSel, RtcClock, RtcFastClock, RtcSlowClock},
6};
7
8pub(crate) fn init() {}
9
10pub(crate) fn configure_clock() {
11    RtcClock::set_fast_freq(RtcFastClock::RtcFastClock8m);
12
13    let cal_val = loop {
14        RtcClock::set_slow_freq(RtcSlowClock::RtcSlowClockRtc);
15
16        let res = RtcClock::calibrate(RtcCalSel::RtcCalRtcMux, 1024);
17        if res != 0 {
18            break res;
19        }
20    };
21
22    LPWR::regs().store1().write(|w| unsafe { w.bits(cal_val) });
23}
24
25// Terminology:
26//
27// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
28//               reset vector
29// Core Reset:   Reset the whole digital system except RTC sub-system
30// System Reset: Reset the whole digital system, including RTC sub-system
31// Chip Reset:   Reset the whole chip, including the analog part
32
33#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
34/// SOC Reset Reason.
35pub enum SocResetReason {
36    /// Power on reset
37    ChipPowerOn   = 0x01,
38    /// Software resets the digital core
39    CoreSw        = 0x03,
40    /// Deep sleep reset the digital core
41    CoreDeepSleep = 0x05,
42    /// SDIO module resets the digital core
43    CoreSdio      = 0x06,
44    /// Main watch dog 0 resets digital core
45    CoreMwdt0     = 0x07,
46    /// Main watch dog 1 resets digital core
47    CoreMwdt1     = 0x08,
48    /// RTC watch dog resets digital core
49    CoreRtcWdt    = 0x09,
50    /// Main watch dog 0 resets CPU
51    ///
52    /// In ESP-IDF there are `Cpu0Mwdt1` and `Cpu1Mwdt1`, however they have the
53    /// same values.
54    CpuMwdt0      = 0x0B,
55    /// Software resets CPU
56    ///
57    /// In ESP-IDF there are `Cpu0Sw` and `Cpu1Sw`, however they have the same
58    /// values.
59    Cpu0Sw        = 0x0C,
60    /// RTC watch dog resets CPU
61    ///
62    /// In ESP-IDF there are `Cpu0RtcWdt` and `Cpu1RtcWdt`, however they have
63    /// the same values.
64    Cpu0RtcWdt    = 0x0D,
65    /// CPU0 resets CPU1 by DPORT_APPCPU_RESETTING
66    Cpu1Cpu0      = 0x0E,
67    /// Reset when the VDD voltage is not stable
68    SysBrownOut   = 0x0F,
69    /// RTC watch dog resets digital core and rtc module
70    SysRtcWdt     = 0x10,
71}
esp_hal/rtc_cntl/rtc/esp32.rs

esp_hal/rtc_cntl/rtc/
esp32.rs
