esp_hal/aes/
esp32s2.rs

1use crate::aes::{ALIGN_SIZE, Aes, Aes128, Aes192, Aes256, AesFlavour, Endianness, Mode};
2
3impl Aes<'_> {
4    pub(super) fn init(&mut self) {
5        self.write_dma(false);
6        self.write_endianness(
7            Endianness::BigEndian,
8            Endianness::BigEndian,
9            Endianness::BigEndian,
10            Endianness::BigEndian,
11            Endianness::BigEndian,
12            Endianness::BigEndian,
13        );
14    }
15
16    fn write_dma(&mut self, enable_dma: bool) {
17        self.regs()
18            .dma_enable()
19            .write(|w| w.dma_enable().bit(enable_dma));
20    }
21
22    pub(super) fn write_key(&mut self, key: &[u8]) {
23        let key_len = self.regs().key_iter().count();
24        debug_assert!(key.len() <= key_len * ALIGN_SIZE);
25        debug_assert_eq!(key.len() % ALIGN_SIZE, 0);
26        self.alignment_helper
27            .volatile_write_regset(self.regs().key(0).as_ptr(), key, key_len);
28    }
29
30    pub(super) fn write_block(&mut self, block: &[u8]) {
31        let text_in_len = self.regs().text_in_iter().count();
32        debug_assert_eq!(block.len(), text_in_len * ALIGN_SIZE);
33        self.alignment_helper.volatile_write_regset(
34            self.regs().text_in(0).as_ptr(),
35            block,
36            text_in_len,
37        );
38    }
39
40    pub(super) fn write_mode(&self, mode: Mode) {
41        self.regs().mode().write(|w| unsafe { w.bits(mode as _) });
42    }
43
44    /// Configures how the state matrix would be laid out.
45    pub fn write_endianness(
46        &mut self,
47        input_text_word_endianess: Endianness,
48        input_text_byte_endianess: Endianness,
49        output_text_word_endianess: Endianness,
50        output_text_byte_endianess: Endianness,
51        key_word_endianess: Endianness,
52        key_byte_endianess: Endianness,
53    ) {
54        let mut to_write = 0_u32;
55        to_write |= key_byte_endianess as u32;
56        to_write |= (key_word_endianess as u32) << 1;
57        to_write |= (input_text_byte_endianess as u32) << 2;
58        to_write |= (input_text_word_endianess as u32) << 3;
59        to_write |= (output_text_byte_endianess as u32) << 4;
60        to_write |= (output_text_word_endianess as u32) << 5;
61        self.regs().endian().write(|w| unsafe { w.bits(to_write) });
62    }
63
64    pub(super) fn write_start(&self) {
65        self.regs().trigger().write(|w| w.trigger().set_bit());
66    }
67
68    pub(super) fn read_idle(&mut self) -> bool {
69        self.regs().state().read().state().bits() == 0
70    }
71
72    pub(super) fn read_block(&self, block: &mut [u8]) {
73        let text_out_len = self.regs().text_out_iter().count();
74        debug_assert_eq!(block.len(), text_out_len * ALIGN_SIZE);
75        self.alignment_helper.volatile_read_regset(
76            self.regs().text_out(0).as_ptr(),
77            block,
78            text_out_len,
79        );
80    }
81}
82
83impl AesFlavour for Aes128 {
84    type KeyType<'b> = &'b [u8; 16];
85}
86
87impl AesFlavour for Aes192 {
88    type KeyType<'b> = &'b [u8; 24];
89}
90
91impl AesFlavour for Aes256 {
92    type KeyType<'b> = &'b [u8; 32];
93}
esp_hal/aes/esp32s2.rs

esp_hal/aes/
esp32s2.rs
