esp_hal/efuse/esp32/
fields.rs

1//! This file was automatically generated, please do not edit it manually!
2//!
3//! Generated: 2025-05-30 12:24
4//! Version:   369d2d860d34e777c0f7d545a7dfc3c4
5
6#![allow(clippy::empty_docs)]
7
8use crate::efuse::EfuseField;
9
10/// Efuse write disable mask
11pub const WR_DIS: EfuseField = EfuseField::new(0, 0, 0, 16);
12/// Disable reading from BlOCK1-3
13pub const RD_DIS: EfuseField = EfuseField::new(0, 0, 16, 4);
14/// Flash encryption is enabled if this field has an odd number of bits set
15pub const FLASH_CRYPT_CNT: EfuseField = EfuseField::new(0, 0, 20, 7);
16/// Disable UART download mode. Valid for ESP32 V3 and newer; only
17pub const UART_DOWNLOAD_DIS: EfuseField = EfuseField::new(0, 0, 27, 1);
18/// reserved
19pub const RESERVED_0_28: EfuseField = EfuseField::new(0, 0, 28, 4);
20/// MAC address
21pub const MAC0: EfuseField = EfuseField::new(0, 1, 32, 32);
22/// MAC address
23pub const MAC1: EfuseField = EfuseField::new(0, 2, 64, 16);
24/// CRC8 for MAC address
25pub const MAC_CRC: EfuseField = EfuseField::new(0, 2, 80, 8);
26/// Reserved; it was created by set_missed_fields_in_regs func
27pub const RESERVE_0_88: EfuseField = EfuseField::new(0, 2, 88, 8);
28/// Disables APP CPU
29pub const DISABLE_APP_CPU: EfuseField = EfuseField::new(0, 3, 96, 1);
30/// Disables Bluetooth
31pub const DISABLE_BT: EfuseField = EfuseField::new(0, 3, 97, 1);
32/// Chip package identifier #4bit
33pub const CHIP_PACKAGE_4BIT: EfuseField = EfuseField::new(0, 3, 98, 1);
34/// Disables cache
35pub const DIS_CACHE: EfuseField = EfuseField::new(0, 3, 99, 1);
36/// read for SPI_pad_config_hd
37pub const SPI_PAD_CONFIG_HD: EfuseField = EfuseField::new(0, 3, 100, 5);
38/// Chip package identifier
39pub const CHIP_PACKAGE: EfuseField = EfuseField::new(0, 3, 105, 3);
40/// If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32's max CPU frequency
41/// is rated for 160MHz. 240MHz otherwise
42pub const CHIP_CPU_FREQ_LOW: EfuseField = EfuseField::new(0, 3, 108, 1);
43/// If set; the ESP32's maximum CPU frequency has been rated
44pub const CHIP_CPU_FREQ_RATED: EfuseField = EfuseField::new(0, 3, 109, 1);
45/// BLOCK3 partially served for ADC calibration data
46pub const BLK3_PART_RESERVE: EfuseField = EfuseField::new(0, 3, 110, 1);
47/// bit is set to 1 for rev1 silicon
48pub const CHIP_VER_REV1: EfuseField = EfuseField::new(0, 3, 111, 1);
49/// Reserved; it was created by set_missed_fields_in_regs func
50pub const RESERVE_0_112: EfuseField = EfuseField::new(0, 3, 112, 16);
51/// 8MHz clock freq override
52pub const CLK8M_FREQ: EfuseField = EfuseField::new(0, 4, 128, 8);
53/// True ADC reference voltage
54pub const ADC_VREF: EfuseField = EfuseField::new(0, 4, 136, 5);
55/// Reserved; it was created by set_missed_fields_in_regs func
56pub const RESERVE_0_141: EfuseField = EfuseField::new(0, 4, 141, 1);
57/// read for XPD_SDIO_REG
58pub const XPD_SDIO_REG: EfuseField = EfuseField::new(0, 4, 142, 1);
59/// If XPD_SDIO_FORCE & XPD_SDIO_REG
60pub const XPD_SDIO_TIEH: EfuseField = EfuseField::new(0, 4, 143, 1);
61/// Ignore MTDI pin (GPIO12) for VDD_SDIO on reset
62pub const XPD_SDIO_FORCE: EfuseField = EfuseField::new(0, 4, 144, 1);
63/// Reserved; it was created by set_missed_fields_in_regs func
64pub const RESERVE_0_145: EfuseField = EfuseField::new(0, 4, 145, 15);
65/// Override SD_CLK pad (GPIO6/SPICLK)
66pub const SPI_PAD_CONFIG_CLK: EfuseField = EfuseField::new(0, 5, 160, 5);
67/// Override SD_DATA_0 pad (GPIO7/SPIQ)
68pub const SPI_PAD_CONFIG_Q: EfuseField = EfuseField::new(0, 5, 165, 5);
69/// Override SD_DATA_1 pad (GPIO8/SPID)
70pub const SPI_PAD_CONFIG_D: EfuseField = EfuseField::new(0, 5, 170, 5);
71/// Override SD_CMD pad (GPIO11/SPICS0)
72pub const SPI_PAD_CONFIG_CS0: EfuseField = EfuseField::new(0, 5, 175, 5);
73///
74pub const CHIP_VER_REV2: EfuseField = EfuseField::new(0, 5, 180, 1);
75/// Reserved; it was created by set_missed_fields_in_regs func
76pub const RESERVE_0_181: EfuseField = EfuseField::new(0, 5, 181, 1);
77/// This field stores the voltage level for CPU to run at 240 MHz; or for
78/// flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3:
79/// level 4. (RO)
80pub const VOL_LEVEL_HP_INV: EfuseField = EfuseField::new(0, 5, 182, 2);
81///
82pub const WAFER_VERSION_MINOR: EfuseField = EfuseField::new(0, 5, 184, 2);
83/// Reserved; it was created by set_missed_fields_in_regs func
84pub const RESERVE_0_186: EfuseField = EfuseField::new(0, 5, 186, 2);
85/// Flash encryption config (key tweak bits)
86pub const FLASH_CRYPT_CONFIG: EfuseField = EfuseField::new(0, 5, 188, 4);
87/// Efuse variable block length scheme
88pub const CODING_SCHEME: EfuseField = EfuseField::new(0, 6, 192, 2);
89/// Disable ROM BASIC interpreter fallback
90pub const CONSOLE_DEBUG_DISABLE: EfuseField = EfuseField::new(0, 6, 194, 1);
91///
92pub const DISABLE_SDIO_HOST: EfuseField = EfuseField::new(0, 6, 195, 1);
93/// Secure boot V1 is enabled for bootloader image
94pub const ABS_DONE_0: EfuseField = EfuseField::new(0, 6, 196, 1);
95/// Secure boot V2 is enabled for bootloader image
96pub const ABS_DONE_1: EfuseField = EfuseField::new(0, 6, 197, 1);
97/// Disable JTAG
98pub const JTAG_DISABLE: EfuseField = EfuseField::new(0, 6, 198, 1);
99/// Disable flash encryption in UART bootloader
100pub const DISABLE_DL_ENCRYPT: EfuseField = EfuseField::new(0, 6, 199, 1);
101/// Disable flash decryption in UART bootloader
102pub const DISABLE_DL_DECRYPT: EfuseField = EfuseField::new(0, 6, 200, 1);
103/// Disable flash cache in UART bootloader
104pub const DISABLE_DL_CACHE: EfuseField = EfuseField::new(0, 6, 201, 1);
105/// Usage of efuse block 3 (reserved)
106pub const KEY_STATUS: EfuseField = EfuseField::new(0, 6, 202, 1);
107/// Reserved; it was created by set_missed_fields_in_regs func
108pub const RESERVE_0_203: EfuseField = EfuseField::new(0, 6, 203, 21);
109/// Flash encryption key
110pub const BLOCK1: EfuseField = EfuseField::new(1, 0, 0, 256);
111/// Security boot key
112pub const BLOCK2: EfuseField = EfuseField::new(2, 0, 0, 256);
113/// CRC8 for custom MAC address
114pub const CUSTOM_MAC_CRC: EfuseField = EfuseField::new(3, 0, 0, 8);
115/// Custom MAC address
116pub const CUSTOM_MAC: EfuseField = EfuseField::new(3, 0, 8, 48);
117/// reserved
118pub const RESERVED_3_56: EfuseField = EfuseField::new(3, 1, 56, 8);
119/// read for BLOCK3
120pub const BLK3_RESERVED_2: EfuseField = EfuseField::new(3, 2, 64, 32);
121/// ADC1 Two Point calibration low point. Only valid if
122/// EFUSE_RD_BLK3_PART_RESERVE
123pub const ADC1_TP_LOW: EfuseField = EfuseField::new(3, 3, 96, 7);
124/// ADC1 Two Point calibration high point. Only valid if
125/// EFUSE_RD_BLK3_PART_RESERVE
126pub const ADC1_TP_HIGH: EfuseField = EfuseField::new(3, 3, 103, 9);
127/// ADC2 Two Point calibration low point. Only valid if
128/// EFUSE_RD_BLK3_PART_RESERVE
129pub const ADC2_TP_LOW: EfuseField = EfuseField::new(3, 3, 112, 7);
130/// ADC2 Two Point calibration high point. Only valid if
131/// EFUSE_RD_BLK3_PART_RESERVE
132pub const ADC2_TP_HIGH: EfuseField = EfuseField::new(3, 3, 119, 9);
133/// Secure version for anti-rollback
134pub const SECURE_VERSION: EfuseField = EfuseField::new(3, 4, 128, 32);
135/// reserved
136pub const RESERVED_3_160: EfuseField = EfuseField::new(3, 5, 160, 24);
137/// Version of the MAC field
138pub const MAC_VERSION: EfuseField = EfuseField::new(3, 5, 184, 8);
139/// read for BLOCK3
140pub const BLK3_RESERVED_6: EfuseField = EfuseField::new(3, 6, 192, 32);
141/// read for BLOCK3
142pub const BLK3_RESERVED_7: EfuseField = EfuseField::new(3, 7, 224, 32);
esp_hal/efuse/esp32/fields.rs

esp_hal/efuse/esp32/
fields.rs
