esp_hal/soc/esp32c3/
gpio.rs

1//! # GPIO configuration module (ESP32-C3)
2//!
3//! ## Overview
4//!
5//! The `GPIO` module provides functions and configurations for controlling the
6//! `General Purpose Input/Output` pins on the `ESP32-C3` chip. It allows you to
7//! configure pins as inputs or outputs, set their state and read their state.
8//!
9//! Let's get through the functionality and configurations provided by this GPIO
10//! module:
11//!   - `gpio` block:
12//!       * Defines the pin configurations for various GPIO pins. Each line represents a pin and its
13//!         associated options such as input/output mode, analog capability, and corresponding
14//!         functions.
15//!   - `analog` block:
16//!       * Block defines the analog capabilities of various GPIO pins. Each line represents a pin
17//!         and its associated options such as mux selection, function selection, and input enable.
18//!   - `enum InputSignal`:
19//!       * This enumeration defines input signals for the GPIO mux. Each input signal is assigned a
20//!         specific value.
21//!   - `enum OutputSignal`:
22//!       * This enumeration defines output signals for the GPIO mux. Each output signal is assigned
23//!         a specific value.
24//!
25//! This trait provides functions to read the interrupt status and NMI status
26//! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
27//! `gpio` peripheral to access the appropriate registers.
28
29macro_rules! rtc_pins {
30    ( $( $pin_num:expr )+ ) => {
31        $(
32            paste::paste! {
33                #[cfg_attr(docsrs, doc(cfg(feature = "unstable")))]
34                impl $crate::gpio::RtcPin for $crate::peripherals::[<GPIO $pin_num>]<'_> {
35                    unsafe fn apply_wakeup(&self, wakeup: bool, level: u8) {
36                        let rtc_cntl = $crate::peripherals::LPWR::regs();
37                        let gpio_wakeup = rtc_cntl.gpio_wakeup();
38
39                        unsafe {
40                            gpio_wakeup.modify(|_, w| w.[< gpio_pin $pin_num _wakeup_enable >]().bit(wakeup));
41                            gpio_wakeup.modify(|_, w| w.[< gpio_pin $pin_num _int_type >]().bits(level));
42                        }
43                    }
44
45                    fn rtcio_pad_hold(&self, enable: bool) {
46                        $crate::peripherals::LPWR::regs()
47                            .pad_hold().modify(|_, w| w.[< gpio_pin $pin_num _hold >]().bit(enable));
48                    }
49                }
50
51                #[cfg_attr(docsrs, doc(cfg(feature = "unstable")))]
52                impl crate::gpio::RtcPinWithResistors for $crate::peripherals::[<GPIO $pin_num>]<'_> {
53                    fn rtcio_pullup(&self, enable: bool) {
54                        $crate::peripherals::IO_MUX::regs()
55                            .gpio($pin_num)
56                            .modify(|_, w| w.fun_wpu().bit(enable));
57                    }
58
59                    fn rtcio_pulldown(&self, enable: bool) {
60                        $crate::peripherals::IO_MUX::regs()
61                            .gpio($pin_num)
62                            .modify(|_, w| w.fun_wpd().bit(enable));
63                    }
64                }
65            }
66        )+
67    };
68}
69
70// RTC pins 0 through 5 (inclusive) support GPIO wakeup
71rtc_pins! {
72    0
73    1
74    2
75    3
76    4
77    5
78}
esp_hal/soc/esp32c3/gpio.rs

esp_hal/soc/esp32c3/
gpio.rs
