esp_hal/rtc_cntl/rtc/
esp32s2.rs

1use strum::FromRepr;
2
3use crate::{
4    clock::{RtcClock, RtcFastClock, RtcSlowClock},
5    peripherals::LPWR,
6    rtc_cntl::RtcCalSel,
7};
8
9pub(crate) fn init() {
10    RtcClock::set_fast_freq(RtcFastClock::RcFast);
11    RtcClock::set_slow_freq(RtcSlowClock::RcSlow);
12}
13
14pub(crate) fn configure_clock() {
15    let cal_val = loop {
16        let res = RtcClock::calibrate(RtcCalSel::RtcMux, 1024);
17        if res != 0 {
18            break res;
19        }
20    };
21
22    LPWR::regs().store1().write(|w| unsafe { w.bits(cal_val) });
23}
24
25// Terminology:
26//
27// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
28//               reset vector
29// Core Reset:   Reset the whole digital system except RTC sub-system
30// System Reset: Reset the whole digital system, including RTC sub-system
31// Chip Reset:   Reset the whole chip, including the analog part
32
33/// SOC Reset Reason.
34#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
35pub enum SocResetReason {
36    /// Power on reset
37    ///
38    /// In ESP-IDF this value (0x01) can *also* be `ChipBrownOut` or
39    /// `ChipSuperWdt`, however that is not really compatible with Rust-style
40    /// enums.
41    ChipPowerOn   = 0x01,
42    /// Software resets the digital core by RTC_CNTL_SW_SYS_RST
43    CoreSw        = 0x03,
44    /// Deep sleep reset the digital core
45    CoreDeepSleep = 0x05,
46    /// Main watch dog 0 resets digital core
47    CoreMwdt0     = 0x07,
48    /// Main watch dog 1 resets digital core
49    CoreMwdt1     = 0x08,
50    /// RTC watch dog resets digital core
51    CoreRtcWdt    = 0x09,
52    /// Main watch dog 0 resets CPU 0
53    Cpu0Mwdt0     = 0x0B,
54    /// Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
55    Cpu0Sw        = 0x0C,
56    /// RTC watch dog resets CPU 0
57    Cpu0RtcWdt    = 0x0D,
58    /// VDD voltage is not stable and resets the digital core
59    SysBrownOut   = 0x0F,
60    /// RTC watch dog resets digital core and rtc module
61    SysRtcWdt     = 0x10,
62    /// Main watch dog 1 resets CPU 0
63    Cpu0Mwdt1     = 0x11,
64    /// Super watch dog resets the digital core and rtc module
65    SysSuperWdt   = 0x12,
66    /// Glitch on clock resets the digital core and rtc module
67    SysClkGlitch  = 0x13,
68    /// eFuse CRC error resets the digital core
69    CoreEfuseCrc  = 0x14,
70}
esp_hal/rtc_cntl/rtc/esp32s2.rs

esp_hal/rtc_cntl/rtc/
esp32s2.rs
