esp_hal/rtc_cntl/rtc/
esp32s3.rs

1use strum::FromRepr;
2
3use crate::{
4    clock::{RtcClock, RtcFastClock, RtcSlowClock},
5    peripherals::LPWR,
6    rtc_cntl::RtcCalSel,
7};
8
9pub(crate) fn init() {
10    RtcClock::set_fast_freq(RtcFastClock::RcFast);
11    RtcClock::set_slow_freq(RtcSlowClock::RcSlow);
12}
13
14pub(crate) fn configure_clock() {
15    let cal_val = loop {
16        let res = RtcClock::calibrate(RtcCalSel::RtcMux, 1024);
17        if res != 0 {
18            break res;
19        }
20    };
21
22    LPWR::regs().store1().write(|w| unsafe { w.bits(cal_val) });
23}
24
25// Terminology:
26//
27// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
28//               reset vector
29// Core Reset:   Reset the whole digital system except RTC sub-system
30// System Reset: Reset the whole digital system, including RTC sub-system
31// Chip Reset:   Reset the whole chip, including the analog part
32
33/// SOC Reset Reason.
34#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
35pub enum SocResetReason {
36    /// Power on reset
37    ///
38    /// In ESP-IDF this value (0x01) can *also* be `ChipBrownOut` or
39    /// `ChipSuperWdt`, however that is not really compatible with Rust-style
40    /// enums.
41    ChipPowerOn   = 0x01,
42    /// Software resets the digital core by RTC_CNTL_SW_SYS_RST
43    CoreSw        = 0x03,
44    /// Deep sleep reset the digital core
45    CoreDeepSleep = 0x05,
46    /// Main watch dog 0 resets digital core
47    CoreMwdt0     = 0x07,
48    /// Main watch dog 1 resets digital core
49    CoreMwdt1     = 0x08,
50    /// RTC watch dog resets digital core
51    CoreRtcWdt    = 0x09,
52    /// Main watch dog 0 resets CPU
53    ///
54    /// In ESP-IDF there are `Cpu0Mwdt0` and `Cpu1Mwdt0`, however they have the
55    /// same values.
56    CpuMwdt0      = 0x0B,
57    /// Software resets CPU by RTC_CNTL_SW_(PRO|APP)CPU_RST
58    ///
59    /// In ESP-IDF there are `Cpu0Sw` and `Cpu1Sw`, however they have the same
60    /// values.
61    CpuSw         = 0x0C,
62    /// RTC watch dog resets CPU
63    ///
64    /// In ESP-IDF there are `Cpu0RtcWdt` and `Cpu1RtcWdt`, however they have
65    /// the same values.
66    CpuRtcWdt     = 0x0D,
67    /// VDD voltage is not stable and resets the digital core
68    SysBrownOut   = 0x0F,
69    /// RTC watch dog resets digital core and rtc module
70    SysRtcWdt     = 0x10,
71    /// Main watch dog 1 resets CPU
72    ///
73    /// In ESP-IDF there are `Cpu0Mwdt1` and `Cpu1Mwdt1`, however they have the
74    /// same values.
75    CpuMwdt1      = 0x11,
76    /// Super watch dog resets the digital core and rtc module
77    SysSuperWdt   = 0x12,
78    /// Glitch on clock resets the digital core and rtc module
79    SysClkGlitch  = 0x13,
80    /// eFuse CRC error resets the digital core
81    CoreEfuseCrc  = 0x14,
82    /// USB UART resets the digital core
83    CoreUsbUart   = 0x15,
84    /// USB JTAG resets the digital core
85    CoreUsbJtag   = 0x16,
86    /// Glitch on power resets the digital core
87    CorePwrGlitch = 0x17,
88}
esp_hal/rtc_cntl/rtc/esp32s3.rs

esp_hal/rtc_cntl/rtc/
esp32s3.rs
