esp_hal/rtc_cntl/rtc/
esp32c5.rs

1use strum::FromRepr;
2
3pub(crate) fn init() {}
4
5// Terminology:
6//
7// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
8//               reset vector
9// Core Reset:   Reset the whole digital system except RTC sub-system
10// System Reset: Reset the whole digital system, including RTC sub-system
11// Chip Reset:   Reset the whole chip, including the analog part
12
13/// SOC Reset Reason.
14#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
15pub enum SocResetReason {
16    /// Power on reset
17    ///
18    /// In ESP-IDF this value (0x01) can *also* be `ChipBrownOut` or
19    /// `ChipSuperWdt`, however that is not really compatible with Rust-style
20    /// enums.
21    ChipPowerOn   = 0x01,
22    /// Software resets the digital core by RTC_CNTL_SW_SYS_RST
23    CoreSw        = 0x03,
24    /// Deep sleep reset the digital core
25    CoreDeepSleep = 0x05,
26    /// Main watch dog 0 resets digital core
27    CoreMwdt0     = 0x07,
28    /// Main watch dog 1 resets digital core
29    CoreMwdt1     = 0x08,
30    /// RTC watch dog resets digital core
31    CoreRtcWdt    = 0x09,
32    /// Main watch dog 0 resets CPU 0
33    Cpu0Mwdt0     = 0x0B,
34    /// Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
35    Cpu0Sw        = 0x0C,
36    /// RTC watch dog resets CPU 0
37    Cpu0RtcWdt    = 0x0D,
38    /// VDD voltage is not stable and resets the digital core
39    SysBrownOut   = 0x0F,
40    /// RTC watch dog resets digital core and rtc module
41    SysRtcWdt     = 0x10,
42    /// Main watch dog 1 resets CPU 0
43    Cpu0Mwdt1     = 0x11,
44    /// Super watch dog resets the digital core and rtc module
45    SysSuperWdt   = 0x12,
46    /// eFuse CRC error resets the digital core
47    CoreEfuseCrc  = 0x14,
48    /// USB UART resets the digital core
49    CoreUsbUart   = 0x15,
50    /// USB JTAG resets the digital core
51    CoreUsbJtag   = 0x16,
52    /// JTAG resets CPU
53    Cpu0JtagCpu   = 0x18,
54    /// Power glitch resets CPU
55    PowerGlitch   = 0x19,
56    /// CPU lockup reset
57    CpuLockup     = 0x1A,
58}
esp_hal/rtc_cntl/rtc/esp32c5.rs

esp_hal/rtc_cntl/rtc/
esp32c5.rs
