esp_hal/rtc_cntl/rtc/
esp32.rs

1use strum::FromRepr;
2
3pub(crate) fn init() {}
4
5// Terminology:
6//
7// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
8//               reset vector
9// Core Reset:   Reset the whole digital system except RTC sub-system
10// System Reset: Reset the whole digital system, including RTC sub-system
11// Chip Reset:   Reset the whole chip, including the analog part
12
13#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
14/// SOC Reset Reason.
15pub enum SocResetReason {
16    /// Power on reset
17    ChipPowerOn   = 0x01,
18    /// Software resets the digital core
19    CoreSw        = 0x03,
20    /// Deep sleep reset the digital core
21    CoreDeepSleep = 0x05,
22    /// SDIO module resets the digital core
23    CoreSdio      = 0x06,
24    /// Main watch dog 0 resets digital core
25    CoreMwdt0     = 0x07,
26    /// Main watch dog 1 resets digital core
27    CoreMwdt1     = 0x08,
28    /// RTC watch dog resets digital core
29    CoreRtcWdt    = 0x09,
30    /// Main watch dog 0 resets CPU
31    ///
32    /// In ESP-IDF there are `Cpu0Mwdt1` and `Cpu1Mwdt1`, however they have the
33    /// same values.
34    CpuMwdt0      = 0x0B,
35    /// Software resets CPU
36    ///
37    /// In ESP-IDF there are `Cpu0Sw` and `Cpu1Sw`, however they have the same
38    /// values.
39    Cpu0Sw        = 0x0C,
40    /// RTC watch dog resets CPU
41    ///
42    /// In ESP-IDF there are `Cpu0RtcWdt` and `Cpu1RtcWdt`, however they have
43    /// the same values.
44    Cpu0RtcWdt    = 0x0D,
45    /// CPU0 resets CPU1 by DPORT_APPCPU_RESETTING
46    Cpu1Cpu0      = 0x0E,
47    /// Reset when the VDD voltage is not stable
48    SysBrownOut   = 0x0F,
49    /// RTC watch dog resets digital core and rtc module
50    SysRtcWdt     = 0x10,
51}
esp_hal/rtc_cntl/rtc/esp32.rs

esp_hal/rtc_cntl/rtc/
esp32.rs
