esp_hal/rtc_cntl/rtc/
esp32c2.rs

1use strum::FromRepr;
2
3use crate::{
4    peripherals::{APB_CTRL, EXTMEM, LPWR, SPI0, SPI1, SYSTEM},
5    soc::regi2c,
6};
7
8pub(crate) fn init() {
9    let rtc_cntl = LPWR::regs();
10
11    regi2c::I2C_DIG_REG_XPD_DIG_REG.write_field(0);
12    regi2c::I2C_DIG_REG_XPD_RTC_REG.write_field(0);
13
14    unsafe {
15        rtc_cntl.timer1().modify(|_, w| {
16            w.pll_buf_wait().bits(20u8);
17            w.ck8m_wait().bits(20u8)
18        });
19
20        rtc_cntl.timer5().modify(|_, w| w.min_slp_val().bits(2u8));
21    }
22
23    calibrate_ocode();
24
25    set_rtc_dig_dbias();
26
27    clock_control_init();
28
29    power_control_init();
30
31    unsafe {
32        rtc_cntl.int_ena().write(|w| w.bits(0));
33        rtc_cntl.int_clr().write(|w| w.bits(u32::MAX));
34    }
35
36    regi2c::I2C_ULP_IR_FORCE_XPD_CK.write_field(0);
37}
38
39fn calibrate_ocode() {}
40
41fn set_rtc_dig_dbias() {}
42
43/// Perform clock control related initialization
44fn clock_control_init() {
45    let extmem = EXTMEM::regs();
46    let spi_mem_0 = SPI0::regs();
47    let spi_mem_1 = SPI1::regs();
48
49    // Clear CMMU clock force on
50    extmem
51        .cache_mmu_power_ctrl()
52        .modify(|_, w| w.cache_mmu_mem_force_on().clear_bit());
53
54    // Clear tag clock force on
55    extmem
56        .icache_tag_power_ctrl()
57        .modify(|_, w| w.icache_tag_mem_force_on().clear_bit());
58
59    // Clear register clock force on
60    spi_mem_0.clock_gate().modify(|_, w| w.clk_en().clear_bit());
61    spi_mem_1.clock_gate().modify(|_, w| w.clk_en().clear_bit());
62}
63
64/// Perform power control related initialization
65fn power_control_init() {
66    let rtc_cntl = LPWR::regs();
67    let system = SYSTEM::regs();
68
69    rtc_cntl
70        .clk_conf()
71        .modify(|_, w| w.ck8m_force_pu().clear_bit());
72
73    // Cancel XTAL force PU if no need to force power up
74    // Cannot cancel XTAL force PU if PLL is force power on
75    rtc_cntl
76        .options0()
77        .modify(|_, w| w.xtl_force_pu().clear_bit());
78
79    // Force PD APLL
80    rtc_cntl.ana_conf().modify(|_, w| {
81        w.plla_force_pu().clear_bit();
82        w.plla_force_pd().set_bit();
83        // Open SAR_I2C protect function to avoid SAR_I2C
84        // Reset when rtc_ldo is low.
85        w.i2c_reset_por_force_pd().clear_bit()
86    });
87
88    // Cancel BBPLL force PU if setting no force power up
89    rtc_cntl.options0().modify(|_, w| {
90        w.bbpll_force_pu().clear_bit();
91        w.bbpll_i2c_force_pu().clear_bit();
92        w.bb_i2c_force_pu().clear_bit()
93    });
94
95    rtc_cntl
96        .rtc_cntl()
97        .modify(|_, w| w.regulator_force_pu().clear_bit());
98
99    // If this mask is enabled, all soc memories cannot enter power down mode.
100    // We should control soc memory power down mode from RTC,
101    // so we will not touch this register any more.
102    system
103        .mem_pd_mask()
104        .modify(|_, w| w.lslp_mem_pd_mask().clear_bit());
105
106    rtc_sleep_pu();
107
108    rtc_cntl
109        .dig_pwc()
110        .modify(|_, w| w.dg_wrap_force_pu().clear_bit());
111
112    rtc_cntl
113        .dig_iso()
114        .modify(|_, w| w.dg_wrap_force_noiso().clear_bit());
115
116    // Cancel digital PADS force no iso
117    system
118        .cpu_per_conf()
119        .modify(|_, w| w.cpu_wait_mode_force_on().clear_bit());
120
121    // If SYSTEM_CPU_WAIT_MODE_FORCE_ON == 0,
122    // the CPU clock will be closed when CPU enter WAITI mode.
123    rtc_cntl.dig_iso().modify(|_, w| {
124        w.dg_pad_force_unhold().clear_bit();
125        w.dg_pad_force_noiso().clear_bit()
126    });
127}
128
129/// Configure whether certain peripherals are powered down in deep sleep
130fn rtc_sleep_pu() {
131    LPWR::regs()
132        .dig_pwc()
133        .modify(|_, w| w.lslp_mem_force_pu().clear_bit());
134
135    APB_CTRL::regs().front_end_mem_pd().modify(|_, w| {
136        w.dc_mem_force_pu().clear_bit();
137        w.pbus_mem_force_pu().clear_bit();
138        w.agc_mem_force_pu().clear_bit()
139    });
140    APB_CTRL::regs().mem_power_up().modify(|_, w| unsafe {
141        w.sram_power_up().bits(0u8);
142        w.rom_power_up().bits(0u8)
143    });
144}
145
146// Terminology:
147//
148// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
149//               reset vector
150// Core Reset:   Reset the whole digital system except RTC sub-system
151// System Reset: Reset the whole digital system, including RTC sub-system
152// Chip Reset:   Reset the whole chip, including the analog part
153
154#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
155/// SOC Reset Reason.
156pub enum SocResetReason {
157    /// Power on reset
158    ChipPowerOn   = 0x01,
159    /// Software resets the digital core by RTC_CNTL_SW_SYS_RST
160    CoreSw        = 0x03,
161    /// Deep sleep reset the digital core
162    CoreDeepSleep = 0x05,
163    /// Main watch dog 0 resets digital core
164    CoreMwdt0     = 0x07,
165    /// RTC watch dog resets digital core
166    CoreRtcWdt    = 0x09,
167    /// Main watch dog 0 resets CPU 0
168    Cpu0Mwdt0     = 0x0B,
169    /// Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
170    Cpu0Sw        = 0x0C,
171    /// RTC watch dog resets CPU 0
172    Cpu0RtcWdt    = 0x0D,
173    /// VDD voltage is not stable and resets the digital core
174    SysBrownOut   = 0x0F,
175    /// RTC watch dog resets digital core and rtc module
176    SysRtcWdt     = 0x10,
177    /// Super watch dog resets the digital core and rtc module
178    SysSuperWdt   = 0x12,
179    /// Glitch on clock resets the digital core and rtc module
180    SysClkGlitch  = 0x13,
181    /// eFuse CRC error resets the digital core
182    CoreEfuseCrc  = 0x14,
183    /// JTAG resets the CPU 0
184    Cpu0Jtag      = 0x18,
185}
esp_hal/rtc_cntl/rtc/esp32c2.rs

esp_hal/rtc_cntl/rtc/
esp32c2.rs
