esp_hal/rtc_cntl/rtc/
esp32c61.rs

1use strum::FromRepr;
2
3pub(crate) fn init() {}
4
5// Terminology:
6//
7// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
8//               reset vector
9// Core Reset:   Reset the whole digital system except RTC sub-system
10// System Reset: Reset the whole digital system, including RTC sub-system
11// Chip Reset:   Reset the whole chip, including the analog part
12
13/// SOC Reset Reason (ESP32-C61).
14///
15/// Parsed from ESP-IDF `soc_reset_reason_t` in `reset_reasons.h`.
16#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
17pub enum SocResetReason {
18    /// Power on reset
19    ///
20    /// In ESP-IDF this value (0x01) can *also* be `ChipBrownOut` (VDD voltage
21    /// not stable, resets the chip); that is not distinguishable in a Rust enum.
22    ChipPowerOn   = 0x01,
23    /// Software resets the digital core (hp system) by LP_AON_HPSYS_SW_RESET
24    CoreSw        = 0x03,
25    /// Deep sleep reset the digital core (hp system)
26    CoreDeepSleep = 0x05,
27    /// Main watch dog 0 resets digital core (hp system)
28    CoreMwdt0     = 0x07,
29    /// Main watch dog 1 resets digital core (hp system)
30    CoreMwdt1     = 0x08,
31    /// RTC watch dog resets digital core (hp system)
32    CoreRtcWdt    = 0x09,
33    /// Main watch dog 0 resets CPU 0
34    Cpu0Mwdt0     = 0x0B,
35    /// Software resets CPU 0 by LP_AON_CPU_CORE0_SW_RESET
36    Cpu0Sw        = 0x0C,
37    /// RTC watch dog resets CPU 0
38    Cpu0RtcWdt    = 0x0D,
39    /// VDD voltage is not stable and resets the digital core
40    SysBrownOut   = 0x0F,
41    /// RTC watch dog resets digital core and rtc module
42    SysRtcWdt     = 0x10,
43    /// Main watch dog 1 resets CPU 0
44    Cpu0Mwdt1     = 0x11,
45    /// Super watch dog resets the digital core and rtc module
46    SysSuperWdt   = 0x12,
47    /// eFuse CRC error resets the digital core (hp system)
48    CoreEfuseCrc  = 0x14,
49    /// USB UART resets the digital core (hp system)
50    CoreUsbUart   = 0x15,
51    /// USB JTAG resets the digital core (hp system)
52    CoreUsbJtag   = 0x16,
53    /// JTAG resets CPU 0
54    Cpu0Jtag      = 0x18,
55    /// RTC power glitch resets system
56    RtcBrownOut   = 0x19,
57    /// CPU lockup resets
58    CpuLockup     = 0x1A,
59}
esp_hal/rtc_cntl/rtc/esp32c61.rs

esp_hal/rtc_cntl/rtc/
esp32c61.rs
