esp_hal/rtc_cntl/rtc/
esp32h2.rs

1use strum::FromRepr;
2
3use crate::{
4    peripherals::{PCR, PMU},
5    soc::regi2c,
6};
7
8pub(crate) fn init() {
9    // * No peripheral reg i2c power up required on the target */
10    regi2c::I2C_PMU_EN_I2C_RTC_DREG.write_field(0);
11    regi2c::I2C_PMU_EN_I2C_DIG_DREG.write_field(0);
12    regi2c::I2C_PMU_EN_I2C_RTC_DREG_SLP.write_field(0);
13    regi2c::I2C_PMU_EN_I2C_DIG_DREG_SLP.write_field(0);
14    regi2c::I2C_PMU_OR_XPD_RTC_REG.write_field(0);
15    regi2c::I2C_PMU_OR_XPD_DIG_REG.write_field(0);
16    regi2c::I2C_PMU_OR_XPD_TRX.write_field(0);
17    regi2c::I2C_BIAS_DREG_0P8.write_field(8);
18
19    let pmu = PMU::regs();
20    unsafe {
21        pmu.power_pd_top_cntl().write(|w| w.bits(0));
22        pmu.power_pd_hpaon_cntl().write(|w| w.bits(0));
23        pmu.power_pd_hpcpu_cntl().write(|w| w.bits(0));
24        pmu.power_pd_hpperi_reserve().write(|w| w.bits(0));
25        pmu.power_pd_hpwifi_cntl().write(|w| w.bits(0));
26        pmu.power_pd_lpperi_cntl().write(|w| w.bits(0));
27
28        pmu.hp_active_hp_regulator0()
29            .modify(|_, w| w.hp_active_hp_regulator_dbias().bits(25));
30        pmu.hp_sleep_lp_regulator0()
31            .modify(|_, w| w.hp_sleep_lp_regulator_dbias().bits(26));
32
33        pmu.hp_sleep_dig_power().modify(|_, w| {
34            w.hp_sleep_vdd_spi_pd_en()
35                .set_bit()
36                .hp_sleep_pd_hp_wifi_pd_en()
37                .set_bit()
38                .hp_sleep_pd_hp_cpu_pd_en()
39                .set_bit()
40                .hp_sleep_pd_top_pd_en()
41                .set_bit()
42        });
43
44        pmu.hp_active_hp_ck_power().modify(|_, w| {
45            w.hp_active_xpd_bbpll()
46                .set_bit()
47                .hp_active_xpd_bb_i2c()
48                .set_bit()
49                .hp_active_xpd_bbpll_i2c()
50                .set_bit()
51        });
52
53        pmu.hp_active_sysclk().modify(|_, w| {
54            w.hp_active_icg_sys_clock_en()
55                .set_bit()
56                .hp_active_sys_clk_slp_sel()
57                .clear_bit()
58                .hp_active_icg_slp_sel()
59                .clear_bit()
60        });
61        pmu.hp_sleep_sysclk().modify(|_, w| {
62            w.hp_sleep_icg_sys_clock_en()
63                .clear_bit()
64                .hp_sleep_sys_clk_slp_sel()
65                .set_bit()
66                .hp_sleep_icg_slp_sel()
67                .set_bit()
68        });
69
70        pmu.slp_wakeup_cntl5()
71            .modify(|_, w| w.lp_ana_wait_target().bits(15));
72        pmu.slp_wakeup_cntl7()
73            .modify(|_, w| w.ana_wait_target().bits(1700));
74    }
75
76    PCR::regs()
77        .ctrl_tick_conf()
78        .modify(|_, w| unsafe { w.fosc_tick_num().bits(255) });
79}
80
81// Terminology:
82//
83// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
84//               reset vector
85// Core Reset:   Reset the whole digital system except RTC sub-system
86// System Reset: Reset the whole digital system, including RTC sub-system
87// Chip Reset:   Reset the whole chip, including the analog part
88
89/// SOC Reset Reason.
90#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
91pub enum SocResetReason {
92    /// Power on reset
93    ///
94    /// In ESP-IDF this value (0x01) can *also* be `ChipBrownOut` or
95    /// `ChipSuperWdt`, however that is not really compatible with Rust-style
96    /// enums.
97    ChipPowerOn   = 0x01,
98    /// Software resets the digital core by RTC_CNTL_SW_SYS_RST
99    CoreSw        = 0x03,
100    /// Deep sleep reset the digital core
101    CoreDeepSleep = 0x05,
102    /// Main watch dog 0 resets digital core
103    CoreMwdt0     = 0x07,
104    /// Main watch dog 1 resets digital core
105    CoreMwdt1     = 0x08,
106    /// RTC watch dog resets digital core
107    CoreRtcWdt    = 0x09,
108    /// Main watch dog 0 resets CPU 0
109    Cpu0Mwdt0     = 0x0B,
110    /// Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
111    Cpu0Sw        = 0x0C,
112    /// RTC watch dog resets CPU 0
113    Cpu0RtcWdt    = 0x0D,
114    /// VDD voltage is not stable and resets the digital core
115    SysBrownOut   = 0x0F,
116    /// RTC watch dog resets digital core and rtc module
117    SysRtcWdt     = 0x10,
118    /// Main watch dog 1 resets CPU 0
119    Cpu0Mwdt1     = 0x11,
120    /// Super watch dog resets the digital core and rtc module
121    SysSuperWdt   = 0x12,
122    /// Glitch on clock resets the digital core and rtc module
123    SysClkGlitch  = 0x13,
124    /// eFuse CRC error resets the digital core
125    CoreEfuseCrc  = 0x14,
126    /// USB UART resets the digital core
127    CoreUsbUart   = 0x15,
128    /// USB JTAG resets the digital core
129    CoreUsbJtag   = 0x16,
130    /// Glitch on power resets the digital core
131    CorePwrGlitch = 0x17,
132}
133
134bitfield::bitfield! {
135    /// Representation of `PMU_HP_{ACTIVE,SLEEP}_DIG_POWER_REG` registers.
136    #[derive(Clone, Copy, Default)]
137    pub struct HpDigPower(u32);
138
139    pub bool, vdd_spi_pd_en, set_vdd_spi_pd_en: 21;
140    pub bool, mem_dslp     , set_mem_dslp     : 22;
141    pub bool, modem_pd_en  , set_modem_pd_en  : 27;
142    pub bool, cpu_pd_en    , set_cpu_pd_en    : 29;
143    pub bool, top_pd_en    , set_top_pd_en    : 31;
144}
145
146bitfield::bitfield! {
147    /// Representation of `PMU_HP_{ACTIVE,SLEEP}_HP_CK_POWER_REG` registers.
148    #[derive(Clone, Copy, Default)]
149    pub struct HpClkPower(u32);
150
151    pub bool, xpd_bbpll    , set_xpd_bbpll    : 30;
152}
153
154bitfield::bitfield! {
155    /// Representation of `PMU_{HP_ACTIVE,HP_SLEEP,LP_SLEEP}_XTAL_REG` register.
156    #[derive(Clone, Copy, Default)]
157    pub struct XtalPower(u32);
158
159    pub bool, xpd_xtal     , set_xpd_xtal     : 31;
160}
161
162/// Combined HP system power settings.
163#[derive(Clone, Copy, Default)]
164pub struct HpSysPower {
165    pub dig_power: HpDigPower,
166    pub clk: HpClkPower,
167    pub xtal: XtalPower,
168}
169
170bitfield::bitfield! {
171    /// Representation of `PMU_{HP,LP}_SLEEP_LP_DIG_POWER_REG`.
172    #[derive(Clone, Copy, Default)]
173    pub struct LpDigPower(u32);
174
175    pub bool, bod_source_sel, set_bod_source_sel : 27;
176    pub u32, vddbat_mode, set_vddbat_mode : 29, 28;
177    pub u32, mem_dslp  , set_mem_dslp  : 30;
178
179}
180
181bitfield::bitfield! {
182    /// Representation of `PMU_{HP,LP}_SLEEP_LP_CK_POWER_REG`.
183    #[derive(Clone, Copy, Default)]
184    pub struct LpClkPower(u32);
185
186    pub u32, xpd_xtal32k, set_xpd_xtal32k: 28;
187    pub u32, xpd_fosc   , set_xpd_fosc   : 30;
188}
189
190/// Combined LP system power settings.
191#[derive(Clone, Copy, Default)]
192pub struct LpSysPower {
193    pub dig_power: LpDigPower,
194    pub clk_power: LpClkPower,
195    pub xtal: XtalPower,
196}
197
198bitfield::bitfield! {
199    /// Representation of `PMU_HP_{ACTIVE,SLEEP}_HP_SYS_CNTL_REG` register.
200    #[derive(Clone, Copy, Default)]
201    pub struct HpSysCntlReg(u32);
202
203    pub bool, uart_wakeup_en , set_uart_wakeup_en : 24;
204    pub bool, lp_pad_hold_all, set_lp_pad_hold_all: 25;
205    pub bool, hp_pad_hold_all, set_hp_pad_hold_all: 26;
206    pub bool, dig_pad_slp_sel, set_dig_pad_slp_sel: 27;
207    pub bool, dig_pause_wdt  , set_dig_pause_wdt  : 28;
208    pub bool, dig_cpu_stall  , set_dig_cpu_stall  : 29;
209}
esp_hal/rtc_cntl/rtc/esp32h2.rs

esp_hal/rtc_cntl/rtc/
esp32h2.rs
