esp_hal/rtc_cntl/rtc/
esp32s3.rs

1use strum::FromRepr;
2
3pub(crate) fn init() {}
4
5// Terminology:
6//
7// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
8//               reset vector
9// Core Reset:   Reset the whole digital system except RTC sub-system
10// System Reset: Reset the whole digital system, including RTC sub-system
11// Chip Reset:   Reset the whole chip, including the analog part
12
13/// SOC Reset Reason.
14#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
15pub enum SocResetReason {
16    /// Power on reset
17    ///
18    /// In ESP-IDF this value (0x01) can *also* be `ChipBrownOut` or
19    /// `ChipSuperWdt`, however that is not really compatible with Rust-style
20    /// enums.
21    ChipPowerOn   = 0x01,
22    /// Software resets the digital core by RTC_CNTL_SW_SYS_RST
23    CoreSw        = 0x03,
24    /// Deep sleep reset the digital core
25    CoreDeepSleep = 0x05,
26    /// Main watch dog 0 resets digital core
27    CoreMwdt0     = 0x07,
28    /// Main watch dog 1 resets digital core
29    CoreMwdt1     = 0x08,
30    /// RTC watch dog resets digital core
31    CoreRtcWdt    = 0x09,
32    /// Main watch dog 0 resets CPU
33    ///
34    /// In ESP-IDF there are `Cpu0Mwdt0` and `Cpu1Mwdt0`, however they have the
35    /// same values.
36    CpuMwdt0      = 0x0B,
37    /// Software resets CPU by RTC_CNTL_SW_(PRO|APP)CPU_RST
38    ///
39    /// In ESP-IDF there are `Cpu0Sw` and `Cpu1Sw`, however they have the same
40    /// values.
41    CpuSw         = 0x0C,
42    /// RTC watch dog resets CPU
43    ///
44    /// In ESP-IDF there are `Cpu0RtcWdt` and `Cpu1RtcWdt`, however they have
45    /// the same values.
46    CpuRtcWdt     = 0x0D,
47    /// VDD voltage is not stable and resets the digital core
48    SysBrownOut   = 0x0F,
49    /// RTC watch dog resets digital core and rtc module
50    SysRtcWdt     = 0x10,
51    /// Main watch dog 1 resets CPU
52    ///
53    /// In ESP-IDF there are `Cpu0Mwdt1` and `Cpu1Mwdt1`, however they have the
54    /// same values.
55    CpuMwdt1      = 0x11,
56    /// Super watch dog resets the digital core and rtc module
57    SysSuperWdt   = 0x12,
58    /// Glitch on clock resets the digital core and rtc module
59    SysClkGlitch  = 0x13,
60    /// eFuse CRC error resets the digital core
61    CoreEfuseCrc  = 0x14,
62    /// USB UART resets the digital core
63    CoreUsbUart   = 0x15,
64    /// USB JTAG resets the digital core
65    CoreUsbJtag   = 0x16,
66    /// Glitch on power resets the digital core
67    CorePwrGlitch = 0x17,
68}
esp_hal/rtc_cntl/rtc/esp32s3.rs

esp_hal/rtc_cntl/rtc/
esp32s3.rs
