Module dma 

Available on crate feature unstable only.

Direct Memory Access (DMA)

Overview

The DMA driver provides an interface to efficiently transfer data between different memory regions and peripherals within the ESP microcontroller without involving the CPU. The DMA controller is responsible for managing these data transfers.

Notice, that this module is a common version of the DMA driver, ESP32 and ESP32-S2 are using older PDMA controller, whenever other chips are using newer GDMA controller.

Examples

Initialize and utilize DMA controller in SPI

let sclk = peripherals.GPIO0;
let miso = peripherals.GPIO2;
let mosi = peripherals.GPIO4;
let cs = peripherals.GPIO5;

let mut spi = Spi::new(
    peripherals.SPI2,
    Config::default()
        .with_frequency(Rate::from_khz(100))
        .with_mode(Mode::_0),
)?
.with_sck(sclk)
.with_mosi(mosi)
.with_miso(miso)
.with_cs(cs)
.with_dma(peripherals.DMA_SPI2);

⚠️ Note: Descriptors should be sized as (max_transfer_size + CHUNK_SIZE - 1) / CHUNK_SIZE. I.e., to transfer buffers of size 1..=CHUNK_SIZE, you need 1 descriptor.

⚠️ Note: For chips that support DMA to/from PSRAM DMA transfers to/from PSRAM have extra alignment requirements. The address and size of the buffer pointed to by each descriptor must be a multiple of the cache line (block) size.

For convenience you can use the crate::dma_buffers macro.

Modules

aligned

Helper types for DMA buffers.

Structs

BufView

An in-progress view into DmaRxBuf/DmaTxBuf.

Channel

DMA Channel

DmaDescriptor

A DMA transfer descriptor.

DmaDescriptorFlags

DMA descriptor flags.

DmaLoopBuf

DMA Loop Buffer

DmaRxBuf

DMA receive buffer

DmaRxStreamBuf

DMA Streaming Receive Buffer.

DmaRxStreamBufView

A view into a DmaRxStreamBuf

DmaRxTxBuf

DMA transmit and receive buffer.

DmaTxBuf

DMA transmit buffer

DmaTxStreamBuf

DMA Streaming Transmit Buffer.

DmaTxStreamBufView

A view into a DmaTxStreamBuf

EmptyBuf

An empty buffer that can be used when you don’t need to transfer any data.

I2sDmaChannel

An I2S-compatible type-erased DMA channel.

I2sDmaRxChannel

The RX half of an arbitrary I2S DMA channel.

I2sDmaTxChannel

The TX half of an arbitrary I2S DMA channel.

Preparation

Holds all the information needed to configure a DMA channel for a transfer.

SpiDmaChannel

An SPI-compatible type-erased DMA channel.

SpiDmaRxChannel

The RX half of an arbitrary SPI DMA channel.

SpiDmaTxChannel

The TX half of an arbitrary SPI DMA channel.

Enums

BurstConfig

Burst transfer configuration.

DmaAlignmentError

DMA buffer alignment errors.

DmaBufError

Error returned from Dma[Rx|Tx|RxTx]Buf operations.

DmaError

DMA Errors

DmaInterrupt

Kinds of interrupt to listen to.

DmaRxInterrupt

Types of interrupts emitted by the RX channel.

DmaTxInterrupt

Types of interrupts emitted by the TX channel.

Owner

The owner bit of a DMA descriptor.

TransferDirection

The direction of the DMA transfer.

Constants

CHUNK_SIZE

The default chunk size used for DMA transfers.

Traits

DmaChannel

A description of a DMA Channel.

DmaEligiblePeripheral

Implemented by peripheral singletons that can be used with a DMA engine.

DmaRxBuffer

DmaRxBuffer is a DMA descriptor + memory combo that can be used for receiving data from a peripheral’s FIFO to a DMA channel.

DmaRxChannel

Stability

DmaTxBuffer

DmaTxBuffer is a DMA descriptor + memory combo that can be used for transmitting data from a DMA channel to a peripheral’s FIFO.

DmaTxChannel

Stability

Functions

descriptor_count

Computes the number of descriptors required for a given buffer size with a given chunk size.