Module sleep 

RTC Control Sleep Module

Overview

The sleep module allows configuring various wakeup sources and setting up the sleep behavior based on those sources. The supported wakeup sources include:

• GPIO pins - light sleep only
• timers
• SDIO (Secure Digital Input/Output) - light sleep only
• MAC (Media Access Control) wake - light sleep only
• UART0 - light sleep only
• UART1 - light sleep only
• touch
• ULP (Ultra-Low Power) wake
• BT (Bluetooth) wake - light sleep only

Structs

LowPowerunstable

Low-power management.

RtcSleepConfigunstable

Configuration for the RTC sleep behavior.

Constants

DG_WRAP_POWERUP_CYCLESunstable

Power-up cycles for the digital wrap components.

DG_WRAP_WAIT_CYCLESunstable

Wait cycles for the digital wrap components.

ROM_RAM_POWERUP_CYCLESunstable

Power-up cycles for ROM and RAM.

ROM_RAM_WAIT_CYCLESunstable

Wait cycles for ROM and RAM.

RTC_CK8M_ENABLE_WAIT_DEFAULTunstable

Default wait cycles to enable the 8MHz clock.

RTC_CNTL_CK8M_WAIT_DEFAULTunstable

Default wait cycles for the 8MHz clock.

RTC_CNTL_CK8M_WAIT_SLP_CYCLESunstable

Cycles to wait for the 8MHz clock to stabilize.

RTC_CNTL_DBG_ATTEN_DEFAULTunstable

Default debug attenuation value.

RTC_CNTL_DBIAS_0V90unstable

RTC digital bias setting corresponding to 0.90V.

RTC_CNTL_DBIAS_0V95unstable

RTC digital bias setting corresponding to 0.95V.

RTC_CNTL_DBIAS_1V00unstable

RTC digital bias setting corresponding to 1.00V.

RTC_CNTL_DBIAS_1V05unstable

RTC digital bias setting corresponding to 1.05V.

RTC_CNTL_DBIAS_1V10unstable

RTC digital bias setting corresponding to 1.10V.

RTC_CNTL_DBIAS_1V15unstable

RTC digital bias setting corresponding to 1.15V.

RTC_CNTL_DBIAS_1V20unstable

RTC digital bias setting corresponding to 1.20V.

RTC_CNTL_DBIAS_1V25unstable

RTC digital bias setting corresponding to 1.25V.

RTC_CNTL_MIN_SLP_VAL_MINunstable

Minimum sleep value (in cycles).

RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLESunstable

Power-up cycles for other blocks.

RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLESunstable

Wait cycles for other blocks.

RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLESunstable

Cycles to wait for PLL buffer stabilization.

RTC_CNTL_WAKEUP_DELAY_CYCLESunstable

Delay in cycles for wakeup signal to be applied.

RTC_CNTL_XTL_BUF_WAIT_SLP_USunstable

Time (in microseconds) for waiting the XTL buffer to stabilize during sleep.

RTC_MEM_POWERUP_CYCLESunstable

Power-up cycles for RTC memory.

RTC_MEM_WAIT_CYCLESunstable

Wait cycles for RTC memory.

RTC_POWERUP_CYCLESunstable

Power-up cycles for RTC components.

RTC_WAIT_CYCLESunstable

Wait cycles for RTC components.

WIFI_POWERUP_CYCLESunstable

Power-up cycles for Wi-Fi.

WIFI_WAIT_CYCLESunstable

Wait cycles for Wi-Fi.