esp_hal/rtc_cntl/rtc/
esp32.rs

1use strum::FromRepr;
2
3use crate::soc::clocks::ClockConfig;
4
5pub(crate) fn init(_config: &ClockConfig) {}
6
7// Terminology:
8//
9// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
10//               reset vector
11// Core Reset:   Reset the whole digital system except RTC sub-system
12// System Reset: Reset the whole digital system, including RTC sub-system
13// Chip Reset:   Reset the whole chip, including the analog part
14
15#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
16/// SOC Reset Reason.
17pub enum SocResetReason {
18    /// Power on reset
19    ChipPowerOn   = 0x01,
20    /// Software resets the digital core
21    CoreSw        = 0x03,
22    /// Deep sleep reset the digital core
23    CoreDeepSleep = 0x05,
24    /// SDIO module resets the digital core
25    CoreSdio      = 0x06,
26    /// Main watch dog 0 resets digital core
27    CoreMwdt0     = 0x07,
28    /// Main watch dog 1 resets digital core
29    CoreMwdt1     = 0x08,
30    /// RTC watch dog resets digital core
31    CoreRtcWdt    = 0x09,
32    /// Main watch dog 0 resets CPU
33    ///
34    /// In ESP-IDF there are `Cpu0Mwdt1` and `Cpu1Mwdt1`, however they have the
35    /// same values.
36    CpuMwdt0      = 0x0B,
37    /// Software resets CPU
38    ///
39    /// In ESP-IDF there are `Cpu0Sw` and `Cpu1Sw`, however they have the same
40    /// values.
41    Cpu0Sw        = 0x0C,
42    /// RTC watch dog resets CPU
43    ///
44    /// In ESP-IDF there are `Cpu0RtcWdt` and `Cpu1RtcWdt`, however they have
45    /// the same values.
46    Cpu0RtcWdt    = 0x0D,
47    /// CPU0 resets CPU1 by DPORT_APPCPU_RESETTING
48    Cpu1Cpu0      = 0x0E,
49    /// Reset when the VDD voltage is not stable
50    SysBrownOut   = 0x0F,
51    /// RTC watch dog resets digital core and rtc module
52    SysRtcWdt     = 0x10,
53}
esp_hal/rtc_cntl/rtc/esp32.rs

esp_hal/rtc_cntl/rtc/
esp32.rs
