esp_hal/gpio/lp_io/low_level/
v4.rs

1use crate::{
2    gpio::{LpPin, lp_io::LpFunction},
3    peripherals::LP_AON,
4};
5
6cfg_select! {
7    esp32c6 => {
8        use crate::peripherals::{LP_IO as LP_GPIO, LP_IO as LP_IO_MUX};
9    }
10    any(esp32c5, esp32c61) => {
11        // Only a low-power peripheral or a low-power core reads and drives the pads.
12        #[cfg(any(
13            ulp_riscv_driver_supported,
14            lp_io_has_gpio_matrix,
15            lp_i2c_master_driver_supported,
16        ))]
17        use crate::peripherals::LP_GPIO;
18        use crate::peripherals::LP_IO_MUX;
19    }
20}
21
22for_each_lp_function! {
23    (($_lp:ident, LP_GPIOn, $pin:literal), $gpio:ident, $_af:ident, $_lp_in:tt $_lp_out:tt) => {
24        #[cfg_attr(docsrs, doc(cfg(feature = "unstable")))]
25        impl LpPin for crate::peripherals::$gpio<'_> {
26            fn lp_number(&self) -> u8 {
27                $pin
28            }
29        }
30    };
31}
32
33// The low-power number of a pad is its digital number on these chips, and one register holds every
34// pad, so both paths write the same bit.
35pub(crate) fn pad_hold(lp: u8, enable: bool) {
36    digital_pad_hold(lp, enable);
37}
38
39/// Returns whether something holds the pad.
40pub(crate) fn is_pad_held(lp: u8) -> bool {
41    is_digital_pad_held(lp)
42}
43
44/// Takes or releases the hold of the pad of `gpio`.
45pub(crate) fn digital_pad_hold(gpio: u8, enable: bool) {
46    let mask = 1 << gpio;
47    LP_AON::regs().gpio_hold0().modify(|r, w| unsafe {
48        let bits = r.gpio_hold0().bits();
49        w.gpio_hold0()
50            .bits(if enable { bits | mask } else { bits & !mask })
51    });
52}
53
54/// Returns whether something holds the pad of `gpio`.
55pub(crate) fn is_digital_pad_held(gpio: u8) -> bool {
56    LP_AON::regs().gpio_hold0().read().gpio_hold0().bits() & (1 << gpio) != 0
57}
58
59pub(crate) fn set_config(lp: u8, input_enable: bool, mux: bool, func: LpFunction) {
60    let mask = 1 << lp;
61    LP_AON::regs().gpio_mux().modify(|r, w| unsafe {
62        let bits = r.sel().bits();
63        w.sel().bits(if mux { bits | mask } else { bits & !mask })
64    });
65
66    LP_IO_MUX::regs().gpio(lp as usize).modify(|_, w| unsafe {
67        w.slp_sel().bit(false);
68        w.fun_ie().bit(input_enable);
69        w.mcu_sel().bits(func as u8)
70    });
71}
72
73#[cfg(any(ulp_riscv_driver_supported, lp_io_has_gpio_matrix))]
74pub(crate) fn init_pin(lp: u8, input_enable: bool) -> u8 {
75    set_config(lp, input_enable, true, LpFunction::LP_GPIO);
76    lp
77}
78
79#[cfg(any(
80    ulp_riscv_driver_supported,
81    lp_io_has_gpio_matrix,
82    lp_i2c_master_driver_supported,
83))]
84pub(crate) fn output_enable(lp: u8, enable: bool) {
85    if enable {
86        LP_GPIO::regs()
87            .out_enable_w1ts()
88            .write(|w| unsafe { w.enable_w1ts().bits(1 << lp) });
89    } else {
90        LP_GPIO::regs()
91            .out_enable_w1tc()
92            .write(|w| unsafe { w.enable_w1tc().bits(1 << lp) });
93    }
94}
95
96#[cfg(any(ulp_riscv_driver_supported, lp_io_has_gpio_matrix))]
97pub(crate) fn input_enable(lp: u8, enable: bool) {
98    LP_IO_MUX::regs()
99        .gpio(lp as usize)
100        .modify(|_, w| w.fun_ie().bit(enable));
101}
102
103pub(crate) fn pullup_enable(lp: u8, enable: bool) {
104    LP_IO_MUX::regs()
105        .gpio(lp as usize)
106        .modify(|_, w| w.fun_wpu().bit(enable));
107}
108
109pub(crate) fn pulldown_enable(lp: u8, enable: bool) {
110    LP_IO_MUX::regs()
111        .gpio(lp as usize)
112        .modify(|_, w| w.fun_wpd().bit(enable));
113}
114
115// On these chips, the pad driver bit is part of the low-power GPIO peripheral, so this function
116// takes the low-power number, like the functions beside it.
117#[cfg(any(
118    ulp_riscv_driver_supported,
119    lp_io_has_gpio_matrix,
120    lp_i2c_master_driver_supported,
121))]
122pub(crate) fn set_open_drain_output(lp: u8, enable: bool) {
123    LP_GPIO::regs()
124        .pin(lp as usize)
125        .modify(|_, w| w.pad_driver().bit(enable));
126}
127
128#[cfg(lp_i2c_master_driver_supported)]
129pub(crate) fn reset_pin(lp: u8) {
130    output_enable(lp, false);
131    set_open_drain_output(lp, false);
132
133    // Resistors, input enable and the pad's LP function all live in this register.
134    LP_IO_MUX::regs().gpio(lp as usize).reset();
135
136    // Hand the pad back to the digital IO MUX.
137    LP_AON::regs()
138        .gpio_mux()
139        .modify(|r, w| unsafe { w.sel().bits(r.sel().bits() & !(1 << lp)) });
140}
esp_hal/gpio/lp_io/low_level/v4.rs

esp_hal/gpio/lp_io/low_level/
v4.rs
