esp_hal/spi/
mod.rs

1//! Serial Peripheral Interface (SPI)
2//!
3//! ## Overview
4//! The Serial Peripheral Interface (SPI) is a synchronous serial interface
5//! useful for communication with external peripherals.
6//!
7//! ## Configuration
8//! This peripheral is capable of operating in either master or slave mode. For
9//! more information on these modes, please refer to the documentation in their
10//! respective modules.
11
12#[cfg(any(spi_master_supports_dma, spi_slave_supports_dma))]
13use crate::dma::DmaError;
14
15#[cfg(spi_master_driver_supported)]
16pub mod master;
17
18crate::unstable_module! {
19    #[cfg(spi_slave_driver_supported)]
20    pub mod slave;
21}
22
23#[cfg_attr(
24    any(spi_master_version = "1", spi_master_version = "2"),
25    path = "clocks/v1v2.rs"
26)]
27#[cfg_attr(
28    all(spi_master_version = "3", not(any(esp32p4, esp32s31, soc_has_pcr))),
29    path = "clocks/v3.rs"
30)]
31#[cfg_attr(esp32p4, path = "clocks/esp32p4.rs")]
32#[cfg_attr(esp32s31, path = "clocks/esp32s31.rs")]
33#[cfg_attr(soc_has_pcr, path = "clocks/v3_pcr.rs")]
34mod clocks;
35
36/// SPI errors
37#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
38#[cfg_attr(feature = "defmt", derive(defmt::Format))]
39#[non_exhaustive]
40pub enum Error {
41    /// Error occurred due to a DMA-related issue.
42    #[cfg(feature = "unstable")]
43    #[cfg_attr(docsrs, doc(cfg(feature = "unstable")))]
44    #[allow(clippy::enum_variant_names, reason = "DMA is unstable")]
45    #[cfg(any(spi_master_supports_dma, spi_slave_supports_dma))]
46    DmaError(DmaError),
47    /// Error indicating that the maximum DMA transfer size was exceeded.
48    MaxDmaTransferSizeExceeded,
49    /// Error indicating that the FIFO size was exceeded during SPI
50    /// communication.
51    FifoSizeExeeded,
52    /// Error indicating that the operation is unsupported by the current
53    /// implementation or for the given arguments.
54    Unsupported,
55    /// An unknown error occurred during SPI communication.
56    Unknown,
57}
58
59#[doc(hidden)]
60#[cfg(feature = "unstable")]
61#[cfg(any(spi_master_supports_dma, spi_slave_supports_dma))]
62impl From<DmaError> for Error {
63    fn from(value: DmaError) -> Self {
64        Error::DmaError(value)
65    }
66}
67
68#[doc(hidden)]
69#[cfg(not(feature = "unstable"))]
70#[cfg(any(spi_master_supports_dma, spi_slave_supports_dma))]
71impl From<DmaError> for Error {
72    fn from(_value: DmaError) -> Self {
73        Error::Unknown
74    }
75}
76
77impl embedded_hal::spi::Error for Error {
78    fn kind(&self) -> embedded_hal::spi::ErrorKind {
79        embedded_hal::spi::ErrorKind::Other
80    }
81}
82
83/// SPI communication modes, defined by clock polarity (CPOL) and clock phase
84/// (CPHA).
85///
86/// These modes control the clock signal's idle state and when data is sampled
87/// and shifted.
88#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
89#[cfg_attr(feature = "defmt", derive(defmt::Format))]
90pub enum Mode {
91    /// Mode 0 (CPOL = 0, CPHA = 0): Clock is low when idle, data is captured on
92    /// the rising edge and propagated on the falling edge.
93    _0,
94    /// Mode 1 (CPOL = 0, CPHA = 1): Clock is low when idle, data is captured on
95    /// the falling edge and propagated on the rising edge.
96    _1,
97    /// Mode 2 (CPOL = 1, CPHA = 0): Clock is high when idle, data is captured
98    /// on the falling edge and propagated on the rising edge.
99    _2,
100    /// Mode 3 (CPOL = 1, CPHA = 1): Clock is high when idle, data is captured
101    /// on the rising edge and propagated on the falling edge.
102    _3,
103}
104
105/// SPI Bit Order
106#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
107#[cfg_attr(feature = "defmt", derive(defmt::Format))]
108pub enum BitOrder {
109    /// Most Significant Bit (MSB) is transmitted first.
110    MsbFirst,
111    /// Least Significant Bit (LSB) is transmitted first.
112    LsbFirst,
113}
esp_hal/spi/mod.rs

esp_hal/spi/
mod.rs
