esp_hal/rtc_cntl/rtc/
esp32h2.rs

1use strum::FromRepr;
2
3use crate::{
4    peripherals::{PCR, PMU},
5    soc::{clocks::ClockConfig, regi2c},
6};
7
8pub(crate) fn init(_config: &ClockConfig) {
9    // * No peripheral reg i2c power up required on the target */
10    regi2c::I2C_PMU_EN_I2C_RTC_DREG.write_field(0);
11    regi2c::I2C_PMU_EN_I2C_DIG_DREG.write_field(0);
12    regi2c::I2C_PMU_EN_I2C_RTC_DREG_SLP.write_field(0);
13    regi2c::I2C_PMU_EN_I2C_DIG_DREG_SLP.write_field(0);
14    regi2c::I2C_PMU_OR_XPD_RTC_REG.write_field(0);
15    regi2c::I2C_PMU_OR_XPD_DIG_REG.write_field(0);
16    regi2c::I2C_PMU_OR_XPD_TRX.write_field(0);
17    regi2c::I2C_BIAS_DREG_0P8.write_field(8);
18
19    let pmu = PMU::regs();
20    unsafe {
21        pmu.power_pd_top_cntl().write(|w| w.bits(0));
22        pmu.power_pd_hpaon_cntl().write(|w| w.bits(0));
23        pmu.power_pd_hpcpu_cntl().write(|w| w.bits(0));
24        pmu.power_pd_hpperi_reserve().write(|w| w.bits(0));
25        pmu.power_pd_hpwifi_cntl().write(|w| w.bits(0));
26        pmu.power_pd_lpperi_cntl().write(|w| w.bits(0));
27
28        pmu.hp_active_hp_regulator0()
29            .modify(|_, w| w.hp_active_hp_regulator_dbias().bits(25));
30        pmu.hp_sleep_lp_regulator0()
31            .modify(|_, w| w.hp_sleep_lp_regulator_dbias().bits(26));
32
33        pmu.hp_sleep_dig_power().modify(|_, w| {
34            w.hp_sleep_vdd_spi_pd_en().set_bit();
35            w.hp_sleep_pd_hp_wifi_pd_en().set_bit();
36            w.hp_sleep_pd_hp_cpu_pd_en().set_bit();
37            w.hp_sleep_pd_top_pd_en().set_bit()
38        });
39
40        pmu.hp_active_hp_ck_power().modify(|_, w| {
41            w.hp_active_xpd_bbpll().set_bit();
42            w.hp_active_xpd_bb_i2c().set_bit();
43            w.hp_active_xpd_bbpll_i2c().set_bit()
44        });
45
46        pmu.hp_active_sysclk().modify(|_, w| {
47            w.hp_active_icg_sys_clock_en().set_bit();
48            w.hp_active_sys_clk_slp_sel().clear_bit();
49            w.hp_active_icg_slp_sel().clear_bit()
50        });
51        pmu.hp_sleep_sysclk().modify(|_, w| {
52            w.hp_sleep_icg_sys_clock_en().clear_bit();
53            w.hp_sleep_sys_clk_slp_sel().set_bit();
54            w.hp_sleep_icg_slp_sel().set_bit()
55        });
56
57        pmu.slp_wakeup_cntl5()
58            .modify(|_, w| w.lp_ana_wait_target().bits(15));
59        pmu.slp_wakeup_cntl7()
60            .modify(|_, w| w.ana_wait_target().bits(1700));
61    }
62
63    PCR::regs()
64        .ctrl_tick_conf()
65        .modify(|_, w| unsafe { w.fosc_tick_num().bits(255) });
66}
67
68// Terminology:
69//
70// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
71//               reset vector
72// Core Reset:   Reset the whole digital system except RTC sub-system
73// System Reset: Reset the whole digital system, including RTC sub-system
74// Chip Reset:   Reset the whole chip, including the analog part
75
76/// SOC Reset Reason.
77#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
78pub enum SocResetReason {
79    /// Power on reset
80    ///
81    /// In ESP-IDF this value (0x01) can *also* be `ChipBrownOut` or
82    /// `ChipSuperWdt`, however that is not really compatible with Rust-style
83    /// enums.
84    ChipPowerOn   = 0x01,
85    /// Software resets the digital core by RTC_CNTL_SW_SYS_RST
86    CoreSw        = 0x03,
87    /// Deep sleep reset the digital core
88    CoreDeepSleep = 0x05,
89    /// Main watch dog 0 resets digital core
90    CoreMwdt0     = 0x07,
91    /// Main watch dog 1 resets digital core
92    CoreMwdt1     = 0x08,
93    /// RTC watch dog resets digital core
94    CoreRtcWdt    = 0x09,
95    /// Main watch dog 0 resets CPU 0
96    Cpu0Mwdt0     = 0x0B,
97    /// Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
98    Cpu0Sw        = 0x0C,
99    /// RTC watch dog resets CPU 0
100    Cpu0RtcWdt    = 0x0D,
101    /// VDD voltage is not stable and resets the digital core
102    SysBrownOut   = 0x0F,
103    /// RTC watch dog resets digital core and rtc module
104    SysRtcWdt     = 0x10,
105    /// Main watch dog 1 resets CPU 0
106    Cpu0Mwdt1     = 0x11,
107    /// Super watch dog resets the digital core and rtc module
108    SysSuperWdt   = 0x12,
109    /// Glitch on clock resets the digital core and rtc module
110    SysClkGlitch  = 0x13,
111    /// eFuse CRC error resets the digital core
112    CoreEfuseCrc  = 0x14,
113    /// USB UART resets the digital core
114    CoreUsbUart   = 0x15,
115    /// USB JTAG resets the digital core
116    CoreUsbJtag   = 0x16,
117    /// Glitch on power resets the digital core
118    CorePwrGlitch = 0x17,
119}
120
121bitfield::bitfield! {
122    /// Representation of `PMU_HP_{ACTIVE,SLEEP}_DIG_POWER_REG` registers.
123    #[derive(Clone, Copy, Default)]
124    pub struct HpDigPower(u32);
125
126    pub bool, vdd_spi_pd_en, set_vdd_spi_pd_en: 21;
127    pub bool, mem_dslp     , set_mem_dslp     : 22;
128    pub bool, modem_pd_en  , set_modem_pd_en  : 27;
129    pub bool, cpu_pd_en    , set_cpu_pd_en    : 29;
130    pub bool, top_pd_en    , set_top_pd_en    : 31;
131}
132
133bitfield::bitfield! {
134    /// Representation of `PMU_HP_{ACTIVE,SLEEP}_HP_CK_POWER_REG` registers.
135    #[derive(Clone, Copy, Default)]
136    pub struct HpClkPower(u32);
137
138    pub bool, xpd_bbpll    , set_xpd_bbpll    : 30;
139}
140
141bitfield::bitfield! {
142    /// Representation of `PMU_{HP_ACTIVE,HP_SLEEP,LP_SLEEP}_XTAL_REG` register.
143    #[derive(Clone, Copy, Default)]
144    pub struct XtalPower(u32);
145
146    pub bool, xpd_xtal     , set_xpd_xtal     : 31;
147}
148
149/// Combined HP system power settings.
150#[derive(Clone, Copy, Default)]
151pub struct HpSysPower {
152    pub dig_power: HpDigPower,
153    pub clk: HpClkPower,
154    pub xtal: XtalPower,
155}
156
157bitfield::bitfield! {
158    /// Representation of `PMU_{HP,LP}_SLEEP_LP_DIG_POWER_REG`.
159    #[derive(Clone, Copy, Default)]
160    pub struct LpDigPower(u32);
161
162    pub bool, bod_source_sel, set_bod_source_sel : 27;
163    pub u32, vddbat_mode, set_vddbat_mode : 29, 28;
164    pub u32, mem_dslp  , set_mem_dslp  : 30;
165
166}
167
168bitfield::bitfield! {
169    /// Representation of `PMU_{HP,LP}_SLEEP_LP_CK_POWER_REG`.
170    #[derive(Clone, Copy, Default)]
171    pub struct LpClkPower(u32);
172
173    pub u32, xpd_xtal32k, set_xpd_xtal32k: 28;
174    pub u32, xpd_fosc   , set_xpd_fosc   : 30;
175}
176
177/// Combined LP system power settings.
178#[derive(Clone, Copy, Default)]
179pub struct LpSysPower {
180    pub dig_power: LpDigPower,
181    pub clk_power: LpClkPower,
182    pub xtal: XtalPower,
183}
184
185bitfield::bitfield! {
186    /// Representation of `PMU_HP_{ACTIVE,SLEEP}_HP_SYS_CNTL_REG` register.
187    #[derive(Clone, Copy, Default)]
188    pub struct HpSysCntlReg(u32);
189
190    pub bool, uart_wakeup_en , set_uart_wakeup_en : 24;
191    pub bool, lp_pad_hold_all, set_lp_pad_hold_all: 25;
192    pub bool, hp_pad_hold_all, set_hp_pad_hold_all: 26;
193    pub bool, dig_pad_slp_sel, set_dig_pad_slp_sel: 27;
194    pub bool, dig_pause_wdt  , set_dig_pause_wdt  : 28;
195    pub bool, dig_cpu_stall  , set_dig_cpu_stall  : 29;
196}
esp_hal/rtc_cntl/rtc/esp32h2.rs

esp_hal/rtc_cntl/rtc/
esp32h2.rs
