Available on crate feature
unstable only.Expand description
MIPI DSI bus driver (ESP32-P4).
Wraps MIPI_DSI_HOST and MIPI_DSI_BRIDGE register blocks behind two
virtual-peripheral ownership tokens (MIPI_DSI + one VDMA_CH* channel).
§Example
use esp_hal::{
clock::ll::{MipiDsiPhyPllRefclkConfig, MipiDsiPhyPllRefclkSclk},
mipi_dsi::{Config, DataLanes, MipiDsi},
};
let bus = MipiDsi::new(
peripherals.MIPI_DSI,
peripherals.VDMA_CH0,
Config::default()
.with_num_data_lanes(DataLanes::_2)
.with_lane_bit_rate_mbps(500.0)
.with_phy_pll_refclk(MipiDsiPhyPllRefclkConfig::new(
MipiDsiPhyPllRefclkSclk::Xtal, // XTAL as reference
0, // divider = 1 (div_num register = 0)
))
.with_force_clock_lane_hs(false),
)
.unwrap();Modules§
Structs§
Enums§
- Config
Error - Configuration error.
- Data
Lanes - Number of MIPI D-PHY data lanes.
Traits§
- Vdma
DmaChannel - Implemented by VDMA channel singletons (
VDMA_CH0–VDMA_CH3).