esp_hal/rtc_cntl/rtc/
esp32s2.rs

1use strum::FromRepr;
2
3use crate::soc::clocks::ClockConfig;
4
5pub(crate) fn init(_config: &ClockConfig) {}
6
7// Terminology:
8//
9// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
10//               reset vector
11// Core Reset:   Reset the whole digital system except RTC sub-system
12// System Reset: Reset the whole digital system, including RTC sub-system
13// Chip Reset:   Reset the whole chip, including the analog part
14
15/// SOC Reset Reason.
16#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
17pub enum SocResetReason {
18    /// Power on reset
19    ///
20    /// In ESP-IDF this value (0x01) can *also* be `ChipBrownOut` or
21    /// `ChipSuperWdt`, however that is not really compatible with Rust-style
22    /// enums.
23    ChipPowerOn   = 0x01,
24    /// Software resets the digital core by RTC_CNTL_SW_SYS_RST
25    CoreSw        = 0x03,
26    /// Deep sleep reset the digital core
27    CoreDeepSleep = 0x05,
28    /// Main watch dog 0 resets digital core
29    CoreMwdt0     = 0x07,
30    /// Main watch dog 1 resets digital core
31    CoreMwdt1     = 0x08,
32    /// RTC watch dog resets digital core
33    CoreRtcWdt    = 0x09,
34    /// Main watch dog 0 resets CPU 0
35    Cpu0Mwdt0     = 0x0B,
36    /// Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
37    Cpu0Sw        = 0x0C,
38    /// RTC watch dog resets CPU 0
39    Cpu0RtcWdt    = 0x0D,
40    /// VDD voltage is not stable and resets the digital core
41    SysBrownOut   = 0x0F,
42    /// RTC watch dog resets digital core and rtc module
43    SysRtcWdt     = 0x10,
44    /// Main watch dog 1 resets CPU 0
45    Cpu0Mwdt1     = 0x11,
46    /// Super watch dog resets the digital core and rtc module
47    SysSuperWdt   = 0x12,
48    /// Glitch on clock resets the digital core and rtc module
49    SysClkGlitch  = 0x13,
50    /// eFuse CRC error resets the digital core
51    CoreEfuseCrc  = 0x14,
52}
esp_hal/rtc_cntl/rtc/esp32s2.rs

esp_hal/rtc_cntl/rtc/
esp32s2.rs
