Skip to main content

Module sleep

esp_hal::rtc_cntl

Module sleep 

Source
Expand description

§RTC Control Sleep Module

§Overview

The sleep module allows configuring various wakeup sources and setting up the sleep behavior based on those sources. The supported wakeup sources include:

  • GPIO pins - light sleep only
  • timers
  • SDIO (Secure Digital Input/Output) - light sleep only
  • MAC (Media Access Control) wake - light sleep only
  • UART0 - light sleep only
  • UART1 - light sleep only
  • touch
  • ULP (Ultra-Low Power) wake
  • BT (Bluetooth) wake - light sleep only

Structs§

LowPowerunstable
Low-power management.
RtcSleepConfigunstable
Configuration for the RTC sleep behavior.

Constants§

BT_POWERUP_CYCLESunstable
Bluetooth power-up cycles.
BT_WAIT_CYCLESunstable
Bluetooth wait cycles.
CPU_TOP_POWERUP_CYCLESunstable
CPU top power-up cycles.
CPU_TOP_WAIT_CYCLESunstable
CPU top wait cycles.
DG_PERI_POWERUP_CYCLESunstable
DG peripheral power-up cycles.
DG_PERI_WAIT_CYCLESunstable
DG peripheral wait cycles.
DG_WRAP_POWERUP_CYCLESunstable
DG wrap power-up cycles.
DG_WRAP_WAIT_CYCLESunstable
DG wrap wait cycles.
OTHER_BLOCKS_POWERUPunstable
Power-up setting for other blocks.
OTHER_BLOCKS_WAITunstable
Wait cycles for other blocks.
RTC_CNTL_CK8M_WAIT_DEFAULTunstable
Default wait time for CK8M during startup.
RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOWunstable
Deep sleep debug attenuation setting for ultra-low power mode.
RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULTunstable
Default monitor debug attenuation value.
RTC_CNTL_DBIAS_0V90unstable
Digital bias setting for 0.90V.
RTC_CNTL_DBIAS_0V95unstable
Digital bias setting for 0.95V.
RTC_CNTL_DBIAS_1V00unstable
Digital bias setting for 1.00V.
RTC_CNTL_DBIAS_1V05unstable
Digital bias setting for 1.05V.
RTC_CNTL_DBIAS_1V10unstable
Digital bias setting for 1.10V.
RTC_CNTL_DBIAS_1V15unstable
Digital bias setting for 1.15V.
RTC_CNTL_DBIAS_1V20unstable
Digital bias setting for 1.20V.
RTC_CNTL_DBIAS_1V25unstable
Digital bias setting for 1.25V.
RTC_CNTL_DBIAS_1V30unstable
Digital bias setting for 1.30V. Voltage is approximately 1.34V in practice.
RTC_CNTL_MIN_SLP_VAL_MINunstable
Minimum sleep value.
RTC_CNTL_PLL_BUF_WAIT_DEFAULTunstable
Default wait time for PLL buffer during startup.
RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULTunstable
ULP co-processor touch start wait time default value.
RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEPunstable
ULP co-processor touch start wait time during sleep, set to maximum.
RTC_MEM_POWERUP_CYCLESunstable
RTC memory power-up cycles.
RTC_MEM_WAIT_CYCLESunstable
RTC memory wait cycles.
RTC_POWERUP_CYCLESunstable
RTC power-up cycles.
RTC_WAIT_CYCLESunstable
RTC wait cycles.
WIFI_POWERUP_CYCLESunstable
WiFi power-up cycles.
WIFI_WAIT_CYCLESunstable
WiFi wait cycles.