esp_hal/rtc_cntl/rtc/
esp32s3.rs

1use strum::FromRepr;
2
3use crate::soc::clocks::ClockConfig;
4
5pub(crate) fn init(_config: &ClockConfig) {}
6
7// Terminology:
8//
9// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
10//               reset vector
11// Core Reset:   Reset the whole digital system except RTC sub-system
12// System Reset: Reset the whole digital system, including RTC sub-system
13// Chip Reset:   Reset the whole chip, including the analog part
14
15/// SOC Reset Reason.
16#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
17pub enum SocResetReason {
18    /// Power on reset
19    ///
20    /// In ESP-IDF this value (0x01) can *also* be `ChipBrownOut` or
21    /// `ChipSuperWdt`, however that is not really compatible with Rust-style
22    /// enums.
23    ChipPowerOn   = 0x01,
24    /// Software resets the digital core by RTC_CNTL_SW_SYS_RST
25    CoreSw        = 0x03,
26    /// Deep sleep reset the digital core
27    CoreDeepSleep = 0x05,
28    /// Main watch dog 0 resets digital core
29    CoreMwdt0     = 0x07,
30    /// Main watch dog 1 resets digital core
31    CoreMwdt1     = 0x08,
32    /// RTC watch dog resets digital core
33    CoreRtcWdt    = 0x09,
34    /// Main watch dog 0 resets CPU
35    ///
36    /// In ESP-IDF there are `Cpu0Mwdt0` and `Cpu1Mwdt0`, however they have the
37    /// same values.
38    CpuMwdt0      = 0x0B,
39    /// Software resets CPU by RTC_CNTL_SW_(PRO|APP)CPU_RST
40    ///
41    /// In ESP-IDF there are `Cpu0Sw` and `Cpu1Sw`, however they have the same
42    /// values.
43    CpuSw         = 0x0C,
44    /// RTC watch dog resets CPU
45    ///
46    /// In ESP-IDF there are `Cpu0RtcWdt` and `Cpu1RtcWdt`, however they have
47    /// the same values.
48    CpuRtcWdt     = 0x0D,
49    /// VDD voltage is not stable and resets the digital core
50    SysBrownOut   = 0x0F,
51    /// RTC watch dog resets digital core and rtc module
52    SysRtcWdt     = 0x10,
53    /// Main watch dog 1 resets CPU
54    ///
55    /// In ESP-IDF there are `Cpu0Mwdt1` and `Cpu1Mwdt1`, however they have the
56    /// same values.
57    CpuMwdt1      = 0x11,
58    /// Super watch dog resets the digital core and rtc module
59    SysSuperWdt   = 0x12,
60    /// Glitch on clock resets the digital core and rtc module
61    SysClkGlitch  = 0x13,
62    /// eFuse CRC error resets the digital core
63    CoreEfuseCrc  = 0x14,
64    /// USB UART resets the digital core
65    CoreUsbUart   = 0x15,
66    /// USB JTAG resets the digital core
67    CoreUsbJtag   = 0x16,
68    /// Glitch on power resets the digital core
69    CorePwrGlitch = 0x17,
70}
esp_hal/rtc_cntl/rtc/esp32s3.rs

esp_hal/rtc_cntl/rtc/
esp32s3.rs
