esp_hal/rtc_cntl/rtc/
esp32s2.rs

1use strum::FromRepr;
2
3use crate::soc::clocks::ClockConfig;
4
5pub(crate) fn init(_config: &ClockConfig) {
6    calibrate_ocode();
7}
8
9// Trims the RTC bandgap using eFuse calibration data.
10//
11// See `set_ocode_by_efuse` in
12// <https://github.com/espressif/esp-idf/blob/v6.1/components/esp_hw_support/port/esp32s2/rtc_init.c>
13fn calibrate_ocode() {
14    super::calibrate_ocode(|| {
15        (crate::efuse::read_field_le::<u8>(crate::efuse::BLK_VERSION_MINOR) == 2)
16            .then(|| (crate::efuse::sign_magnitude(crate::efuse::ocode().into(), 6) + 93) as u8)
17    });
18}
19
20// Terminology:
21//
22// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
23//               reset vector
24// Core Reset:   Reset the whole digital system except RTC sub-system
25// System Reset: Reset the whole digital system, including RTC sub-system
26// Chip Reset:   Reset the whole chip, including the analog part
27
28/// SOC Reset Reason.
29#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
30pub enum SocResetReason {
31    /// Powers on reset.
32    ///
33    /// In ESP-IDF this value (0x01) can *also* be `ChipBrownOut` or
34    /// `ChipSuperWdt`, however that is not really compatible with Rust-style
35    /// enums.
36    ChipPowerOn   = 0x01,
37    /// Software resets the digital core by RTC_CNTL_SW_SYS_RST
38    CoreSw        = 0x03,
39    /// Deep sleep reset the digital core
40    CoreDeepSleep = 0x05,
41    /// Main watch dog 0 resets digital core
42    CoreMwdt0     = 0x07,
43    /// Main watch dog 1 resets digital core
44    CoreMwdt1     = 0x08,
45    /// RTC watch dog resets digital core
46    CoreRtcWdt    = 0x09,
47    /// Main watch dog 0 resets CPU 0
48    Cpu0Mwdt0     = 0x0B,
49    /// Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
50    Cpu0Sw        = 0x0C,
51    /// RTC watch dog resets CPU 0
52    Cpu0RtcWdt    = 0x0D,
53    /// VDD voltage is not stable and resets the digital core.
54    SysBrownOut   = 0x0F,
55    /// RTC watch dog resets digital core and rtc module
56    SysRtcWdt     = 0x10,
57    /// Main watch dog 1 resets CPU 0
58    Cpu0Mwdt1     = 0x11,
59    /// Super watch dog resets the digital core and rtc module
60    SysSuperWdt   = 0x12,
61    /// Glitch on clock resets the digital core and rtc module
62    SysClkGlitch  = 0x13,
63    /// eFuse CRC error resets the digital core
64    CoreEfuseCrc  = 0x14,
65}
esp_hal/rtc_cntl/rtc/esp32s2.rs

esp_hal/rtc_cntl/rtc/
esp32s2.rs
