esp_hal/rtc_cntl/rtc/
esp32s3.rs

1use strum::FromRepr;
2
3use crate::soc::clocks::ClockConfig;
4
5pub(crate) fn init(_config: &ClockConfig) {
6    calibrate_ocode();
7}
8
9// Trims the RTC bandgap using eFuse calibration data.
10//
11// See `set_ocode_by_efuse` in
12// <https://github.com/espressif/esp-idf/blob/v6.1/components/esp_hw_support/port/esp32s3/rtc_init.c>
13fn calibrate_ocode() {
14    super::calibrate_ocode(|| {
15        (crate::efuse::block_version().0 == 1)
16            .then(|| crate::efuse::read_field_le::<u8>(crate::efuse::OCODE))
17    });
18}
19
20// Terminology:
21//
22// CPU Reset:    Reset CPU core only, once reset done, CPU will execute from
23//               reset vector
24// Core Reset:   Reset the whole digital system except RTC sub-system
25// System Reset: Reset the whole digital system, including RTC sub-system
26// Chip Reset:   Reset the whole chip, including the analog part
27
28/// SOC Reset Reason.
29#[derive(Debug, Clone, Copy, PartialEq, Eq, FromRepr)]
30pub enum SocResetReason {
31    /// Powers on reset.
32    ///
33    /// In ESP-IDF this value (0x01) can *also* be `ChipBrownOut` or
34    /// `ChipSuperWdt`, however that is not really compatible with Rust-style
35    /// enums.
36    ChipPowerOn   = 0x01,
37    /// Software resets the digital core by RTC_CNTL_SW_SYS_RST
38    CoreSw        = 0x03,
39    /// Deep sleep reset the digital core
40    CoreDeepSleep = 0x05,
41    /// Main watch dog 0 resets digital core
42    CoreMwdt0     = 0x07,
43    /// Main watch dog 1 resets digital core
44    CoreMwdt1     = 0x08,
45    /// RTC watch dog resets digital core
46    CoreRtcWdt    = 0x09,
47    /// Main watch dog 0 resets CPU
48    ///
49    /// In ESP-IDF there are `Cpu0Mwdt0` and `Cpu1Mwdt0`, however they have the
50    /// same values.
51    CpuMwdt0      = 0x0B,
52    /// Software resets CPU by RTC_CNTL_SW_(PRO|APP)CPU_RST
53    ///
54    /// In ESP-IDF there are `Cpu0Sw` and `Cpu1Sw`, however they have the same
55    /// values.
56    CpuSw         = 0x0C,
57    /// RTC watch dog resets CPU
58    ///
59    /// In ESP-IDF there are `Cpu0RtcWdt` and `Cpu1RtcWdt`, however they have
60    /// the same values.
61    CpuRtcWdt     = 0x0D,
62    /// VDD voltage is not stable and resets the digital core.
63    SysBrownOut   = 0x0F,
64    /// RTC watch dog resets digital core and rtc module
65    SysRtcWdt     = 0x10,
66    /// Main watch dog 1 resets CPU
67    ///
68    /// In ESP-IDF there are `Cpu0Mwdt1` and `Cpu1Mwdt1`, however they have the
69    /// same values.
70    CpuMwdt1      = 0x11,
71    /// Super watch dog resets the digital core and rtc module
72    SysSuperWdt   = 0x12,
73    /// Glitch on clock resets the digital core and rtc module
74    SysClkGlitch  = 0x13,
75    /// eFuse CRC error resets the digital core
76    CoreEfuseCrc  = 0x14,
77    /// USB UART resets the digital core
78    CoreUsbUart   = 0x15,
79    /// USB JTAG resets the digital core
80    CoreUsbJtag   = 0x16,
81    /// Glitch on power resets the digital core
82    CorePwrGlitch = 0x17,
83}
esp_hal/rtc_cntl/rtc/esp32s3.rs

esp_hal/rtc_cntl/rtc/
esp32s3.rs
