esp_hal/lcd_cam/lcd/
mod.rs

1//! LCD
2//!
3//! ## Overview
4//! The LCD module is designed to send parallel video data signals, and its bus
5//! supports RGB, MOTO6800, and I8080 interface timing.
6//!
7//! For more information on these modes, please refer to the documentation in
8//! their respective modules.
9
10use core::marker::PhantomData;
11
12use super::GenericPeripheralGuard;
13use crate::{
14    Async,
15    Blocking,
16    DriverMode,
17    clock::ll::{ClockTree, LcdCamInstance, LcdCamLcdClockConfig},
18    lcd_cam::{ClockError, calculate_clkm},
19    peripherals::LCD_CAM,
20    system,
21    time::Rate,
22};
23
24pub mod dpi;
25pub mod i8080;
26
27pub(super) struct Inner<'d> {
28    /// The `LCD_CAM` peripheral reference for managing the LCD functionality.
29    pub lcd_cam: LCD_CAM<'d>,
30
31    pub _guard: GenericPeripheralGuard<{ system::Peripheral::LcdCam as u8 }>,
32
33    pub clock_requested: bool,
34}
35
36impl<'a> Drop for Inner<'a> {
37    fn drop(&mut self) {
38        if self.clock_requested {
39            ClockTree::with(|clocks| LcdCamInstance::LcdCam.release_lcd_clock(clocks));
40        }
41    }
42}
43
44/// Represents an LCD interface.
45pub struct Lcd<'d, Dm: DriverMode> {
46    pub(super) inner: Inner<'d>,
47
48    /// A marker for the mode of operation (blocking or asynchronous).
49    pub(super) _mode: PhantomData<Dm>,
50}
51
52struct ClockConfig {
53    /// Specifies the clock mode, including polarity and phase settings.
54    pub clock_mode: ClockMode,
55
56    /// The frequency of the pixel clock.
57    pub frequency: Rate,
58}
59
60impl<'d, Dm: DriverMode> Lcd<'d, Dm> {
61    fn regs(&self) -> &crate::pac::lcd_cam::RegisterBlock {
62        self.inner.lcd_cam.register_block()
63    }
64
65    fn configure_clocks(&mut self, config: &ClockConfig) -> Result<(), ClockError> {
66        let sources = property!("clock_tree.lcd_cam.lcd_clock.sclk");
67        let (i, divider) = calculate_clkm(
68            config.frequency.as_hz(),
69            &sources.map(LcdCamInstance::lcd_clock_source_frequency),
70        )?;
71        let clock_config =
72            LcdCamLcdClockConfig::new(sources[i], divider.div_num, divider.div_a, divider.div_b);
73
74        self.regs().lcd_clock().write(|w| unsafe {
75            // Force enable the clock for all configuration registers.
76            w.clk_en().set_bit();
77            if cfg!(esp32s3) {
78                // ESP32-S3 errata: LCD_PCLK must divide LCD_CLK by at least 2.
79                w.lcd_clk_equ_sysclk().clear_bit();
80                w.lcd_clkcnt_n().bits(2 - 1); // Must not be 0.
81            } else {
82                // ESP32-S31: PCLK tracks LCD_CLK.
83                w.lcd_clk_equ_sysclk().set_bit();
84            }
85            w.lcd_ck_idle_edge()
86                .bit(config.clock_mode.polarity == Polarity::IdleHigh);
87            w.lcd_ck_out_edge()
88                .bit(config.clock_mode.phase == Phase::ShiftHigh)
89        });
90        ClockTree::with(|clocks| {
91            LcdCamInstance::LcdCam.configure_lcd_clock(clocks, clock_config);
92            if !self.inner.clock_requested {
93                LcdCamInstance::LcdCam.request_lcd_clock(clocks);
94                self.inner.clock_requested = true;
95            }
96        });
97
98        Ok(())
99    }
100
101    pub(super) fn into_async(self) -> Lcd<'d, Async> {
102        Lcd {
103            inner: self.inner,
104            _mode: PhantomData,
105        }
106    }
107}
108
109impl<'d> Lcd<'d, Async> {
110    pub(super) fn into_blocking(self) -> Lcd<'d, Blocking> {
111        Lcd {
112            inner: self.inner,
113            _mode: PhantomData,
114        }
115    }
116}
117
118#[derive(Debug, Clone, Copy, PartialEq, Default)]
119#[cfg_attr(feature = "defmt", derive(defmt::Format))]
120/// Represents the clock mode configuration for the LCD interface.
121pub struct ClockMode {
122    /// The polarity of the clock signal (idle high or low).
123    pub polarity: Polarity,
124
125    /// The phase of the clock signal (shift on the rising or falling edge).
126    pub phase: Phase,
127}
128
129#[derive(Debug, Clone, Copy, PartialEq, Default)]
130#[cfg_attr(feature = "defmt", derive(defmt::Format))]
131/// Represents the polarity of the clock signal for the LCD interface.
132pub enum Polarity {
133    /// The clock signal is low when idle.
134    #[default]
135    IdleLow,
136
137    /// The clock signal is high when idle.
138    IdleHigh,
139}
140
141#[derive(Debug, Clone, Copy, PartialEq, Default)]
142#[cfg_attr(feature = "defmt", derive(defmt::Format))]
143/// Represents the phase of the clock signal for the LCD interface.
144pub enum Phase {
145    /// Data is shifted on the low (falling) edge of the clock signal.
146    #[default]
147    ShiftLow,
148
149    /// Data is shifted on the high (rising) edge of the clock signal.
150    ShiftHigh,
151}
152
153#[derive(Debug, Clone, Copy, PartialEq, Default)]
154#[cfg_attr(feature = "defmt", derive(defmt::Format))]
155/// Represents the delay mode for the LCD signal output.
156pub enum DelayMode {
157    /// Output without delay.
158    #[default]
159    None        = 0,
160    /// Delayed by the rising edge of LCD_CLK.
161    RaisingEdge = 1,
162    /// Delayed by the falling edge of LCD_CLK.
163    FallingEdge = 2,
164}
esp_hal/lcd_cam/lcd/mod.rs

esp_hal/lcd_cam/lcd/
mod.rs
