Macro property 

macro_rules! property {
    ("chip") => { ... };
    ("arch") => { ... };
    ("cores") => { ... };
    ("cores", str) => { ... };
    ("trm") => { ... };
    ("soc.cpu_has_csr_pc") => { ... };
    ("soc.cpu_has_prv_mode") => { ... };
    ("soc.rc_fast_clk_default") => { ... };
    ("soc.rc_fast_clk_default", str) => { ... };
    ("soc.rc_slow_clock") => { ... };
    ("soc.rc_slow_clock", str) => { ... };
    ("soc.xtal_frequency") => { ... };
    ("soc.xtal_frequency", str) => { ... };
    ("aes.dma") => { ... };
    ("aes.has_split_text_registers") => { ... };
    ("aes.endianness_configurable") => { ... };
    ("assist_debug.has_sp_monitor") => { ... };
    ("assist_debug.has_region_monitor") => { ... };
    ("gpio.has_bank_1") => { ... };
    ("gpio.gpio_function") => { ... };
    ("gpio.gpio_function", str) => { ... };
    ("gpio.constant_0_input") => { ... };
    ("gpio.constant_0_input", str) => { ... };
    ("gpio.constant_1_input") => { ... };
    ("gpio.constant_1_input", str) => { ... };
    ("gpio.remap_iomux_pin_registers") => { ... };
    ("gpio.func_in_sel_offset") => { ... };
    ("gpio.func_in_sel_offset", str) => { ... };
    ("gpio.input_signal_max") => { ... };
    ("gpio.input_signal_max", str) => { ... };
    ("gpio.output_signal_max") => { ... };
    ("gpio.output_signal_max", str) => { ... };
    ("i2c_master.has_fsm_timeouts") => { ... };
    ("i2c_master.has_hw_bus_clear") => { ... };
    ("i2c_master.has_bus_timeout_enable") => { ... };
    ("i2c_master.separate_filter_config_registers") => { ... };
    ("i2c_master.can_estimate_nack_reason") => { ... };
    ("i2c_master.has_conf_update") => { ... };
    ("i2c_master.has_reliable_fsm_reset") => { ... };
    ("i2c_master.has_arbitration_en") => { ... };
    ("i2c_master.has_tx_fifo_watermark") => { ... };
    ("i2c_master.bus_timeout_is_exponential") => { ... };
    ("i2c_master.max_bus_timeout") => { ... };
    ("i2c_master.max_bus_timeout", str) => { ... };
    ("i2c_master.ll_intr_mask") => { ... };
    ("i2c_master.ll_intr_mask", str) => { ... };
    ("i2c_master.fifo_size") => { ... };
    ("i2c_master.fifo_size", str) => { ... };
    ("interrupts.status_registers") => { ... };
    ("interrupts.status_registers", str) => { ... };
    ("rmt.ram_start") => { ... };
    ("rmt.ram_start", str) => { ... };
    ("rmt.channel_ram_size") => { ... };
    ("rmt.channel_ram_size", str) => { ... };
    ("rmt.has_tx_immediate_stop") => { ... };
    ("rmt.has_tx_loop_count") => { ... };
    ("rmt.has_tx_loop_auto_stop") => { ... };
    ("rmt.has_tx_carrier_data_only") => { ... };
    ("rmt.has_tx_sync") => { ... };
    ("rmt.has_rx_wrap") => { ... };
    ("rmt.has_rx_demodulation") => { ... };
    ("rmt.has_dma") => { ... };
    ("rmt.has_per_channel_clock") => { ... };
    ("rng.apb_cycle_wait_num") => { ... };
    ("rng.apb_cycle_wait_num", str) => { ... };
    ("rsa.size_increment") => { ... };
    ("rsa.size_increment", str) => { ... };
    ("rsa.memory_size_bytes") => { ... };
    ("rsa.memory_size_bytes", str) => { ... };
    ("sha.dma") => { ... };
    ("spi_master.has_octal") => { ... };
    ("timergroup.timg_has_timer1") => { ... };
    ("timergroup.timg_has_divcnt_rst") => { ... };
    ("timergroup.default_clock_source") => { ... };
    ("timergroup.default_clock_source", str) => { ... };
    ("timergroup.default_wdt_clock_source") => { ... };
    ("timergroup.default_wdt_clock_source", str) => { ... };
    ("uart.ram_size") => { ... };
    ("uart.ram_size", str) => { ... };
    ("bt.controller") => { ... };
    ("phy.combo_module") => { ... };
}

Available on crate feature _device-selected only.

The properties of this chip and its drivers.