Macro property 

macro_rules! property {
    ("chip") => { ... };
    ("arch") => { ... };
    ("cores") => { ... };
    ("cores", str) => { ... };
    ("trm") => { ... };
    ("aes.dma") => { ... };
    ("aes.has_split_text_registers") => { ... };
    ("aes.endianness_configurable") => { ... };
    ("assist_debug.has_sp_monitor") => { ... };
    ("assist_debug.has_region_monitor") => { ... };
    ("bt.controller") => { ... };
    ("dedicated_gpio.needs_initialization") => { ... };
    ("dedicated_gpio.channel_count") => { ... };
    ("dedicated_gpio.channel_count", str) => { ... };
    ("dma.kind") => { ... };
    ("dma.supports_mem2mem") => { ... };
    ("dma.can_access_psram") => { ... };
    ("dma.ext_mem_configurable_block_size") => { ... };
    ("dma.separate_in_out_interrupts") => { ... };
    ("dma.max_priority") => { ... };
    ("dma.max_priority", str) => { ... };
    ("dma.gdma_version") => { ... };
    ("dma.gdma_version", str) => { ... };
    ("ecc.zero_extend_writes") => { ... };
    ("ecc.separate_jacobian_point_memory") => { ... };
    ("ecc.has_memory_clock_gate") => { ... };
    ("ecc.supports_enhanced_security") => { ... };
    ("ecc.mem_block_size") => { ... };
    ("gpio.has_bank_1") => { ... };
    ("gpio.gpio_function") => { ... };
    ("gpio.gpio_function", str) => { ... };
    ("gpio.constant_0_input") => { ... };
    ("gpio.constant_0_input", str) => { ... };
    ("gpio.constant_1_input") => { ... };
    ("gpio.constant_1_input", str) => { ... };
    ("gpio.remap_iomux_pin_registers") => { ... };
    ("gpio.func_in_sel_offset") => { ... };
    ("gpio.func_in_sel_offset", str) => { ... };
    ("gpio.input_signal_max") => { ... };
    ("gpio.input_signal_max", str) => { ... };
    ("gpio.output_signal_max") => { ... };
    ("gpio.output_signal_max", str) => { ... };
    ("i2c_master.has_fsm_timeouts") => { ... };
    ("i2c_master.has_hw_bus_clear") => { ... };
    ("i2c_master.has_bus_timeout_enable") => { ... };
    ("i2c_master.separate_filter_config_registers") => { ... };
    ("i2c_master.can_estimate_nack_reason") => { ... };
    ("i2c_master.has_conf_update") => { ... };
    ("i2c_master.has_reliable_fsm_reset") => { ... };
    ("i2c_master.has_arbitration_en") => { ... };
    ("i2c_master.has_tx_fifo_watermark") => { ... };
    ("i2c_master.bus_timeout_is_exponential") => { ... };
    ("i2c_master.max_bus_timeout") => { ... };
    ("i2c_master.max_bus_timeout", str) => { ... };
    ("i2c_master.ll_intr_mask") => { ... };
    ("i2c_master.ll_intr_mask", str) => { ... };
    ("i2c_master.fifo_size") => { ... };
    ("i2c_master.fifo_size", str) => { ... };
    ("interrupts.status_registers") => { ... };
    ("interrupts.status_registers", str) => { ... };
    ("interrupts.disabled_interrupt") => { ... };
    ("parl_io.version") => { ... };
    ("parl_io.version", str) => { ... };
    ("phy.combo_module") => { ... };
    ("rmt.ram_start") => { ... };
    ("rmt.ram_start", str) => { ... };
    ("rmt.channel_ram_size") => { ... };
    ("rmt.channel_ram_size", str) => { ... };
    ("rmt.has_tx_immediate_stop") => { ... };
    ("rmt.has_tx_loop_count") => { ... };
    ("rmt.has_tx_loop_auto_stop") => { ... };
    ("rmt.has_tx_carrier_data_only") => { ... };
    ("rmt.has_tx_sync") => { ... };
    ("rmt.has_rx_wrap") => { ... };
    ("rmt.has_rx_demodulation") => { ... };
    ("rmt.has_dma") => { ... };
    ("rmt.has_per_channel_clock") => { ... };
    ("rng.apb_cycle_wait_num") => { ... };
    ("rng.apb_cycle_wait_num", str) => { ... };
    ("rng.trng_supported") => { ... };
    ("rsa.size_increment") => { ... };
    ("rsa.size_increment", str) => { ... };
    ("rsa.memory_size_bytes") => { ... };
    ("rsa.memory_size_bytes", str) => { ... };
    ("sha.dma") => { ... };
    ("sleep.light_sleep") => { ... };
    ("sleep.deep_sleep") => { ... };
    ("soc.cpu_has_branch_predictor") => { ... };
    ("soc.cpu_has_csr_pc") => { ... };
    ("soc.multi_core_enabled") => { ... };
    ("soc.cpu_csr_prv_mode") => { ... };
    ("soc.cpu_csr_prv_mode", str) => { ... };
    ("soc.rc_fast_clk_default") => { ... };
    ("soc.rc_fast_clk_default", str) => { ... };
    ("clock_tree.cpu_clk.divisor") => { ... };
    ("clock_tree.ahb_clk.divisor") => { ... };
    ("clock_tree.apb_clk.divisor") => { ... };
    ("clock_tree.uart.function_clock.div_num") => { ... };
    ("clock_tree.uart.baud_rate_generator.fractional") => { ... };
    ("clock_tree.uart.baud_rate_generator.integral") => { ... };
    ("spi_master.supports_dma") => { ... };
    ("spi_master.has_octal") => { ... };
    ("spi_master.has_app_interrupts") => { ... };
    ("spi_master.has_dma_segmented_transfer") => { ... };
    ("spi_master.has_clk_pre_div") => { ... };
    ("spi_slave.supports_dma") => { ... };
    ("timergroup.timg_has_timer1") => { ... };
    ("timergroup.timg_has_divcnt_rst") => { ... };
    ("timergroup.rc_fast_calibration_divider_min_rev") => { ... };
    ("timergroup.rc_fast_calibration_divider") => { ... };
    ("timergroup.rc_fast_calibration_tick_enable") => { ... };
    ("uart.ram_size") => { ... };
    ("uart.ram_size", str) => { ... };
    ("uart.peripheral_controls_mem_clk") => { ... };
    ("uart.has_sclk_divider") => { ... };
    ("uhci.combined_uart_selector_field") => { ... };
}

Available on crate feature _device-selected only.

The properties of this chip and its drivers.