esp_metadata_generated/

_generated_esp32.rs

// Do NOT edit this file directly. Make your changes to esp-metadata,
// then run `cargo update-metadata`.

/// The name of the chip as `&str`
///
/// # Example
///
/// ```rust, no_run
/// use esp_hal::chip;
/// let chip_name = chip!();
#[doc = concat!("assert_eq!(chip_name, ", chip!(), ")")]
/// ```
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! chip {
    () => {
        "esp32"
    };
}
/// The pretty name of the chip as `&str`
///
/// # Example
///
/// ```rust, no_run
/// use esp_hal::chip;
/// let chip_name = chip_pretty!();
#[doc = concat!("assert_eq!(chip_name, ", chip_pretty!(), ")")]
/// ```
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! chip_pretty {
    () => {
        "ESP32"
    };
}
/// The properties of this chip and its drivers.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! property {
    ("chip") => {
        "esp32"
    };
    ("arch") => {
        "xtensa"
    };
    ("cores") => {
        2
    };
    ("cores", str) => {
        stringify!(2)
    };
    ("trm") => {
        "https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf"
    };
    ("gpio.version") => {
        1
    };
    ("gpio.version", str) => {
        stringify!(1)
    };
    ("gpio.has_input_sync") => {
        false
    };
    ("gpio.gpio_function") => {
        2
    };
    ("gpio.gpio_function", str) => {
        stringify!(2)
    };
    ("gpio.constant_0_input") => {
        48
    };
    ("gpio.constant_0_input", str) => {
        stringify!(48)
    };
    ("gpio.constant_1_input") => {
        56
    };
    ("gpio.constant_1_input", str) => {
        stringify!(56)
    };
    ("gpio.remap_iomux_pin_registers") => {
        true
    };
    ("gpio.func_in_sel_offset") => {
        0
    };
    ("gpio.func_in_sel_offset", str) => {
        stringify!(0)
    };
    ("gpio.need_soft_isolate_during_pd") => {
        false
    };
    ("gpio.has_bank_1") => {
        true
    };
    ("gpio.input_signal_max") => {
        206
    };
    ("gpio.input_signal_max", str) => {
        stringify!(206)
    };
    ("gpio.output_signal_max") => {
        256
    };
    ("gpio.output_signal_max", str) => {
        stringify!(256)
    };
    ("lp_io.version") => {
        "esp32"
    };
    ("lp_io.has_gpio_matrix") => {
        false
    };
    ("uart.ram_size") => {
        128
    };
    ("uart.ram_size", str) => {
        stringify!(128)
    };
    ("uart.version") => {
        1
    };
    ("uart.version", str) => {
        stringify!(1)
    };
    ("uart.peripheral_controls_mem_clk") => {
        false
    };
    ("uart.has_sclk_divider") => {
        false
    };
    ("uart.has_sclk_enable") => {
        false
    };
    ("i2c_master.version") => {
        1
    };
    ("i2c_master.version", str) => {
        stringify!(1)
    };
    ("i2c_master.has_fsm_timeouts") => {
        false
    };
    ("i2c_master.has_hw_bus_clear") => {
        false
    };
    ("i2c_master.has_bus_timeout_enable") => {
        false
    };
    ("i2c_master.separate_filter_config_registers") => {
        true
    };
    ("i2c_master.can_estimate_nack_reason") => {
        false
    };
    ("i2c_master.has_conf_update") => {
        false
    };
    ("i2c_master.has_reliable_fsm_reset") => {
        false
    };
    ("i2c_master.has_arbitration_en") => {
        false
    };
    ("i2c_master.has_tx_fifo_watermark") => {
        false
    };
    ("i2c_master.bus_timeout_is_exponential") => {
        false
    };
    ("i2c_master.has_pd_en") => {
        false
    };
    ("i2c_master.i2c0_data_register_ahb_address") => {
        1610690588
    };
    ("i2c_master.i2c0_data_register_ahb_address", str) => {
        stringify!(1610690588)
    };
    ("i2c_master.max_bus_timeout") => {
        1048575
    };
    ("i2c_master.max_bus_timeout", str) => {
        stringify!(1048575)
    };
    ("i2c_master.ll_intr_mask") => {
        262143
    };
    ("i2c_master.ll_intr_mask", str) => {
        stringify!(262143)
    };
    ("i2c_master.fifo_size") => {
        32
    };
    ("i2c_master.fifo_size", str) => {
        stringify!(32)
    };
    ("spi_master.version") => {
        1
    };
    ("spi_master.version", str) => {
        stringify!(1)
    };
    ("spi_master.fifo_size") => {
        64
    };
    ("spi_master.fifo_size", str) => {
        stringify!(64)
    };
    ("spi_master.bit_order_is_bool") => {
        true
    };
    ("spi_master.has_octal") => {
        false
    };
    ("spi_master.has_app_interrupts") => {
        false
    };
    ("spi_master.has_dma_segmented_transfer") => {
        false
    };
    ("spi_master.has_clk_pre_div") => {
        false
    };
    ("spi_master.dma_can_access_flash") => {
        false
    };
    ("i2s.version") => {
        1
    };
    ("i2s.version", str) => {
        stringify!(1)
    };
    ("i2s.mclk_divider_bit_width") => {
        6
    };
    ("i2s.mclk_divider_bit_width", str) => {
        stringify!(6)
    };
    ("i2s.max_ws_width") => {
        128
    };
    ("i2s.max_ws_width", str) => {
        stringify!(128)
    };
    ("i2s.clock_configured_by_pcr") => {
        false
    };
    ("i2s.clock_configured_by_hp_sys_clkrst") => {
        false
    };
    ("i2s.supports_pdm_rx_hp_filter") => {
        false
    };
    ("i2s.supports_pdm_tx") => {
        true
    };
    ("i2s.supports_pdm_rx") => {
        true
    };
    ("i2s.supports_pcm2pdm") => {
        true
    };
    ("i2s.supports_pdm2pcm") => {
        true
    };
    ("rmt.ram_start") => {
        1073047552
    };
    ("rmt.ram_start", str) => {
        stringify!(1073047552)
    };
    ("rmt.channel_ram_size") => {
        64
    };
    ("rmt.channel_ram_size", str) => {
        stringify!(64)
    };
    ("rmt.has_tx_immediate_stop") => {
        false
    };
    ("rmt.has_tx_loop_count") => {
        false
    };
    ("rmt.has_tx_loop_auto_stop") => {
        false
    };
    ("rmt.has_tx_carrier_data_only") => {
        false
    };
    ("rmt.has_tx_sync") => {
        false
    };
    ("rmt.has_rx_wrap") => {
        false
    };
    ("rmt.has_rx_demodulation") => {
        false
    };
    ("rmt.has_per_channel_clock") => {
        true
    };
    ("sdmmc.has_iomux") => {
        true
    };
    ("sdmmc.has_gpio_matrix") => {
        false
    };
    ("sdmmc.psram_dma") => {
        false
    };
    ("sdmmc.uhs") => {
        false
    };
    ("bt.controller") => {
        "btdm"
    };
    ("wifi.has_wifi6") => {
        false
    };
    ("wifi.mac_version") => {
        1
    };
    ("wifi.mac_version", str) => {
        stringify!(1)
    };
    ("wifi.has_5g") => {
        false
    };
    ("wifi.csi_supported") => {
        true
    };
    ("wifi.has_nan") => {
        true
    };
    ("wifi.has_ftm") => {
        false
    };
    ("ethernet.mii_via_gpio_matrix") => {
        false
    };
    ("ethernet.rx_store_and_forward") => {
        true
    };
    ("ethernet.rx_checksum_offload") => {
        false
    };
    ("ethernet.tx_checksum_offload") => {
        false
    };
    ("ethernet.dma_burst_len") => {
        32
    };
    ("ethernet.dma_burst_len", str) => {
        stringify!(32)
    };
    ("ethernet.has_rgmii") => {
        false
    };
    ("phy.combo_module") => {
        true
    };
    ("rgb_display.output_lines") => {
        24
    };
    ("rgb_display.output_lines", str) => {
        stringify!(24)
    };
    ("adc.line_calibration") => {
        true
    };
    ("adc.curve_calibration") => {
        false
    };
    ("adc.basic_calibration") => {
        false
    };
    ("adc.calibration_v1_scheme_supported") => {
        false
    };
    ("adc.channel_compensation") => {
        false
    };
    ("adc.pcr_clock") => {
        false
    };
    ("adc.pcr_sar_clk_div") => {
        false
    };
    ("adc.sar_power_override") => {
        false
    };
    ("ledc.version") => {
        1
    };
    ("ledc.version", str) => {
        stringify!(1)
    };
    ("ledc.channel_count") => {
        8
    };
    ("ledc.channel_count", str) => {
        stringify!(8)
    };
    ("sdm.channel_count") => {
        8
    };
    ("sdm.channel_count", str) => {
        stringify!(8)
    };
    ("timergroup.timg_has_timer1") => {
        true
    };
    ("timergroup.timg_has_divcnt_rst") => {
        false
    };
    ("timergroup.wdt_has_conf_update") => {
        false
    };
    ("aes.has_split_text_registers") => {
        false
    };
    ("aes.endianness_configurable") => {
        true
    };
    ("rng.apb_cycle_wait_num") => {
        16
    };
    ("rng.apb_cycle_wait_num", str) => {
        stringify!(16)
    };
    ("rng.trng_supported") => {
        true
    };
    ("rng.is_lp_sys") => {
        false
    };
    ("rsa.version") => {
        1
    };
    ("rsa.version", str) => {
        stringify!(1)
    };
    ("rsa.size_increment") => {
        512
    };
    ("rsa.size_increment", str) => {
        stringify!(512)
    };
    ("rsa.memory_size_bytes") => {
        512
    };
    ("rsa.memory_size_bytes", str) => {
        stringify!(512)
    };
    ("sleep.light_sleep") => {
        true
    };
    ("sleep.deep_sleep") => {
        true
    };
    ("sleep.rejectable_mask") => {
        20
    };
    ("sleep.ext1_version") => {
        1
    };
    ("sleep.ext1_version", str) => {
        stringify!(1)
    };
    ("sleep.pin_wakeup_version") => {
        1
    };
    ("sleep.pin_wakeup_version", str) => {
        stringify!(1)
    };
    ("sleep.deep_sleep_needs_gpio_isolation") => {
        true
    };
    ("dma.mem2mem_requires_peripheral") => {
        false
    };
    ("dma.ext_mem_configurable_block_size") => {
        false
    };
    ("dma.separate_in_out_interrupts") => {
        false
    };
    ("interrupts.status_registers") => {
        3
    };
    ("interrupts.status_registers", str) => {
        stringify!(3)
    };
    ("mmu.page_size") => {
        65536
    };
    ("mmu.page_size", str) => {
        stringify!(65536)
    };
    ("mmu.entry_num") => {
        256
    };
    ("mmu.entry_num", str) => {
        stringify!(256)
    };
    ("psram.octal_spi") => {
        false
    };
    ("psram.hex_spi") => {
        false
    };
    ("psram.extmem_origin") => {
        1065353216
    };
    ("psram.extmem_origin", str) => {
        stringify!(1065353216)
    };
    ("rom.has_crc_le") => {
        true
    };
    ("rom.has_crc_be") => {
        true
    };
    ("rom.has_md5_bsd") => {
        true
    };
    ("rom.has_md5_mbedtls") => {
        false
    };
    ("soc.cpu_has_branch_predictor") => {
        false
    };
    ("soc.cpu_has_csr_pc") => {
        false
    };
    ("soc.cpu_has_zcmp_workaround") => {
        false
    };
    ("soc.multi_core_enabled") => {
        true
    };
    ("soc.internal_memory_cached") => {
        false
    };
    ("soc.has_swd_watchdog") => {
        false
    };
    ("soc.cpu_mcause_mask") => {
        0
    };
    ("soc.cpu_mcause_mask", str) => {
        stringify!(0)
    };
    ("soc.cpu_pmp_granularity") => {
        4
    };
    ("soc.cpu_pmp_granularity", str) => {
        stringify!(4)
    };
    ("clock_tree.cpu_pll_div_in") => {
        [crate ::soc::clocks::CpuPllDivInConfig::Pll, crate
        ::soc::clocks::CpuPllDivInConfig::Apll]
    };
    ("clock_tree.cpu_pll_div.divisor") => {
        [2, 4]
    };
    ("clock_tree.syscon_pre_div_in") => {
        [crate ::soc::clocks::SysconPreDivInConfig::Xtal, crate
        ::soc::clocks::SysconPreDivInConfig::RcFast]
    };
    ("clock_tree.syscon_pre_div.divisor") => {
        (0, 1023)
    };
    ("clock_tree.cpu_clk") => {
        [crate ::soc::clocks::CpuClkConfig::Xtal, crate
        ::soc::clocks::CpuClkConfig::RcFast, crate ::soc::clocks::CpuClkConfig::Apll,
        crate ::soc::clocks::CpuClkConfig::Pll]
    };
    ("clock_tree.apb_clk") => {
        [crate ::soc::clocks::ApbClkConfig::Pll80m, crate
        ::soc::clocks::ApbClkConfig::CpuDiv2, crate ::soc::clocks::ApbClkConfig::Cpu]
    };
    ("clock_tree.ref_tick_pll.divisor") => {
        (0, 255)
    };
    ("clock_tree.ref_tick_apll.divisor") => {
        (0, 255)
    };
    ("clock_tree.ref_tick_xtal.divisor") => {
        (0, 255)
    };
    ("clock_tree.ref_tick_fosc.divisor") => {
        (0, 255)
    };
    ("clock_tree.ref_tick") => {
        [crate ::soc::clocks::RefTickConfig::Pll, crate
        ::soc::clocks::RefTickConfig::Apll, crate ::soc::clocks::RefTickConfig::Xtal,
        crate ::soc::clocks::RefTickConfig::Fosc]
    };
    ("clock_tree.rtc_slow_clk") => {
        [#[cfg(use_xtal32k)] crate ::soc::clocks::RtcSlowClkConfig::Xtal32k, crate
        ::soc::clocks::RtcSlowClkConfig::RcSlow, crate
        ::soc::clocks::RtcSlowClkConfig::RcFast]
    };
    ("clock_tree.ble_lp_clk") => {
        [crate ::soc::clocks::BleLpClkConfig::Xtal, crate
        ::soc::clocks::BleLpClkConfig::RtcSlow]
    };
    ("clock_tree.rtc_fast_clk") => {
        [crate ::soc::clocks::RtcFastClkConfig::Xtal, crate
        ::soc::clocks::RtcFastClkConfig::Rc]
    };
    ("clock_tree.timg_calibration_clock") => {
        [crate ::soc::clocks::TimgCalibrationClockConfig::RcSlowClk, crate
        ::soc::clocks::TimgCalibrationClockConfig::RcFastDivClk, #[cfg(use_xtal32k)]
        crate ::soc::clocks::TimgCalibrationClockConfig::Xtal32kClk]
    };
    ("clock_tree.i2c.function_clock.sclk") => {
        [crate ::soc::clocks::I2cFunctionClockSclk::Apb]
    };
    ("clock_tree.uart.function_clock.sclk") => {
        [crate ::soc::clocks::UartFunctionClockSclk::Apb, crate
        ::soc::clocks::UartFunctionClockSclk::RefTick]
    };
    ("clock_tree.uart.baud_rate_generator.fractional") => {
        (0, 15)
    };
    ("clock_tree.uart.baud_rate_generator.integral") => {
        (0, 1048575)
    };
    ("clock_tree.rmt.sclk") => {
        [crate ::soc::clocks::RmtSclkConfig::RefTick, crate
        ::soc::clocks::RmtSclkConfig::ApbClk]
    };
    ("clock_tree.i2s.mclk.sclk") => {
        [crate ::soc::clocks::I2sMclkSclk::PllF160m, crate
        ::soc::clocks::I2sMclkSclk::Apll]
    };
    ("clock_tree.i2s.mclk.div_num") => {
        (1, 255)
    };
    ("clock_tree.i2s.mclk.div_a") => {
        (1, 63)
    };
    ("clock_tree.i2s.mclk.div_b") => {
        (0, 63)
    };
}
/// Defines the `LpInputSignal` and `LpOutputSignal` enums.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_lp_io_signals {
    () => {};
}
/// This macro can be used to generate code for each channel of the RMT peripheral.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has three options for its "Individual matcher" case:
///
/// - `all`: `($num:literal)`
/// - `tx`: `($num:literal, $idx:literal)`
/// - `rx`: `($num:literal, $idx:literal)`
///
/// Macro fragments:
///
/// - `$num`: number of the channel, e.g. `0`
/// - `$idx`: index of the channel among channels of the same capability, e.g. `0`
///
/// Example data:
///
/// - `all`: `(0)`
/// - `tx`: `(1, 1)`
/// - `rx`: `(2, 0)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_rmt_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_rmt_channel { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_rmt_channel!((0)); _for_each_inner_rmt_channel!((1));
        _for_each_inner_rmt_channel!((2)); _for_each_inner_rmt_channel!((3));
        _for_each_inner_rmt_channel!((4)); _for_each_inner_rmt_channel!((5));
        _for_each_inner_rmt_channel!((6)); _for_each_inner_rmt_channel!((7));
        _for_each_inner_rmt_channel!((0, 0)); _for_each_inner_rmt_channel!((1, 1));
        _for_each_inner_rmt_channel!((2, 2)); _for_each_inner_rmt_channel!((3, 3));
        _for_each_inner_rmt_channel!((4, 4)); _for_each_inner_rmt_channel!((5, 5));
        _for_each_inner_rmt_channel!((6, 6)); _for_each_inner_rmt_channel!((7, 7));
        _for_each_inner_rmt_channel!((0, 0)); _for_each_inner_rmt_channel!((1, 1));
        _for_each_inner_rmt_channel!((2, 2)); _for_each_inner_rmt_channel!((3, 3));
        _for_each_inner_rmt_channel!((4, 4)); _for_each_inner_rmt_channel!((5, 5));
        _for_each_inner_rmt_channel!((6, 6)); _for_each_inner_rmt_channel!((7, 7));
        _for_each_inner_rmt_channel!((all(0), (1), (2), (3), (4), (5), (6), (7)));
        _for_each_inner_rmt_channel!((tx(0, 0), (1, 1), (2, 2), (3, 3), (4, 4), (5, 5),
        (6, 6), (7, 7))); _for_each_inner_rmt_channel!((rx(0, 0), (1, 1), (2, 2), (3, 3),
        (4, 4), (5, 5), (6, 6), (7, 7)));
    };
}
/// This macro can be used to generate code for each slot of the SDMMC/SDIO host driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($slot:ident, $idx:literal, $iomux:literal, [$($clk:ident)?]
/// [$($cmd_in:ident)?] [$($cmd_out:ident)?] [$($data_in:ident),*] [$($data_out:ident),*]
/// [$($cd:ident)?] [$($wp:ident)?] [$($card_int:ident)?] [$($data_strobe:ident)?]
/// [$($rst:ident)?])`
///
/// Macro fragments:
///
/// - `$slot`: the name of the slot (`slot0`, `slot1`).
/// - `$idx`: the zero-based slot index.
/// - `$iomux`: `true` if the slot's clock/command/data signals are IO_MUX-routed.
/// - `$clk`, `$cmd_in`, `$cmd_out`, `$data_in`, `$data_out`: GPIO-matrix bus signal names (absent
///   for IO_MUX-routed slots).
/// - `$cd`, `$wp`, `$card_int`, `$data_strobe`, `$rst`: auxiliary signal names, each present only
///   when the slot routes that signal through the GPIO matrix.
///
/// Each optional signal is wrapped in brackets so the branch shape stays uniform: a set
/// signal appears as `[SIGNAL]`, an absent one as `[]`.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sdmmc {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sdmmc { $(($pattern) => $code;)* ($other : tt) => {}
        } _for_each_inner_sdmmc!((slot0, 0, true, [], [], [], [], [],
        [HOST_CARD_DETECT_N_1], [HOST_CARD_WRITE_PRT_1], [HOST_CARD_INT_N_1], [],
        [HOST_RST_N_1])); _for_each_inner_sdmmc!((slot1, 1, true, [], [], [], [], [],
        [HOST_CARD_DETECT_N_2], [HOST_CARD_WRITE_PRT_2], [HOST_CARD_INT_N_2], [],
        [HOST_RST_N_2])); _for_each_inner_sdmmc!((all(slot0, 0, true, [], [], [], [], [],
        [HOST_CARD_DETECT_N_1], [HOST_CARD_WRITE_PRT_1], [HOST_CARD_INT_N_1], [],
        [HOST_RST_N_1]), (slot1, 1, true, [], [], [], [], [], [HOST_CARD_DETECT_N_2],
        [HOST_CARD_WRITE_PRT_2], [HOST_CARD_INT_N_2], [], [HOST_RST_N_2])));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sdm_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sdm_channel { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_sdm_channel!((0, SDM_CH0, SdmCh0, GPIO_SD0));
        _for_each_inner_sdm_channel!((1, SDM_CH1, SdmCh1, GPIO_SD1));
        _for_each_inner_sdm_channel!((2, SDM_CH2, SdmCh2, GPIO_SD2));
        _for_each_inner_sdm_channel!((3, SDM_CH3, SdmCh3, GPIO_SD3));
        _for_each_inner_sdm_channel!((4, SDM_CH4, SdmCh4, GPIO_SD4));
        _for_each_inner_sdm_channel!((5, SDM_CH5, SdmCh5, GPIO_SD5));
        _for_each_inner_sdm_channel!((6, SDM_CH6, SdmCh6, GPIO_SD6));
        _for_each_inner_sdm_channel!((7, SDM_CH7, SdmCh7, GPIO_SD7));
        _for_each_inner_sdm_channel!((channels(0, SDM_CH0, SdmCh0, GPIO_SD0), (1,
        SDM_CH1, SdmCh1, GPIO_SD1), (2, SDM_CH2, SdmCh2, GPIO_SD2), (3, SDM_CH3, SdmCh3,
        GPIO_SD3), (4, SDM_CH4, SdmCh4, GPIO_SD4), (5, SDM_CH5, SdmCh5, GPIO_SD5), (6,
        SDM_CH6, SdmCh6, GPIO_SD6), (7, SDM_CH7, SdmCh7, GPIO_SD7)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_aes_key_length {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_aes_key_length { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_aes_key_length!((128));
        _for_each_inner_aes_key_length!((192)); _for_each_inner_aes_key_length!((256));
        _for_each_inner_aes_key_length!((128, 0, 4));
        _for_each_inner_aes_key_length!((192, 1, 5));
        _for_each_inner_aes_key_length!((256, 2, 6));
        _for_each_inner_aes_key_length!((bits(128), (192), (256)));
        _for_each_inner_aes_key_length!((modes(128, 0, 4), (192, 1, 5), (256, 2, 6)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_rsa_exponentiation {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_rsa_exponentiation { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_rsa_exponentiation!((512));
        _for_each_inner_rsa_exponentiation!((1024));
        _for_each_inner_rsa_exponentiation!((1536));
        _for_each_inner_rsa_exponentiation!((2048));
        _for_each_inner_rsa_exponentiation!((2560));
        _for_each_inner_rsa_exponentiation!((3072));
        _for_each_inner_rsa_exponentiation!((3584));
        _for_each_inner_rsa_exponentiation!((4096));
        _for_each_inner_rsa_exponentiation!((all(512), (1024), (1536), (2048), (2560),
        (3072), (3584), (4096)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_rsa_multiplication {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_rsa_multiplication { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_rsa_multiplication!((512));
        _for_each_inner_rsa_multiplication!((1024));
        _for_each_inner_rsa_multiplication!((1536));
        _for_each_inner_rsa_multiplication!((2048));
        _for_each_inner_rsa_multiplication!((all(512), (1024), (1536), (2048)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sha_algorithm {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sha_algorithm { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_sha_algorithm!((Sha1, "SHA-1"(sizes : 64, 20, 8)
        (insecure_against : "collision", "length extension"), 0));
        _for_each_inner_sha_algorithm!((Sha256, "SHA-256"(sizes : 64, 32, 8)
        (insecure_against : "length extension"), 0));
        _for_each_inner_sha_algorithm!((Sha384, "SHA-384"(sizes : 128, 48, 16)
        (insecure_against :), 0)); _for_each_inner_sha_algorithm!((Sha512,
        "SHA-512"(sizes : 128, 64, 16) (insecure_against : "length extension"), 0));
        _for_each_inner_sha_algorithm!((algos(Sha1, "SHA-1"(sizes : 64, 20, 8)
        (insecure_against : "collision", "length extension"), 0), (Sha256,
        "SHA-256"(sizes : 64, 32, 8) (insecure_against : "length extension"), 0),
        (Sha384, "SHA-384"(sizes : 128, 48, 16) (insecure_against :), 0), (Sha512,
        "SHA-512"(sizes : 128, 64, 16) (insecure_against : "length extension"), 0)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_wakeup_source {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_wakeup_source { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_wakeup_source!((Ext0, 0));
        _for_each_inner_wakeup_source!((Ext1, 1)); _for_each_inner_wakeup_source!((Gpio,
        2)); _for_each_inner_wakeup_source!((Timer, 3));
        _for_each_inner_wakeup_source!((Sdio, 4)); _for_each_inner_wakeup_source!((Wifi,
        5)); _for_each_inner_wakeup_source!((Uart0, 6));
        _for_each_inner_wakeup_source!((Uart1, 7));
        _for_each_inner_wakeup_source!((Touch, 8)); _for_each_inner_wakeup_source!((Ulp,
        9)); _for_each_inner_wakeup_source!((Bt, 10));
        _for_each_inner_wakeup_source!((all(Ext0, 0), (Ext1, 1), (Gpio, 2), (Timer, 3),
        (Sdio, 4), (Wifi, 5), (Uart0, 6), (Uart1, 7), (Touch, 8), (Ulp, 9), (Bt, 10)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_dma_engine!(("SPI_DMA"));
        _for_each_inner_dma_engine!(("I2S_DMA"));
        _for_each_inner_dma_engine!((all("SPI_DMA"), ("I2S_DMA")));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dma_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dma_channel { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_dma_channel!(("SPI_DMA", DMA_SPI2));
        _for_each_inner_dma_channel!(("SPI_DMA", DMA_SPI3));
        _for_each_inner_dma_channel!(("I2S_DMA", DMA_I2S0));
        _for_each_inner_dma_channel!(("I2S_DMA", DMA_I2S1));
        _for_each_inner_dma_channel!(("SPI_DMA", any_channel = SpiDmaChannel));
        _for_each_inner_dma_channel!(("I2S_DMA", any_channel = I2sDmaChannel));
        _for_each_inner_dma_channel!(("SPI_DMA", DMA_SPI2, 0, interrupt = SPI2_DMA,
        compatible = [SPI2])); _for_each_inner_dma_channel!(("SPI_DMA", DMA_SPI3, 1,
        interrupt = SPI3_DMA, compatible = [SPI3]));
        _for_each_inner_dma_channel!(("I2S_DMA", DMA_I2S0, 0, interrupt = I2S0,
        compatible = [I2S0])); _for_each_inner_dma_channel!(("I2S_DMA", DMA_I2S1, 1,
        interrupt = I2S1, compatible = [I2S1]));
        _for_each_inner_dma_channel!((names("SPI_DMA", DMA_SPI2), ("SPI_DMA", DMA_SPI3),
        ("I2S_DMA", DMA_I2S0), ("I2S_DMA", DMA_I2S1)));
        _for_each_inner_dma_channel!((separate_any_type("SPI_DMA", any_channel =
        SpiDmaChannel), ("I2S_DMA", any_channel = I2sDmaChannel)));
        _for_each_inner_dma_channel!((shared("SPI_DMA", DMA_SPI2, 0, interrupt =
        SPI2_DMA, compatible = [SPI2]), ("SPI_DMA", DMA_SPI3, 1, interrupt = SPI3_DMA,
        compatible = [SPI3]), ("I2S_DMA", DMA_I2S0, 0, interrupt = I2S0, compatible =
        [I2S0]), ("I2S_DMA", DMA_I2S1, 1, interrupt = I2S1, compatible = [I2S1])));
        _for_each_inner_dma_channel!((split));
        _for_each_inner_dma_channel!((no_own_interrupt));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dma_channel_peri_pair {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dma_channel_peri_pair { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_dma_channel_peri_pair!(("SPI_DMA",
        DMA_SPI2, SPI2)); _for_each_inner_dma_channel_peri_pair!(("SPI_DMA", DMA_SPI3,
        SPI3)); _for_each_inner_dma_channel_peri_pair!(("I2S_DMA", DMA_I2S0, I2S0));
        _for_each_inner_dma_channel_peri_pair!(("I2S_DMA", DMA_I2S1, I2S1));
        _for_each_inner_dma_channel_peri_pair!(("SPI_DMA", any_channel = SpiDmaChannel,
        SPI2)); _for_each_inner_dma_channel_peri_pair!(("SPI_DMA", any_channel =
        SpiDmaChannel, SPI3)); _for_each_inner_dma_channel_peri_pair!(("I2S_DMA",
        any_channel = I2sDmaChannel, I2S0));
        _for_each_inner_dma_channel_peri_pair!(("I2S_DMA", any_channel = I2sDmaChannel,
        I2S1)); _for_each_inner_dma_channel_peri_pair!((channels("SPI_DMA", DMA_SPI2,
        SPI2), ("SPI_DMA", DMA_SPI3, SPI3), ("I2S_DMA", DMA_I2S0, I2S0), ("I2S_DMA",
        DMA_I2S1, I2S1)));
        _for_each_inner_dma_channel_peri_pair!((any_channels("SPI_DMA", any_channel =
        SpiDmaChannel, SPI2), ("SPI_DMA", any_channel = SpiDmaChannel, SPI3), ("I2S_DMA",
        any_channel = I2sDmaChannel, I2S0), ("I2S_DMA", any_channel = I2sDmaChannel,
        I2S1)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_i2s_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_i2s_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _with_inner_i2s_dma_engine!(("I2S_DMA", I2sDmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_spi_master_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_spi_master_dma_engine { $(($pattern) => $code;)* ($other
        : tt) => {} } _with_inner_spi_master_dma_engine!(("SPI_DMA", SpiDmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_spi_slave_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_spi_slave_dma_engine { $(($pattern) => $code;)* ($other
        : tt) => {} } _with_inner_spi_slave_dma_engine!(("SPI_DMA", SpiDmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sw_interrupt {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sw_interrupt { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_sw_interrupt!((0, FROM_CPU_INTR0,
        software_interrupt0)); _for_each_inner_sw_interrupt!((1, FROM_CPU_INTR1,
        software_interrupt1)); _for_each_inner_sw_interrupt!((2, FROM_CPU_INTR2,
        software_interrupt2)); _for_each_inner_sw_interrupt!((3, FROM_CPU_INTR3,
        software_interrupt3)); _for_each_inner_sw_interrupt!((all(0, FROM_CPU_INTR0,
        software_interrupt0), (1, FROM_CPU_INTR1, software_interrupt1), (2,
        FROM_CPU_INTR2, software_interrupt2), (3, FROM_CPU_INTR3, software_interrupt3)));
    };
}
#[macro_export]
/// ESP-HAL must provide implementation for the following functions:
/// ```rust, no_run
/// // XTAL_CLK
///
/// fn configure_xtal_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<XtalClkConfig>,
///     _new_config: XtalClkConfig,
/// ) {
///     todo!()
/// }
///
/// // PLL_CLK
///
/// fn enable_pll_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_pll_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<PllClkConfig>,
///     _new_config: PllClkConfig,
/// ) {
///     todo!()
/// }
///
/// // APLL_CLK
///
/// fn enable_apll_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_apll_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<ApllClkConfig>,
///     _new_config: ApllClkConfig,
/// ) {
///     todo!()
/// }
///
/// // RC_FAST_CLK
///
/// fn enable_rc_fast_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_F160M_CLK
///
/// fn enable_pll_f160m_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_D2_CLK
///
/// fn enable_pll_d2_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // CPU_PLL_DIV_IN
///
/// fn enable_cpu_pll_div_in_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_cpu_pll_div_in_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CpuPllDivInConfig>,
///     _new_config: CpuPllDivInConfig,
/// ) {
///     todo!()
/// }
///
/// // CPU_PLL_DIV
///
/// fn enable_cpu_pll_div_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_cpu_pll_div_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CpuPllDivConfig>,
///     _new_config: CpuPllDivConfig,
/// ) {
///     todo!()
/// }
///
/// // SYSCON_PRE_DIV_IN
///
/// fn enable_syscon_pre_div_in_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_syscon_pre_div_in_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<SysconPreDivInConfig>,
///     _new_config: SysconPreDivInConfig,
/// ) {
///     todo!()
/// }
///
/// // SYSCON_PRE_DIV
///
/// fn enable_syscon_pre_div_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_syscon_pre_div_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<SysconPreDivConfig>,
///     _new_config: SysconPreDivConfig,
/// ) {
///     todo!()
/// }
///
/// // APB_CLK
///
/// fn enable_apb_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_apb_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<ApbClkConfig>,
///     _new_config: ApbClkConfig,
/// ) {
///     todo!()
/// }
///
/// // REF_TICK
///
/// fn enable_ref_tick_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_ref_tick_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RefTickConfig>,
///     _new_config: RefTickConfig,
/// ) {
///     todo!()
/// }
///
/// // REF_TICK_XTAL
///
/// fn enable_ref_tick_xtal_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_ref_tick_xtal_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RefTickXtalConfig>,
///     _new_config: RefTickXtalConfig,
/// ) {
///     todo!()
/// }
///
/// // REF_TICK_FOSC
///
/// fn enable_ref_tick_fosc_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_ref_tick_fosc_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RefTickFoscConfig>,
///     _new_config: RefTickFoscConfig,
/// ) {
///     todo!()
/// }
///
/// // REF_TICK_APLL
///
/// fn enable_ref_tick_apll_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_ref_tick_apll_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RefTickApllConfig>,
///     _new_config: RefTickApllConfig,
/// ) {
///     todo!()
/// }
///
/// // REF_TICK_PLL
///
/// fn enable_ref_tick_pll_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_ref_tick_pll_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RefTickPllConfig>,
///     _new_config: RefTickPllConfig,
/// ) {
///     todo!()
/// }
///
/// // CPU_CLK
///
/// fn configure_cpu_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CpuClkConfig>,
///     _new_config: CpuClkConfig,
/// ) {
///     todo!()
/// }
///
/// // APB_CLK_CPU_DIV2
///
/// fn enable_apb_clk_cpu_div2_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // APB_CLK_80M
///
/// fn enable_apb_clk_80m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // XTAL32K_CLK
///
/// #[cfg(use_xtal32k)]
/// fn enable_xtal32k_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RC_SLOW_CLK
///
/// fn enable_rc_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RC_FAST_DIV_CLK
///
/// fn enable_rc_fast_div_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // XTAL_DIV_CLK
///
/// fn enable_xtal_div_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RTC_SLOW_CLK
///
/// fn enable_rtc_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_rtc_slow_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RtcSlowClkConfig>,
///     _new_config: RtcSlowClkConfig,
/// ) {
///     todo!()
/// }
///
/// // BLE_LP_XTAL_CLK
///
/// fn enable_ble_lp_xtal_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // BLE_LP_CLK
///
/// fn enable_ble_lp_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_ble_lp_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<BleLpClkConfig>,
///     _new_config: BleLpClkConfig,
/// ) {
///     todo!()
/// }
///
/// // RTC_FAST_CLK
///
/// fn enable_rtc_fast_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_rtc_fast_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RtcFastClkConfig>,
///     _new_config: RtcFastClkConfig,
/// ) {
///     todo!()
/// }
///
/// // UART_MEM_CLK
///
/// fn enable_uart_mem_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // TIMG_CALIBRATION_CLOCK
///
/// fn enable_timg_calibration_clock_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_timg_calibration_clock_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<TimgCalibrationClockConfig>,
///     _new_config: TimgCalibrationClockConfig,
/// ) {
///     todo!()
/// }
///
/// impl SdmInstance {
///     // SDM_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
/// }
/// impl I2cInstance {
///     // I2C_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<I2cFunctionClockConfig>,
///         _new_config: I2cFunctionClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl I2sInstance {
///     // I2S_MCLK
///
///     fn enable_mclk_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_mclk_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<I2sMclkConfig>,
///         _new_config: I2sMclkConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl McpwmInstance {
///     // MCPWM_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
/// }
/// impl RmtInstance {
///     // RMT_SCLK
///
///     fn enable_sclk_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_sclk_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<RmtSclkConfig>,
///         _new_config: RmtSclkConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl SpiInstance {
///     // SPI_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
/// }
/// impl UartInstance {
///     // UART_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<UartFunctionClockConfig>,
///         _new_config: UartFunctionClockConfig,
///     ) {
///         todo!()
///     }
///
///     // UART_MEM_CLOCK
///
///     fn enable_mem_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     // UART_BAUD_RATE_GENERATOR
///
///     fn enable_baud_rate_generator_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_baud_rate_generator_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<UartBaudRateGeneratorConfig>,
///         _new_config: UartBaudRateGeneratorConfig,
///     ) {
///         todo!()
///     }
/// }
/// ```
macro_rules! define_clock_tree_types {
    () => {
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SdmInstance {
            GpioSd = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2cInstance {
            I2c0 = 0,
            I2c1 = 1,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2sInstance {
            I2s0 = 0,
            I2s1 = 1,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum McpwmInstance {
            Mcpwm0 = 0,
            Mcpwm1 = 1,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RmtInstance {
            Rmt = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SpiInstance {
            Spi2 = 0,
            Spi3 = 1,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum UartInstance {
            Uart0 = 0,
            Uart1 = 1,
            Uart2 = 2,
        }
        /// Selects the output frequency of `XTAL_CLK`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum XtalClkConfig {
            /// 26 MHz
            _26,
            /// 40 MHz
            _40,
        }
        impl XtalClkConfig {
            pub fn value(&self) -> u32 {
                match self {
                    XtalClkConfig::_26 => 26000000,
                    XtalClkConfig::_40 => 40000000,
                }
            }
        }
        /// Selects the output frequency of `PLL_CLK`. Depends on `XTAL_CLK`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum PllClkConfig {
            /// 320 MHz
            _320,
            /// 480 MHz
            _480,
        }
        impl PllClkConfig {
            pub fn value(&self) -> u32 {
                match self {
                    PllClkConfig::_320 => 320000000,
                    PllClkConfig::_480 => 480000000,
                }
            }
        }
        /// The target frequency of the `APLL_CLK` clock source. Depends on `PLL_CLK`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct ApllClkConfig(u32);
        impl ApllClkConfig {
            /// Creates a new clock source configuration.
            ///
            /// # Panics
            ///
            /// Panics if the output frequency value is outside the
            /// valid range (16 MHz - 128 MHz).
            pub const fn new(frequency: u32) -> Self {
                ::core::assert!(
                    frequency >= 16000000u32 && frequency <= 128000000u32,
                    "`APLL_CLK` output frequency value must be between 16000000 and 128000000 \
                     (inclusive)."
                );
                Self(frequency)
            }
        }
        impl ApllClkConfig {
            pub fn value(&self) -> u32 {
                self.0
            }
        }
        /// The list of clock signals that the `CPU_PLL_DIV_IN` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CpuPllDivInConfig {
            /// Selects `PLL_CLK`.
            Pll,
            /// Selects `APLL_CLK`.
            Apll,
        }
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CpuPllDivDivisor {
            /// Selects `divisor = 2`.
            _2 = 2,
            /// Selects `divisor = 4`.
            _4 = 4,
        }
        impl CpuPllDivDivisor {
            /// Creates a new parameter value from a raw number.
            pub const fn new(raw: u32) -> Self {
                match raw {
                    2 => Self::_2,
                    4 => Self::_4,
                    _ => ::core::panic!("Invalid CPU_PLL_DIV divisor value"),
                }
            }
        }
        /// Configures the `CPU_PLL_DIV` clock node.
        ///
        /// The output is calculated as `OUTPUT = CPU_PLL_DIV_IN / divisor`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct CpuPllDivConfig {
            divisor: CpuPllDivDivisor,
        }
        impl CpuPllDivConfig {
            /// Creates a new configuration for the CPU_PLL_DIV clock node.
            pub const fn new(divisor: CpuPllDivDivisor) -> Self {
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// The list of clock signals that the `SYSCON_PRE_DIV_IN` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SysconPreDivInConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
        }
        /// Configures the `SYSCON_PRE_DIV` clock node.
        ///
        /// The output is calculated as `OUTPUT = SYSCON_PRE_DIV_IN / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct SysconPreDivConfig {
            divisor: u32,
        }
        impl SysconPreDivConfig {
            /// Creates a new configuration for the SYSCON_PRE_DIV clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 1023).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 1023,
                    "`SYSCON_PRE_DIV` divisor must be between 0 and 1023 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// The list of clock signals that the `APB_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum ApbClkConfig {
            /// Selects `APB_CLK_80M`.
            Pll80m,
            /// Selects `APB_CLK_CPU_DIV2`.
            CpuDiv2,
            /// Selects `CPU_CLK`.
            Cpu,
        }
        /// The list of clock signals that the `REF_TICK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RefTickConfig {
            /// Selects `REF_TICK_PLL`.
            Pll,
            /// Selects `REF_TICK_APLL`.
            Apll,
            /// Selects `REF_TICK_XTAL`.
            Xtal,
            /// Selects `REF_TICK_FOSC`.
            Fosc,
        }
        /// Configures the `REF_TICK_XTAL` clock node.
        ///
        /// The output is calculated as `OUTPUT = APB_CLK / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct RefTickXtalConfig {
            divisor: u32,
        }
        impl RefTickXtalConfig {
            /// Creates a new configuration for the REF_TICK_XTAL clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 255,
                    "`REF_TICK_XTAL` divisor must be between 0 and 255 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// Configures the `REF_TICK_FOSC` clock node.
        ///
        /// The output is calculated as `OUTPUT = APB_CLK / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct RefTickFoscConfig {
            divisor: u32,
        }
        impl RefTickFoscConfig {
            /// Creates a new configuration for the REF_TICK_FOSC clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 255,
                    "`REF_TICK_FOSC` divisor must be between 0 and 255 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// Configures the `REF_TICK_APLL` clock node.
        ///
        /// The output is calculated as `OUTPUT = APB_CLK / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct RefTickApllConfig {
            divisor: u32,
        }
        impl RefTickApllConfig {
            /// Creates a new configuration for the REF_TICK_APLL clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 255,
                    "`REF_TICK_APLL` divisor must be between 0 and 255 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// Configures the `REF_TICK_PLL` clock node.
        ///
        /// The output is calculated as `OUTPUT = APB_CLK / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct RefTickPllConfig {
            divisor: u32,
        }
        impl RefTickPllConfig {
            /// Creates a new configuration for the REF_TICK_PLL clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 255,
                    "`REF_TICK_PLL` divisor must be between 0 and 255 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// The list of clock signals that the `CPU_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CpuClkConfig {
            /// Selects `SYSCON_PRE_DIV`.
            Xtal,
            /// Selects `SYSCON_PRE_DIV`.
            RcFast,
            /// Selects `CPU_PLL_DIV`.
            Apll,
            /// Selects `CPU_PLL_DIV`.
            Pll,
        }
        /// The list of clock signals that the `RTC_SLOW_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RtcSlowClkConfig {
            #[cfg(use_xtal32k)]
            /// Selects `XTAL32K_CLK`.
            Xtal32k,
            /// Selects `RC_SLOW_CLK`.
            RcSlow,
            /// Selects `RC_FAST_DIV_CLK`.
            RcFast,
        }
        /// The list of clock signals that the `BLE_LP_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum BleLpClkConfig {
            /// Selects `BLE_LP_XTAL_CLK`.
            Xtal,
            /// Selects `RTC_SLOW_CLK`.
            RtcSlow,
        }
        /// The list of clock signals that the `RTC_FAST_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RtcFastClkConfig {
            /// Selects `XTAL_DIV_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            Rc,
        }
        /// The list of clock signals that the `UART_MEM_CLK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum UartMemClkConfig {
            #[default]
            /// Selects `XTAL_CLK`.
            Xtal,
        }
        /// The list of clock signals that the `TIMG_CALIBRATION_CLOCK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgCalibrationClockConfig {
            /// Selects `RC_SLOW_CLK`.
            RcSlowClk,
            /// Selects `RC_FAST_DIV_CLK`.
            RcFastDivClk,
            #[cfg(use_xtal32k)]
            /// Selects `XTAL32K_CLK`.
            Xtal32kClk,
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2cFunctionClockSclk {
            #[default]
            /// Selects `APB_CLK`.
            Apb,
        }
        /// Configures the `I2C0_FUNCTION_CLOCK` clock node.
        ///
        /// The output is calculated as `OUTPUT = sclk`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct I2cFunctionClockConfig {
            sclk: I2cFunctionClockSclk,
        }
        impl I2cFunctionClockConfig {
            /// Creates a new configuration for the FUNCTION_CLOCK clock node.
            pub const fn new(sclk: I2cFunctionClockSclk) -> Self {
                Self { sclk }
            }
            pub fn sclk(self) -> I2cFunctionClockSclk {
                self.sclk
            }
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2sMclkSclk {
            #[default]
            /// Selects `PLL_F160M_CLK`.
            PllF160m,
            /// Selects `APLL_CLK`.
            Apll,
        }
        /// Configures the `I2S0_MCLK` clock node.
        ///
        /// The output is calculated as `OUTPUT = (sclk * div_a) / (div_num * div_a + div_b)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct I2sMclkConfig {
            sclk: I2sMclkSclk,
            div_num: u32,
            div_a: u32,
            div_b: u32,
        }
        impl I2sMclkConfig {
            /// Creates a new configuration for the MCLK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (1 ..= 255).
            ///
            /// Panics if the div_a value is outside the
            /// valid range (1 ..= 63).
            ///
            /// Panics if the div_b value is outside the
            /// valid range (0 ..= 63).
            pub const fn new(sclk: I2sMclkSclk, div_num: u32, div_a: u32, div_b: u32) -> Self {
                ::core::assert!(
                    div_num >= 1 && div_num <= 255,
                    "`I2S0_MCLK` div_num must be between 1 and 255 (inclusive)."
                );
                ::core::assert!(
                    div_a >= 1 && div_a <= 63,
                    "`I2S0_MCLK` div_a must be between 1 and 63 (inclusive)."
                );
                ::core::assert!(
                    div_b <= 63,
                    "`I2S0_MCLK` div_b must be between 0 and 63 (inclusive)."
                );
                Self {
                    sclk,
                    div_num,
                    div_a,
                    div_b,
                }
            }
            pub fn sclk(self) -> I2sMclkSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
            pub fn div_a(self) -> u32 {
                self.div_a as u32
            }
            pub fn div_b(self) -> u32 {
                self.div_b as u32
            }
        }
        /// The list of clock signals that the `MCPWM0_FUNCTION_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum McpwmFunctionClockConfig {
            #[default]
            /// Selects `PLL_F160M_CLK`.
            PllF160m,
        }
        /// The list of clock signals that the `RMT_SCLK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RmtSclkConfig {
            /// Selects `REF_TICK`.
            RefTick,
            #[default]
            /// Selects `APB_CLK`.
            ApbClk,
        }
        /// The list of clock signals that the `SPI2_FUNCTION_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SpiFunctionClockConfig {
            #[default]
            /// Selects `APB_CLK`.
            Apb,
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum UartFunctionClockSclk {
            #[default]
            /// Selects `APB_CLK`.
            Apb,
            /// Selects `REF_TICK`.
            RefTick,
        }
        /// Configures the `UART0_FUNCTION_CLOCK` clock node.
        ///
        /// The output is calculated as `OUTPUT = sclk`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct UartFunctionClockConfig {
            sclk: UartFunctionClockSclk,
        }
        impl UartFunctionClockConfig {
            /// Creates a new configuration for the FUNCTION_CLOCK clock node.
            pub const fn new(sclk: UartFunctionClockSclk) -> Self {
                Self { sclk }
            }
            pub fn sclk(self) -> UartFunctionClockSclk {
                self.sclk
            }
        }
        /// Configures the `UART0_BAUD_RATE_GENERATOR` clock node.
        ///
        /// The output is calculated as `OUTPUT = (FUNCTION_CLOCK * 16) / (integral * 16 +
        /// fractional)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct UartBaudRateGeneratorConfig {
            fractional: u32,
            integral: u32,
        }
        impl UartBaudRateGeneratorConfig {
            /// Creates a new configuration for the BAUD_RATE_GENERATOR clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the fractional value is outside the
            /// valid range (0 ..= 15).
            ///
            /// Panics if the integral value is outside the
            /// valid range (0 ..= 1048575).
            pub const fn new(fractional: u32, integral: u32) -> Self {
                ::core::assert!(
                    fractional <= 15,
                    "`UART0_BAUD_RATE_GENERATOR` fractional must be between 0 and 15 (inclusive)."
                );
                ::core::assert!(
                    integral <= 1048575,
                    "`UART0_BAUD_RATE_GENERATOR` integral must be between 0 and 1048575 \
                     (inclusive)."
                );
                Self {
                    fractional,
                    integral,
                }
            }
            pub fn fractional(self) -> u32 {
                self.fractional as u32
            }
            pub fn integral(self) -> u32 {
                self.integral as u32
            }
        }
        /// Represents the device's clock tree.
        pub struct ClockTree {
            xtal_clk: Option<XtalClkConfig>,
            pll_clk: Option<PllClkConfig>,
            apll_clk: Option<ApllClkConfig>,
            cpu_pll_div_in: Option<CpuPllDivInConfig>,
            cpu_pll_div: Option<CpuPllDivConfig>,
            syscon_pre_div_in: Option<SysconPreDivInConfig>,
            syscon_pre_div: Option<SysconPreDivConfig>,
            apb_clk: Option<ApbClkConfig>,
            ref_tick: Option<RefTickConfig>,
            ref_tick_xtal: Option<RefTickXtalConfig>,
            ref_tick_fosc: Option<RefTickFoscConfig>,
            ref_tick_apll: Option<RefTickApllConfig>,
            ref_tick_pll: Option<RefTickPllConfig>,
            cpu_clk: Option<CpuClkConfig>,
            rtc_slow_clk: Option<RtcSlowClkConfig>,
            ble_lp_clk: Option<BleLpClkConfig>,
            rtc_fast_clk: Option<RtcFastClkConfig>,
            timg_calibration_clock: Option<TimgCalibrationClockConfig>,
            i2c_function_clock: [Option<I2cFunctionClockConfig>; 2],
            i2s_mclk: [Option<I2sMclkConfig>; 2],
            rmt_sclk: [Option<RmtSclkConfig>; 1],
            uart_function_clock: [Option<UartFunctionClockConfig>; 3],
            uart_baud_rate_generator: [Option<UartBaudRateGeneratorConfig>; 3],
            pll_clk_refcount: u32,
            apll_clk_refcount: u32,
            rc_fast_clk_refcount: u32,
            pll_f160m_clk_refcount: u32,
            pll_d2_clk_refcount: u32,
            apb_clk_refcount: u32,
            ref_tick_refcount: u32,
            #[cfg(use_xtal32k)]
            xtal32k_clk_refcount: u32,
            rc_slow_clk_refcount: u32,
            rc_fast_div_clk_refcount: u32,
            ble_lp_clk_refcount: u32,
            rtc_fast_clk_refcount: u32,
            uart_mem_clk_refcount: u32,
            timg_calibration_clock_refcount: u32,
            sdm_function_clock_refcount: [u32; 1],
            i2c_function_clock_refcount: [u32; 2],
            i2s_mclk_refcount: [u32; 2],
            mcpwm_function_clock_refcount: [u32; 2],
            rmt_sclk_refcount: [u32; 1],
            spi_function_clock_refcount: [u32; 2],
            uart_function_clock_refcount: [u32; 3],
            uart_mem_clock_refcount: [u32; 3],
            uart_baud_rate_generator_refcount: [u32; 3],
        }
        impl ClockTree {
            /// Locks the clock tree for exclusive access.
            pub fn with<R>(f: impl FnOnce(&mut ClockTree) -> R) -> R {
                CLOCK_TREE.with(f)
            }
            /// Returns the current configuration of the XTAL_CLK clock tree node
            pub fn xtal_clk(&self) -> Option<XtalClkConfig> {
                self.xtal_clk
            }
            /// Returns the current configuration of the PLL_CLK clock tree node
            pub fn pll_clk(&self) -> Option<PllClkConfig> {
                self.pll_clk
            }
            /// Returns the current configuration of the APLL_CLK clock tree node
            pub fn apll_clk(&self) -> Option<ApllClkConfig> {
                self.apll_clk
            }
            /// Returns the current configuration of the CPU_PLL_DIV_IN clock tree node
            pub fn cpu_pll_div_in(&self) -> Option<CpuPllDivInConfig> {
                self.cpu_pll_div_in
            }
            /// Returns the current configuration of the CPU_PLL_DIV clock tree node
            pub fn cpu_pll_div(&self) -> Option<CpuPllDivConfig> {
                self.cpu_pll_div
            }
            /// Returns the current configuration of the SYSCON_PRE_DIV_IN clock tree node
            pub fn syscon_pre_div_in(&self) -> Option<SysconPreDivInConfig> {
                self.syscon_pre_div_in
            }
            /// Returns the current configuration of the SYSCON_PRE_DIV clock tree node
            pub fn syscon_pre_div(&self) -> Option<SysconPreDivConfig> {
                self.syscon_pre_div
            }
            /// Returns the current configuration of the APB_CLK clock tree node
            pub fn apb_clk(&self) -> Option<ApbClkConfig> {
                self.apb_clk
            }
            /// Returns the current configuration of the REF_TICK clock tree node
            pub fn ref_tick(&self) -> Option<RefTickConfig> {
                self.ref_tick
            }
            /// Returns the current configuration of the REF_TICK_XTAL clock tree node
            pub fn ref_tick_xtal(&self) -> Option<RefTickXtalConfig> {
                self.ref_tick_xtal
            }
            /// Returns the current configuration of the REF_TICK_FOSC clock tree node
            pub fn ref_tick_fosc(&self) -> Option<RefTickFoscConfig> {
                self.ref_tick_fosc
            }
            /// Returns the current configuration of the REF_TICK_APLL clock tree node
            pub fn ref_tick_apll(&self) -> Option<RefTickApllConfig> {
                self.ref_tick_apll
            }
            /// Returns the current configuration of the REF_TICK_PLL clock tree node
            pub fn ref_tick_pll(&self) -> Option<RefTickPllConfig> {
                self.ref_tick_pll
            }
            /// Returns the current configuration of the CPU_CLK clock tree node
            pub fn cpu_clk(&self) -> Option<CpuClkConfig> {
                self.cpu_clk
            }
            /// Returns the current configuration of the RTC_SLOW_CLK clock tree node
            pub fn rtc_slow_clk(&self) -> Option<RtcSlowClkConfig> {
                self.rtc_slow_clk
            }
            /// Returns the current configuration of the BLE_LP_CLK clock tree node
            pub fn ble_lp_clk(&self) -> Option<BleLpClkConfig> {
                self.ble_lp_clk
            }
            /// Returns the current configuration of the RTC_FAST_CLK clock tree node
            pub fn rtc_fast_clk(&self) -> Option<RtcFastClkConfig> {
                self.rtc_fast_clk
            }
            /// Returns the current configuration of the TIMG_CALIBRATION_CLOCK clock tree node
            pub fn timg_calibration_clock(&self) -> Option<TimgCalibrationClockConfig> {
                self.timg_calibration_clock
            }
            /// Returns the current configuration of the I2C0_FUNCTION_CLOCK clock tree node
            pub fn i2c0_function_clock(&self) -> Option<I2cFunctionClockConfig> {
                self.i2c_function_clock[I2cInstance::I2c0 as usize]
            }
            /// Returns the current configuration of the I2C1_FUNCTION_CLOCK clock tree node
            pub fn i2c1_function_clock(&self) -> Option<I2cFunctionClockConfig> {
                self.i2c_function_clock[I2cInstance::I2c1 as usize]
            }
            /// Returns the current configuration of the I2S0_MCLK clock tree node
            pub fn i2s0_mclk(&self) -> Option<I2sMclkConfig> {
                self.i2s_mclk[I2sInstance::I2s0 as usize]
            }
            /// Returns the current configuration of the I2S1_MCLK clock tree node
            pub fn i2s1_mclk(&self) -> Option<I2sMclkConfig> {
                self.i2s_mclk[I2sInstance::I2s1 as usize]
            }
            /// Returns the current configuration of the RMT_SCLK clock tree node
            pub fn rmt_sclk(&self) -> Option<RmtSclkConfig> {
                self.rmt_sclk[RmtInstance::Rmt as usize]
            }
            /// Returns the current configuration of the UART0_FUNCTION_CLOCK clock tree node
            pub fn uart0_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart0 as usize]
            }
            /// Returns the current configuration of the UART0_BAUD_RATE_GENERATOR clock tree node
            pub fn uart0_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart0 as usize]
            }
            /// Returns the current configuration of the UART1_FUNCTION_CLOCK clock tree node
            pub fn uart1_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart1 as usize]
            }
            /// Returns the current configuration of the UART1_BAUD_RATE_GENERATOR clock tree node
            pub fn uart1_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart1 as usize]
            }
            /// Returns the current configuration of the UART2_FUNCTION_CLOCK clock tree node
            pub fn uart2_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart2 as usize]
            }
            /// Returns the current configuration of the UART2_BAUD_RATE_GENERATOR clock tree node
            pub fn uart2_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart2 as usize]
            }
        }
        static CLOCK_TREE: ::esp_sync::NonReentrantMutex<ClockTree> =
            ::esp_sync::NonReentrantMutex::new(ClockTree {
                xtal_clk: None,
                pll_clk: None,
                apll_clk: None,
                cpu_pll_div_in: None,
                cpu_pll_div: None,
                syscon_pre_div_in: None,
                syscon_pre_div: None,
                apb_clk: None,
                ref_tick: None,
                ref_tick_xtal: None,
                ref_tick_fosc: None,
                ref_tick_apll: None,
                ref_tick_pll: None,
                cpu_clk: None,
                rtc_slow_clk: None,
                ble_lp_clk: None,
                rtc_fast_clk: None,
                timg_calibration_clock: None,
                i2c_function_clock: [None; 2],
                i2s_mclk: [None; 2],
                rmt_sclk: [None; 1],
                uart_function_clock: [None; 3],
                uart_baud_rate_generator: [None; 3],
                pll_clk_refcount: 0,
                apll_clk_refcount: 0,
                rc_fast_clk_refcount: 0,
                pll_f160m_clk_refcount: 0,
                pll_d2_clk_refcount: 0,
                apb_clk_refcount: 0,
                ref_tick_refcount: 0,
                #[cfg(use_xtal32k)]
                xtal32k_clk_refcount: 0,
                rc_slow_clk_refcount: 0,
                rc_fast_div_clk_refcount: 0,
                ble_lp_clk_refcount: 0,
                rtc_fast_clk_refcount: 0,
                uart_mem_clk_refcount: 0,
                timg_calibration_clock_refcount: 0,
                sdm_function_clock_refcount: [0; 1],
                i2c_function_clock_refcount: [0; 2],
                i2s_mclk_refcount: [0; 2],
                mcpwm_function_clock_refcount: [0; 2],
                rmt_sclk_refcount: [0; 1],
                spi_function_clock_refcount: [0; 2],
                uart_function_clock_refcount: [0; 3],
                uart_mem_clock_refcount: [0; 3],
                uart_baud_rate_generator_refcount: [0; 3],
            });
        static XTAL_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static PLL_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static APLL_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static CPU_PLL_DIV_IN_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static CPU_PLL_DIV_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static SYSCON_PRE_DIV_IN_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static SYSCON_PRE_DIV_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static CPU_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static RTC_SLOW_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static BLE_LP_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static RTC_FAST_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static TIMG_CALIBRATION_CLOCK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static I2S_MCLK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 2];
        static APB_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static REF_TICK_XTAL_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static REF_TICK_FOSC_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static REF_TICK_APLL_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static REF_TICK_PLL_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static REF_TICK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static RMT_SCLK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static UART_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 3] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 3];
        static UART_BAUD_RATE_GENERATOR_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 3] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 3];
        /// The clock sources of the device.
        ///
        /// A clock source is a node of the clock tree that other nodes derive their output
        /// from. Ask a node which source it runs on with its `..._root_source` function.
        #[derive(Debug, enumset::EnumSetType)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum ClockSource {
            /// `XTAL_CLK`.
            XtalClk,
            /// `RC_FAST_CLK`.
            RcFastClk,
            #[cfg(use_xtal32k)]
            /// `XTAL32K_CLK`.
            Xtal32kClk,
            /// `RC_SLOW_CLK`.
            RcSlowClk,
        }
        /// Returns the clock source that `XTAL_CLK` currently runs on.
        pub fn xtal_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::XtalClk)
        }
        /// Returns the clock source that `PLL_CLK` currently runs on.
        pub fn pll_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `APLL_CLK` currently runs on.
        pub fn apll_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            pll_clk_root_source(clocks)
        }
        /// Returns the clock source that `RC_FAST_CLK` currently runs on.
        pub fn rc_fast_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::RcFastClk)
        }
        /// Returns the clock source that `PLL_F160M_CLK` currently runs on.
        pub fn pll_f160m_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            pll_clk_root_source(clocks)
        }
        /// Returns the clock source that `PLL_D2_CLK` currently runs on.
        pub fn pll_d2_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            pll_clk_root_source(clocks)
        }
        /// Returns the clock source that `CPU_PLL_DIV_IN` currently runs on.
        pub fn cpu_pll_div_in_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.cpu_pll_div_in?;
            match config {
                CpuPllDivInConfig::Pll => pll_clk_root_source(clocks),
                CpuPllDivInConfig::Apll => apll_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `CPU_PLL_DIV` currently runs on.
        pub fn cpu_pll_div_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            cpu_pll_div_in_root_source(clocks)
        }
        /// Returns the clock source that `SYSCON_PRE_DIV_IN` currently runs on.
        pub fn syscon_pre_div_in_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.syscon_pre_div_in?;
            match config {
                SysconPreDivInConfig::Xtal => xtal_clk_root_source(clocks),
                SysconPreDivInConfig::RcFast => rc_fast_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `SYSCON_PRE_DIV` currently runs on.
        pub fn syscon_pre_div_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            syscon_pre_div_in_root_source(clocks)
        }
        /// Returns the clock source that `CPU_CLK` currently runs on.
        pub fn cpu_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.cpu_clk?;
            match config {
                CpuClkConfig::Xtal => syscon_pre_div_root_source(clocks),
                CpuClkConfig::RcFast => syscon_pre_div_root_source(clocks),
                CpuClkConfig::Apll => cpu_pll_div_root_source(clocks),
                CpuClkConfig::Pll => cpu_pll_div_root_source(clocks),
            }
        }
        /// Returns the clock source that `APB_CLK_CPU_DIV2` currently runs on.
        pub fn apb_clk_cpu_div2_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            cpu_clk_root_source(clocks)
        }
        /// Returns the clock source that `APB_CLK_80M` currently runs on.
        pub fn apb_clk_80m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            cpu_clk_root_source(clocks)
        }
        #[cfg(use_xtal32k)]
        /// Returns the clock source that `XTAL32K_CLK` currently runs on.
        pub fn xtal32k_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::Xtal32kClk)
        }
        /// Returns the clock source that `RC_SLOW_CLK` currently runs on.
        pub fn rc_slow_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::RcSlowClk)
        }
        /// Returns the clock source that `RC_FAST_DIV_CLK` currently runs on.
        pub fn rc_fast_div_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            rc_fast_clk_root_source(clocks)
        }
        /// Returns the clock source that `XTAL_DIV_CLK` currently runs on.
        pub fn xtal_div_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `RTC_SLOW_CLK` currently runs on.
        pub fn rtc_slow_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.rtc_slow_clk?;
            match config {
                #[cfg(use_xtal32k)]
                RtcSlowClkConfig::Xtal32k => xtal32k_clk_root_source(clocks),
                RtcSlowClkConfig::RcSlow => rc_slow_clk_root_source(clocks),
                RtcSlowClkConfig::RcFast => rc_fast_div_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `BLE_LP_XTAL_CLK` currently runs on.
        pub fn ble_lp_xtal_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `BLE_LP_CLK` currently runs on.
        pub fn ble_lp_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.ble_lp_clk?;
            match config {
                BleLpClkConfig::Xtal => ble_lp_xtal_clk_root_source(clocks),
                BleLpClkConfig::RtcSlow => rtc_slow_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `RTC_FAST_CLK` currently runs on.
        pub fn rtc_fast_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.rtc_fast_clk?;
            match config {
                RtcFastClkConfig::Xtal => xtal_div_clk_root_source(clocks),
                RtcFastClkConfig::Rc => rc_fast_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `UART_MEM_CLK` currently runs on.
        pub fn uart_mem_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `TIMG_CALIBRATION_CLOCK` currently runs on.
        pub fn timg_calibration_clock_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.timg_calibration_clock?;
            match config {
                TimgCalibrationClockConfig::RcSlowClk => rc_slow_clk_root_source(clocks),
                TimgCalibrationClockConfig::RcFastDivClk => rc_fast_div_clk_root_source(clocks),
                #[cfg(use_xtal32k)]
                TimgCalibrationClockConfig::Xtal32kClk => xtal32k_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `APB_CLK` currently runs on.
        pub fn apb_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.apb_clk?;
            match config {
                ApbClkConfig::Pll80m => apb_clk_80m_root_source(clocks),
                ApbClkConfig::CpuDiv2 => apb_clk_cpu_div2_root_source(clocks),
                ApbClkConfig::Cpu => cpu_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `REF_TICK_XTAL` currently runs on.
        pub fn ref_tick_xtal_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            apb_clk_root_source(clocks)
        }
        /// Returns the clock source that `REF_TICK_FOSC` currently runs on.
        pub fn ref_tick_fosc_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            apb_clk_root_source(clocks)
        }
        /// Returns the clock source that `REF_TICK_APLL` currently runs on.
        pub fn ref_tick_apll_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            apb_clk_root_source(clocks)
        }
        /// Returns the clock source that `REF_TICK_PLL` currently runs on.
        pub fn ref_tick_pll_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            apb_clk_root_source(clocks)
        }
        /// Returns the clock source that `REF_TICK` currently runs on.
        pub fn ref_tick_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.ref_tick?;
            match config {
                RefTickConfig::Pll => ref_tick_pll_root_source(clocks),
                RefTickConfig::Apll => ref_tick_apll_root_source(clocks),
                RefTickConfig::Xtal => ref_tick_xtal_root_source(clocks),
                RefTickConfig::Fosc => ref_tick_fosc_root_source(clocks),
            }
        }
        pub fn configure_xtal_clk(clocks: &mut ClockTree, config: XtalClkConfig) {
            let old_config = clocks.xtal_clk.replace(config);
            refresh_xtal_clk_downstream(clocks);
            configure_xtal_clk_impl(clocks, old_config, config);
        }
        pub fn xtal_clk_config(clocks: &mut ClockTree) -> Option<XtalClkConfig> {
            clocks.xtal_clk
        }
        fn request_xtal_clk(_clocks: &mut ClockTree) {}
        fn release_xtal_clk(_clocks: &mut ClockTree) {}
        pub fn xtal_clk_config_frequency(config: XtalClkConfig) -> u32 {
            config.value()
        }
        pub fn xtal_clk_frequency() -> u32 {
            XTAL_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn configure_pll_clk(clocks: &mut ClockTree, config: PllClkConfig) {
            if clocks.cpu_pll_div.is_some() {
                assert!(
                    !((config.value() == 480000000)
                        && (unwrap!(clocks.cpu_pll_div).divisor() == 4))
                );
            }
            let old_config = clocks.pll_clk.replace(config);
            refresh_pll_clk_downstream(clocks);
            configure_pll_clk_impl(clocks, old_config, config);
        }
        pub fn pll_clk_config(clocks: &mut ClockTree) -> Option<PllClkConfig> {
            clocks.pll_clk
        }
        pub fn request_pll_clk(clocks: &mut ClockTree) {
            trace!("Requesting PLL_CLK");
            if increment_reference_count(&mut clocks.pll_clk_refcount) {
                trace!("Enabling PLL_CLK");
                request_xtal_clk(clocks);
                enable_pll_clk_impl(clocks, true);
            }
        }
        pub fn release_pll_clk(clocks: &mut ClockTree) {
            trace!("Releasing PLL_CLK");
            if decrement_reference_count(&mut clocks.pll_clk_refcount) {
                trace!("Disabling PLL_CLK");
                enable_pll_clk_impl(clocks, false);
                release_xtal_clk(clocks);
            }
        }
        pub fn pll_clk_config_frequency(config: PllClkConfig) -> u32 {
            config.value()
        }
        pub fn pll_clk_frequency() -> u32 {
            PLL_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn pll_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn configure_apll_clk(clocks: &mut ClockTree, config: ApllClkConfig) {
            let old_config = clocks.apll_clk.replace(config);
            refresh_apll_clk_downstream(clocks);
            configure_apll_clk_impl(clocks, old_config, config);
        }
        pub fn apll_clk_config(clocks: &mut ClockTree) -> Option<ApllClkConfig> {
            clocks.apll_clk
        }
        pub fn request_apll_clk(clocks: &mut ClockTree) {
            trace!("Requesting APLL_CLK");
            if increment_reference_count(&mut clocks.apll_clk_refcount) {
                trace!("Enabling APLL_CLK");
                request_pll_clk(clocks);
                enable_apll_clk_impl(clocks, true);
            }
        }
        pub fn release_apll_clk(clocks: &mut ClockTree) {
            trace!("Releasing APLL_CLK");
            if decrement_reference_count(&mut clocks.apll_clk_refcount) {
                trace!("Disabling APLL_CLK");
                enable_apll_clk_impl(clocks, false);
                release_pll_clk(clocks);
            }
        }
        pub fn apll_clk_config_frequency(config: ApllClkConfig) -> u32 {
            config.value()
        }
        pub fn apll_clk_frequency() -> u32 {
            APLL_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn apll_clk_source_frequency() -> u32 {
            pll_clk_frequency()
        }
        pub fn request_rc_fast_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC_FAST_CLK");
            if increment_reference_count(&mut clocks.rc_fast_clk_refcount) {
                trace!("Enabling RC_FAST_CLK");
                enable_rc_fast_clk_impl(clocks, true);
            }
        }
        pub fn release_rc_fast_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC_FAST_CLK");
            if decrement_reference_count(&mut clocks.rc_fast_clk_refcount) {
                trace!("Disabling RC_FAST_CLK");
                enable_rc_fast_clk_impl(clocks, false);
            }
        }
        static RC_FAST_CLK_FREQUENCY: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(rc_fast_clk_nominal_frequency());
        pub const fn rc_fast_clk_nominal_frequency() -> u32 {
            8000000
        }
        pub fn rc_fast_clk_frequency() -> u32 {
            RC_FAST_CLK_FREQUENCY.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn set_rc_fast_clk_frequency(clocks: &mut ClockTree, frequency: u32) {
            if !(4000000..=12000000).contains(&frequency) {
                warn!(
                    "Ignoring out-of-range RC_FAST_CLK frequency: {} Hz",
                    frequency
                );
                return;
            }
            debug!(
                "Updating RC_FAST_CLK frequency to {} Hz (nominal {} Hz)",
                frequency,
                rc_fast_clk_nominal_frequency()
            );
            RC_FAST_CLK_FREQUENCY.store(frequency, ::core::sync::atomic::Ordering::Release);
            refresh_rc_fast_clk_downstream(clocks);
        }
        pub fn request_pll_f160m_clk(clocks: &mut ClockTree) {
            trace!("Requesting PLL_F160M_CLK");
            if increment_reference_count(&mut clocks.pll_f160m_clk_refcount) {
                trace!("Enabling PLL_F160M_CLK");
                request_pll_clk(clocks);
                enable_pll_f160m_clk_impl(clocks, true);
            }
        }
        pub fn release_pll_f160m_clk(clocks: &mut ClockTree) {
            trace!("Releasing PLL_F160M_CLK");
            if decrement_reference_count(&mut clocks.pll_f160m_clk_refcount) {
                trace!("Disabling PLL_F160M_CLK");
                enable_pll_f160m_clk_impl(clocks, false);
                release_pll_clk(clocks);
            }
        }
        pub fn pll_f160m_clk_frequency() -> u32 {
            160000000
        }
        pub fn pll_f160m_clk_source_frequency() -> u32 {
            pll_clk_frequency()
        }
        pub fn request_pll_d2_clk(clocks: &mut ClockTree) {
            trace!("Requesting PLL_D2_CLK");
            if increment_reference_count(&mut clocks.pll_d2_clk_refcount) {
                trace!("Enabling PLL_D2_CLK");
                request_pll_clk(clocks);
                enable_pll_d2_clk_impl(clocks, true);
            }
        }
        pub fn release_pll_d2_clk(clocks: &mut ClockTree) {
            trace!("Releasing PLL_D2_CLK");
            if decrement_reference_count(&mut clocks.pll_d2_clk_refcount) {
                trace!("Disabling PLL_D2_CLK");
                enable_pll_d2_clk_impl(clocks, false);
                release_pll_clk(clocks);
            }
        }
        pub fn pll_d2_clk_frequency() -> u32 {
            (pll_clk_frequency() / 2)
        }
        pub fn pll_d2_clk_source_frequency() -> u32 {
            pll_clk_frequency()
        }
        pub fn configure_cpu_pll_div_in(clocks: &mut ClockTree, new_selector: CpuPllDivInConfig) {
            let old_selector = clocks.cpu_pll_div_in.replace(new_selector);
            refresh_cpu_pll_div_in_downstream(clocks);
            match new_selector {
                CpuPllDivInConfig::Pll => request_pll_clk(clocks),
                CpuPllDivInConfig::Apll => request_apll_clk(clocks),
            }
            configure_cpu_pll_div_in_impl(clocks, old_selector, new_selector);
            if let Some(old_selector) = old_selector {
                match old_selector {
                    CpuPllDivInConfig::Pll => release_pll_clk(clocks),
                    CpuPllDivInConfig::Apll => release_apll_clk(clocks),
                }
            }
        }
        pub fn cpu_pll_div_in_config(clocks: &mut ClockTree) -> Option<CpuPllDivInConfig> {
            clocks.cpu_pll_div_in
        }
        pub fn request_cpu_pll_div_in(clocks: &mut ClockTree) {
            trace!("Enabling CPU_PLL_DIV_IN");
            match unwrap!(clocks.cpu_pll_div_in) {
                CpuPllDivInConfig::Pll => request_pll_clk(clocks),
                CpuPllDivInConfig::Apll => request_apll_clk(clocks),
            }
            enable_cpu_pll_div_in_impl(clocks, true);
        }
        pub fn release_cpu_pll_div_in(clocks: &mut ClockTree) {
            trace!("Disabling CPU_PLL_DIV_IN");
            enable_cpu_pll_div_in_impl(clocks, false);
            match unwrap!(clocks.cpu_pll_div_in) {
                CpuPllDivInConfig::Pll => release_pll_clk(clocks),
                CpuPllDivInConfig::Apll => release_apll_clk(clocks),
            }
        }
        pub fn cpu_pll_div_in_config_frequency(config: CpuPllDivInConfig) -> u32 {
            match config {
                CpuPllDivInConfig::Pll => pll_clk_frequency(),
                CpuPllDivInConfig::Apll => apll_clk_frequency(),
            }
        }
        pub fn cpu_pll_div_in_frequency() -> u32 {
            CPU_PLL_DIV_IN_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn cpu_pll_div_in_source_frequency(source: CpuPllDivInConfig) -> u32 {
            cpu_pll_div_in_config_frequency(source)
        }
        pub fn configure_cpu_pll_div(clocks: &mut ClockTree, config: CpuPllDivConfig) {
            if clocks.pll_clk.is_some() {
                assert!(!((pll_clk_frequency() == 480000000) && (config.divisor() == 4)));
            }
            let old_config = clocks.cpu_pll_div.replace(config);
            refresh_cpu_pll_div_downstream(clocks);
            configure_cpu_pll_div_impl(clocks, old_config, config);
        }
        pub fn cpu_pll_div_config(clocks: &mut ClockTree) -> Option<CpuPllDivConfig> {
            clocks.cpu_pll_div
        }
        pub fn request_cpu_pll_div(clocks: &mut ClockTree) {
            trace!("Enabling CPU_PLL_DIV");
            request_cpu_pll_div_in(clocks);
            enable_cpu_pll_div_impl(clocks, true);
        }
        pub fn release_cpu_pll_div(clocks: &mut ClockTree) {
            trace!("Disabling CPU_PLL_DIV");
            enable_cpu_pll_div_impl(clocks, false);
            release_cpu_pll_div_in(clocks);
        }
        pub fn cpu_pll_div_config_frequency(config: CpuPllDivConfig) -> u32 {
            (cpu_pll_div_in_frequency() / config.divisor())
        }
        pub fn cpu_pll_div_frequency() -> u32 {
            CPU_PLL_DIV_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn cpu_pll_div_source_frequency() -> u32 {
            cpu_pll_div_in_frequency()
        }
        pub fn configure_syscon_pre_div_in(
            clocks: &mut ClockTree,
            new_selector: SysconPreDivInConfig,
        ) {
            let old_selector = clocks.syscon_pre_div_in.replace(new_selector);
            refresh_syscon_pre_div_in_downstream(clocks);
            match new_selector {
                SysconPreDivInConfig::Xtal => request_xtal_clk(clocks),
                SysconPreDivInConfig::RcFast => request_rc_fast_clk(clocks),
            }
            configure_syscon_pre_div_in_impl(clocks, old_selector, new_selector);
            if let Some(old_selector) = old_selector {
                match old_selector {
                    SysconPreDivInConfig::Xtal => release_xtal_clk(clocks),
                    SysconPreDivInConfig::RcFast => release_rc_fast_clk(clocks),
                }
            }
        }
        pub fn syscon_pre_div_in_config(clocks: &mut ClockTree) -> Option<SysconPreDivInConfig> {
            clocks.syscon_pre_div_in
        }
        pub fn request_syscon_pre_div_in(clocks: &mut ClockTree) {
            trace!("Enabling SYSCON_PRE_DIV_IN");
            match unwrap!(clocks.syscon_pre_div_in) {
                SysconPreDivInConfig::Xtal => request_xtal_clk(clocks),
                SysconPreDivInConfig::RcFast => request_rc_fast_clk(clocks),
            }
            enable_syscon_pre_div_in_impl(clocks, true);
        }
        pub fn release_syscon_pre_div_in(clocks: &mut ClockTree) {
            trace!("Disabling SYSCON_PRE_DIV_IN");
            enable_syscon_pre_div_in_impl(clocks, false);
            match unwrap!(clocks.syscon_pre_div_in) {
                SysconPreDivInConfig::Xtal => release_xtal_clk(clocks),
                SysconPreDivInConfig::RcFast => release_rc_fast_clk(clocks),
            }
        }
        pub fn syscon_pre_div_in_config_frequency(config: SysconPreDivInConfig) -> u32 {
            match config {
                SysconPreDivInConfig::Xtal => xtal_clk_frequency(),
                SysconPreDivInConfig::RcFast => rc_fast_clk_frequency(),
            }
        }
        pub fn syscon_pre_div_in_frequency() -> u32 {
            SYSCON_PRE_DIV_IN_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn syscon_pre_div_in_source_frequency(source: SysconPreDivInConfig) -> u32 {
            syscon_pre_div_in_config_frequency(source)
        }
        pub fn configure_syscon_pre_div(clocks: &mut ClockTree, config: SysconPreDivConfig) {
            let old_config = clocks.syscon_pre_div.replace(config);
            refresh_syscon_pre_div_downstream(clocks);
            configure_syscon_pre_div_impl(clocks, old_config, config);
        }
        pub fn syscon_pre_div_config(clocks: &mut ClockTree) -> Option<SysconPreDivConfig> {
            clocks.syscon_pre_div
        }
        pub fn request_syscon_pre_div(clocks: &mut ClockTree) {
            trace!("Enabling SYSCON_PRE_DIV");
            request_syscon_pre_div_in(clocks);
            enable_syscon_pre_div_impl(clocks, true);
        }
        pub fn release_syscon_pre_div(clocks: &mut ClockTree) {
            trace!("Disabling SYSCON_PRE_DIV");
            enable_syscon_pre_div_impl(clocks, false);
            release_syscon_pre_div_in(clocks);
        }
        pub fn syscon_pre_div_config_frequency(config: SysconPreDivConfig) -> u32 {
            (syscon_pre_div_in_frequency() / (config.divisor() + 1))
        }
        pub fn syscon_pre_div_frequency() -> u32 {
            SYSCON_PRE_DIV_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn syscon_pre_div_source_frequency() -> u32 {
            syscon_pre_div_in_frequency()
        }
        pub fn configure_apb_clk(clocks: &mut ClockTree, new_selector: ApbClkConfig) {
            let old_selector = clocks.apb_clk.replace(new_selector);
            refresh_apb_clk_downstream(clocks);
            let active = clocks.apb_clk_refcount > 0;
            if active {
                match new_selector {
                    ApbClkConfig::Pll80m => request_apb_clk_80m(clocks),
                    ApbClkConfig::CpuDiv2 => request_apb_clk_cpu_div2(clocks),
                    ApbClkConfig::Cpu => request_cpu_clk(clocks),
                }
            }
            configure_apb_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    ApbClkConfig::Pll80m => release_apb_clk_80m(clocks),
                    ApbClkConfig::CpuDiv2 => release_apb_clk_cpu_div2(clocks),
                    ApbClkConfig::Cpu => release_cpu_clk(clocks),
                }
            }
        }
        pub fn apb_clk_config(clocks: &mut ClockTree) -> Option<ApbClkConfig> {
            clocks.apb_clk
        }
        pub fn request_apb_clk(clocks: &mut ClockTree) {
            trace!("Requesting APB_CLK");
            if increment_reference_count(&mut clocks.apb_clk_refcount) {
                trace!("Enabling APB_CLK");
                match unwrap!(clocks.apb_clk) {
                    ApbClkConfig::Pll80m => request_apb_clk_80m(clocks),
                    ApbClkConfig::CpuDiv2 => request_apb_clk_cpu_div2(clocks),
                    ApbClkConfig::Cpu => request_cpu_clk(clocks),
                }
                enable_apb_clk_impl(clocks, true);
            }
        }
        pub fn release_apb_clk(clocks: &mut ClockTree) {
            trace!("Releasing APB_CLK");
            if decrement_reference_count(&mut clocks.apb_clk_refcount) {
                trace!("Disabling APB_CLK");
                enable_apb_clk_impl(clocks, false);
                match unwrap!(clocks.apb_clk) {
                    ApbClkConfig::Pll80m => release_apb_clk_80m(clocks),
                    ApbClkConfig::CpuDiv2 => release_apb_clk_cpu_div2(clocks),
                    ApbClkConfig::Cpu => release_cpu_clk(clocks),
                }
            }
        }
        pub fn apb_clk_config_frequency(config: ApbClkConfig) -> u32 {
            match config {
                ApbClkConfig::Pll80m => apb_clk_80m_frequency(),
                ApbClkConfig::CpuDiv2 => apb_clk_cpu_div2_frequency(),
                ApbClkConfig::Cpu => cpu_clk_frequency(),
            }
        }
        pub fn apb_clk_frequency() -> u32 {
            APB_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn apb_clk_source_frequency(source: ApbClkConfig) -> u32 {
            apb_clk_config_frequency(source)
        }
        pub fn configure_ref_tick(clocks: &mut ClockTree, new_selector: RefTickConfig) {
            let old_selector = clocks.ref_tick.replace(new_selector);
            refresh_ref_tick_downstream(clocks);
            let active = clocks.ref_tick_refcount > 0;
            if active {
                match new_selector {
                    RefTickConfig::Pll => request_ref_tick_pll(clocks),
                    RefTickConfig::Apll => request_ref_tick_apll(clocks),
                    RefTickConfig::Xtal => request_ref_tick_xtal(clocks),
                    RefTickConfig::Fosc => request_ref_tick_fosc(clocks),
                }
            }
            configure_ref_tick_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    RefTickConfig::Pll => release_ref_tick_pll(clocks),
                    RefTickConfig::Apll => release_ref_tick_apll(clocks),
                    RefTickConfig::Xtal => release_ref_tick_xtal(clocks),
                    RefTickConfig::Fosc => release_ref_tick_fosc(clocks),
                }
            }
        }
        pub fn ref_tick_config(clocks: &mut ClockTree) -> Option<RefTickConfig> {
            clocks.ref_tick
        }
        pub fn request_ref_tick(clocks: &mut ClockTree) {
            trace!("Requesting REF_TICK");
            if increment_reference_count(&mut clocks.ref_tick_refcount) {
                trace!("Enabling REF_TICK");
                match unwrap!(clocks.ref_tick) {
                    RefTickConfig::Pll => request_ref_tick_pll(clocks),
                    RefTickConfig::Apll => request_ref_tick_apll(clocks),
                    RefTickConfig::Xtal => request_ref_tick_xtal(clocks),
                    RefTickConfig::Fosc => request_ref_tick_fosc(clocks),
                }
                enable_ref_tick_impl(clocks, true);
            }
        }
        pub fn release_ref_tick(clocks: &mut ClockTree) {
            trace!("Releasing REF_TICK");
            if decrement_reference_count(&mut clocks.ref_tick_refcount) {
                trace!("Disabling REF_TICK");
                enable_ref_tick_impl(clocks, false);
                match unwrap!(clocks.ref_tick) {
                    RefTickConfig::Pll => release_ref_tick_pll(clocks),
                    RefTickConfig::Apll => release_ref_tick_apll(clocks),
                    RefTickConfig::Xtal => release_ref_tick_xtal(clocks),
                    RefTickConfig::Fosc => release_ref_tick_fosc(clocks),
                }
            }
        }
        pub fn ref_tick_config_frequency(config: RefTickConfig) -> u32 {
            match config {
                RefTickConfig::Pll => ref_tick_pll_frequency(),
                RefTickConfig::Apll => ref_tick_apll_frequency(),
                RefTickConfig::Xtal => ref_tick_xtal_frequency(),
                RefTickConfig::Fosc => ref_tick_fosc_frequency(),
            }
        }
        pub fn ref_tick_frequency() -> u32 {
            REF_TICK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn ref_tick_source_frequency(source: RefTickConfig) -> u32 {
            ref_tick_config_frequency(source)
        }
        pub fn configure_ref_tick_xtal(clocks: &mut ClockTree, config: RefTickXtalConfig) {
            let old_config = clocks.ref_tick_xtal.replace(config);
            refresh_ref_tick_xtal_downstream(clocks);
            configure_ref_tick_xtal_impl(clocks, old_config, config);
        }
        pub fn ref_tick_xtal_config(clocks: &mut ClockTree) -> Option<RefTickXtalConfig> {
            clocks.ref_tick_xtal
        }
        pub fn request_ref_tick_xtal(clocks: &mut ClockTree) {
            trace!("Enabling REF_TICK_XTAL");
            request_apb_clk(clocks);
            enable_ref_tick_xtal_impl(clocks, true);
        }
        pub fn release_ref_tick_xtal(clocks: &mut ClockTree) {
            trace!("Disabling REF_TICK_XTAL");
            enable_ref_tick_xtal_impl(clocks, false);
            release_apb_clk(clocks);
        }
        pub fn ref_tick_xtal_config_frequency(config: RefTickXtalConfig) -> u32 {
            (apb_clk_frequency() / (config.divisor() + 1))
        }
        pub fn ref_tick_xtal_frequency() -> u32 {
            REF_TICK_XTAL_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn ref_tick_xtal_source_frequency() -> u32 {
            apb_clk_frequency()
        }
        pub fn configure_ref_tick_fosc(clocks: &mut ClockTree, config: RefTickFoscConfig) {
            let old_config = clocks.ref_tick_fosc.replace(config);
            refresh_ref_tick_fosc_downstream(clocks);
            configure_ref_tick_fosc_impl(clocks, old_config, config);
        }
        pub fn ref_tick_fosc_config(clocks: &mut ClockTree) -> Option<RefTickFoscConfig> {
            clocks.ref_tick_fosc
        }
        pub fn request_ref_tick_fosc(clocks: &mut ClockTree) {
            trace!("Enabling REF_TICK_FOSC");
            request_apb_clk(clocks);
            enable_ref_tick_fosc_impl(clocks, true);
        }
        pub fn release_ref_tick_fosc(clocks: &mut ClockTree) {
            trace!("Disabling REF_TICK_FOSC");
            enable_ref_tick_fosc_impl(clocks, false);
            release_apb_clk(clocks);
        }
        pub fn ref_tick_fosc_config_frequency(config: RefTickFoscConfig) -> u32 {
            (apb_clk_frequency() / (config.divisor() + 1))
        }
        pub fn ref_tick_fosc_frequency() -> u32 {
            REF_TICK_FOSC_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn ref_tick_fosc_source_frequency() -> u32 {
            apb_clk_frequency()
        }
        pub fn configure_ref_tick_apll(clocks: &mut ClockTree, config: RefTickApllConfig) {
            let old_config = clocks.ref_tick_apll.replace(config);
            refresh_ref_tick_apll_downstream(clocks);
            configure_ref_tick_apll_impl(clocks, old_config, config);
        }
        pub fn ref_tick_apll_config(clocks: &mut ClockTree) -> Option<RefTickApllConfig> {
            clocks.ref_tick_apll
        }
        pub fn request_ref_tick_apll(clocks: &mut ClockTree) {
            trace!("Enabling REF_TICK_APLL");
            request_apb_clk(clocks);
            enable_ref_tick_apll_impl(clocks, true);
        }
        pub fn release_ref_tick_apll(clocks: &mut ClockTree) {
            trace!("Disabling REF_TICK_APLL");
            enable_ref_tick_apll_impl(clocks, false);
            release_apb_clk(clocks);
        }
        pub fn ref_tick_apll_config_frequency(config: RefTickApllConfig) -> u32 {
            (apb_clk_frequency() / (config.divisor() + 1))
        }
        pub fn ref_tick_apll_frequency() -> u32 {
            REF_TICK_APLL_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn ref_tick_apll_source_frequency() -> u32 {
            apb_clk_frequency()
        }
        pub fn configure_ref_tick_pll(clocks: &mut ClockTree, config: RefTickPllConfig) {
            let old_config = clocks.ref_tick_pll.replace(config);
            refresh_ref_tick_pll_downstream(clocks);
            configure_ref_tick_pll_impl(clocks, old_config, config);
        }
        pub fn ref_tick_pll_config(clocks: &mut ClockTree) -> Option<RefTickPllConfig> {
            clocks.ref_tick_pll
        }
        pub fn request_ref_tick_pll(clocks: &mut ClockTree) {
            trace!("Enabling REF_TICK_PLL");
            request_apb_clk(clocks);
            enable_ref_tick_pll_impl(clocks, true);
        }
        pub fn release_ref_tick_pll(clocks: &mut ClockTree) {
            trace!("Disabling REF_TICK_PLL");
            enable_ref_tick_pll_impl(clocks, false);
            release_apb_clk(clocks);
        }
        pub fn ref_tick_pll_config_frequency(config: RefTickPllConfig) -> u32 {
            (apb_clk_frequency() / (config.divisor() + 1))
        }
        pub fn ref_tick_pll_frequency() -> u32 {
            REF_TICK_PLL_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn ref_tick_pll_source_frequency() -> u32 {
            apb_clk_frequency()
        }
        pub fn configure_cpu_clk(clocks: &mut ClockTree, new_selector: CpuClkConfig) {
            let old_selector = clocks.cpu_clk.replace(new_selector);
            refresh_cpu_clk_downstream(clocks);
            match new_selector {
                CpuClkConfig::Xtal => {
                    configure_apb_clk(clocks, ApbClkConfig::Cpu);
                    configure_syscon_pre_div_in(clocks, SysconPreDivInConfig::Xtal);
                    configure_ref_tick(clocks, RefTickConfig::Xtal);
                    let config_value =
                        RefTickXtalConfig::new(((apb_clk_frequency() / 1000000) - 1));
                    configure_ref_tick_xtal(clocks, config_value);
                }
                CpuClkConfig::RcFast => {
                    configure_apb_clk(clocks, ApbClkConfig::Cpu);
                    configure_syscon_pre_div_in(clocks, SysconPreDivInConfig::RcFast);
                    configure_ref_tick(clocks, RefTickConfig::Fosc);
                    let config_value =
                        RefTickFoscConfig::new(((apb_clk_frequency() / 1000000) - 1));
                    configure_ref_tick_fosc(clocks, config_value);
                }
                CpuClkConfig::Apll => {
                    configure_apb_clk(clocks, ApbClkConfig::CpuDiv2);
                    configure_cpu_pll_div_in(clocks, CpuPllDivInConfig::Apll);
                    configure_ref_tick(clocks, RefTickConfig::Apll);
                    let config_value =
                        RefTickApllConfig::new(((apb_clk_frequency() / 1000000) - 1));
                    configure_ref_tick_apll(clocks, config_value);
                }
                CpuClkConfig::Pll => {
                    configure_apb_clk(clocks, ApbClkConfig::Pll80m);
                    configure_cpu_pll_div_in(clocks, CpuPllDivInConfig::Pll);
                    configure_ref_tick(clocks, RefTickConfig::Pll);
                    let config_value = RefTickPllConfig::new(((apb_clk_frequency() / 1000000) - 1));
                    configure_ref_tick_pll(clocks, config_value);
                }
            }
            match new_selector {
                CpuClkConfig::Xtal => request_syscon_pre_div(clocks),
                CpuClkConfig::RcFast => request_syscon_pre_div(clocks),
                CpuClkConfig::Apll => request_cpu_pll_div(clocks),
                CpuClkConfig::Pll => request_cpu_pll_div(clocks),
            }
            configure_cpu_clk_impl(clocks, old_selector, new_selector);
            if let Some(old_selector) = old_selector {
                match old_selector {
                    CpuClkConfig::Xtal => release_syscon_pre_div(clocks),
                    CpuClkConfig::RcFast => release_syscon_pre_div(clocks),
                    CpuClkConfig::Apll => release_cpu_pll_div(clocks),
                    CpuClkConfig::Pll => release_cpu_pll_div(clocks),
                }
            }
        }
        pub fn cpu_clk_config(clocks: &mut ClockTree) -> Option<CpuClkConfig> {
            clocks.cpu_clk
        }
        fn request_cpu_clk(_clocks: &mut ClockTree) {}
        fn release_cpu_clk(_clocks: &mut ClockTree) {}
        pub fn cpu_clk_config_frequency(config: CpuClkConfig) -> u32 {
            match config {
                CpuClkConfig::Xtal => syscon_pre_div_frequency(),
                CpuClkConfig::RcFast => syscon_pre_div_frequency(),
                CpuClkConfig::Apll => cpu_pll_div_frequency(),
                CpuClkConfig::Pll => cpu_pll_div_frequency(),
            }
        }
        pub fn cpu_clk_frequency() -> u32 {
            CPU_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn request_apb_clk_cpu_div2(clocks: &mut ClockTree) {
            trace!("Enabling APB_CLK_CPU_DIV2");
            request_cpu_clk(clocks);
            enable_apb_clk_cpu_div2_impl(clocks, true);
        }
        pub fn release_apb_clk_cpu_div2(clocks: &mut ClockTree) {
            trace!("Disabling APB_CLK_CPU_DIV2");
            enable_apb_clk_cpu_div2_impl(clocks, false);
            release_cpu_clk(clocks);
        }
        pub fn apb_clk_cpu_div2_frequency() -> u32 {
            (cpu_clk_frequency() / 2)
        }
        pub fn apb_clk_cpu_div2_source_frequency() -> u32 {
            cpu_clk_frequency()
        }
        pub fn request_apb_clk_80m(clocks: &mut ClockTree) {
            trace!("Enabling APB_CLK_80M");
            request_cpu_clk(clocks);
            enable_apb_clk_80m_impl(clocks, true);
        }
        pub fn release_apb_clk_80m(clocks: &mut ClockTree) {
            trace!("Disabling APB_CLK_80M");
            enable_apb_clk_80m_impl(clocks, false);
            release_cpu_clk(clocks);
        }
        pub fn apb_clk_80m_frequency() -> u32 {
            80000000
        }
        pub fn apb_clk_80m_source_frequency() -> u32 {
            cpu_clk_frequency()
        }
        #[cfg(use_xtal32k)]
        pub fn request_xtal32k_clk(clocks: &mut ClockTree) {
            trace!("Requesting XTAL32K_CLK");
            if increment_reference_count(&mut clocks.xtal32k_clk_refcount) {
                trace!("Enabling XTAL32K_CLK");
                enable_xtal32k_clk_impl(clocks, true);
            }
        }
        #[cfg(use_xtal32k)]
        pub fn release_xtal32k_clk(clocks: &mut ClockTree) {
            trace!("Releasing XTAL32K_CLK");
            if decrement_reference_count(&mut clocks.xtal32k_clk_refcount) {
                trace!("Disabling XTAL32K_CLK");
                enable_xtal32k_clk_impl(clocks, false);
            }
        }
        #[cfg(use_xtal32k)]
        pub fn xtal32k_clk_frequency() -> u32 {
            32768
        }
        pub fn request_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC_SLOW_CLK");
            if increment_reference_count(&mut clocks.rc_slow_clk_refcount) {
                trace!("Enabling RC_SLOW_CLK");
                enable_rc_slow_clk_impl(clocks, true);
            }
        }
        pub fn release_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC_SLOW_CLK");
            if decrement_reference_count(&mut clocks.rc_slow_clk_refcount) {
                trace!("Disabling RC_SLOW_CLK");
                enable_rc_slow_clk_impl(clocks, false);
            }
        }
        static RC_SLOW_CLK_FREQUENCY: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(rc_slow_clk_nominal_frequency());
        pub const fn rc_slow_clk_nominal_frequency() -> u32 {
            150000
        }
        pub fn rc_slow_clk_frequency() -> u32 {
            RC_SLOW_CLK_FREQUENCY.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn set_rc_slow_clk_frequency(clocks: &mut ClockTree, frequency: u32) {
            if !(75000..=225000).contains(&frequency) {
                warn!(
                    "Ignoring out-of-range RC_SLOW_CLK frequency: {} Hz",
                    frequency
                );
                return;
            }
            debug!(
                "Updating RC_SLOW_CLK frequency to {} Hz (nominal {} Hz)",
                frequency,
                rc_slow_clk_nominal_frequency()
            );
            RC_SLOW_CLK_FREQUENCY.store(frequency, ::core::sync::atomic::Ordering::Release);
            refresh_rc_slow_clk_downstream(clocks);
        }
        pub fn request_rc_fast_div_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC_FAST_DIV_CLK");
            if increment_reference_count(&mut clocks.rc_fast_div_clk_refcount) {
                trace!("Enabling RC_FAST_DIV_CLK");
                request_rc_fast_clk(clocks);
                enable_rc_fast_div_clk_impl(clocks, true);
            }
        }
        pub fn release_rc_fast_div_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC_FAST_DIV_CLK");
            if decrement_reference_count(&mut clocks.rc_fast_div_clk_refcount) {
                trace!("Disabling RC_FAST_DIV_CLK");
                enable_rc_fast_div_clk_impl(clocks, false);
                release_rc_fast_clk(clocks);
            }
        }
        pub fn rc_fast_div_clk_frequency() -> u32 {
            (rc_fast_clk_frequency() / 256)
        }
        pub fn rc_fast_div_clk_source_frequency() -> u32 {
            rc_fast_clk_frequency()
        }
        pub fn request_xtal_div_clk(clocks: &mut ClockTree) {
            trace!("Enabling XTAL_DIV_CLK");
            request_xtal_clk(clocks);
            enable_xtal_div_clk_impl(clocks, true);
        }
        pub fn release_xtal_div_clk(clocks: &mut ClockTree) {
            trace!("Disabling XTAL_DIV_CLK");
            enable_xtal_div_clk_impl(clocks, false);
            release_xtal_clk(clocks);
        }
        pub fn xtal_div_clk_frequency() -> u32 {
            (xtal_clk_frequency() / 4)
        }
        pub fn xtal_div_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn configure_rtc_slow_clk(clocks: &mut ClockTree, new_selector: RtcSlowClkConfig) {
            let old_selector = clocks.rtc_slow_clk.replace(new_selector);
            refresh_rtc_slow_clk_downstream(clocks);
            match new_selector {
                #[cfg(use_xtal32k)]
                RtcSlowClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                RtcSlowClkConfig::RcSlow => request_rc_slow_clk(clocks),
                RtcSlowClkConfig::RcFast => request_rc_fast_div_clk(clocks),
            }
            configure_rtc_slow_clk_impl(clocks, old_selector, new_selector);
            if let Some(old_selector) = old_selector {
                match old_selector {
                    #[cfg(use_xtal32k)]
                    RtcSlowClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                    RtcSlowClkConfig::RcSlow => release_rc_slow_clk(clocks),
                    RtcSlowClkConfig::RcFast => release_rc_fast_div_clk(clocks),
                }
            }
        }
        pub fn rtc_slow_clk_config(clocks: &mut ClockTree) -> Option<RtcSlowClkConfig> {
            clocks.rtc_slow_clk
        }
        pub fn request_rtc_slow_clk(clocks: &mut ClockTree) {
            trace!("Enabling RTC_SLOW_CLK");
            match unwrap!(clocks.rtc_slow_clk) {
                #[cfg(use_xtal32k)]
                RtcSlowClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                RtcSlowClkConfig::RcSlow => request_rc_slow_clk(clocks),
                RtcSlowClkConfig::RcFast => request_rc_fast_div_clk(clocks),
            }
            enable_rtc_slow_clk_impl(clocks, true);
        }
        pub fn release_rtc_slow_clk(clocks: &mut ClockTree) {
            trace!("Disabling RTC_SLOW_CLK");
            enable_rtc_slow_clk_impl(clocks, false);
            match unwrap!(clocks.rtc_slow_clk) {
                #[cfg(use_xtal32k)]
                RtcSlowClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                RtcSlowClkConfig::RcSlow => release_rc_slow_clk(clocks),
                RtcSlowClkConfig::RcFast => release_rc_fast_div_clk(clocks),
            }
        }
        pub fn rtc_slow_clk_config_frequency(config: RtcSlowClkConfig) -> u32 {
            match config {
                #[cfg(use_xtal32k)]
                RtcSlowClkConfig::Xtal32k => xtal32k_clk_frequency(),
                RtcSlowClkConfig::RcSlow => rc_slow_clk_frequency(),
                RtcSlowClkConfig::RcFast => rc_fast_div_clk_frequency(),
            }
        }
        pub fn rtc_slow_clk_frequency() -> u32 {
            RTC_SLOW_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn rtc_slow_clk_source_frequency(source: RtcSlowClkConfig) -> u32 {
            rtc_slow_clk_config_frequency(source)
        }
        pub fn request_ble_lp_xtal_clk(clocks: &mut ClockTree) {
            trace!("Enabling BLE_LP_XTAL_CLK");
            request_xtal_clk(clocks);
            enable_ble_lp_xtal_clk_impl(clocks, true);
        }
        pub fn release_ble_lp_xtal_clk(clocks: &mut ClockTree) {
            trace!("Disabling BLE_LP_XTAL_CLK");
            enable_ble_lp_xtal_clk_impl(clocks, false);
            release_xtal_clk(clocks);
        }
        pub fn ble_lp_xtal_clk_frequency() -> u32 {
            500000
        }
        pub fn ble_lp_xtal_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn configure_ble_lp_clk(clocks: &mut ClockTree, new_selector: BleLpClkConfig) {
            let old_selector = clocks.ble_lp_clk.replace(new_selector);
            refresh_ble_lp_clk_downstream(clocks);
            let active = clocks.ble_lp_clk_refcount > 0;
            if active {
                match new_selector {
                    BleLpClkConfig::Xtal => request_ble_lp_xtal_clk(clocks),
                    BleLpClkConfig::RtcSlow => request_rtc_slow_clk(clocks),
                }
            }
            configure_ble_lp_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    BleLpClkConfig::Xtal => release_ble_lp_xtal_clk(clocks),
                    BleLpClkConfig::RtcSlow => release_rtc_slow_clk(clocks),
                }
            }
        }
        pub fn ble_lp_clk_config(clocks: &mut ClockTree) -> Option<BleLpClkConfig> {
            clocks.ble_lp_clk
        }
        pub fn request_ble_lp_clk(clocks: &mut ClockTree) {
            trace!("Requesting BLE_LP_CLK");
            if increment_reference_count(&mut clocks.ble_lp_clk_refcount) {
                trace!("Enabling BLE_LP_CLK");
                match unwrap!(clocks.ble_lp_clk) {
                    BleLpClkConfig::Xtal => request_ble_lp_xtal_clk(clocks),
                    BleLpClkConfig::RtcSlow => request_rtc_slow_clk(clocks),
                }
                enable_ble_lp_clk_impl(clocks, true);
            }
        }
        pub fn release_ble_lp_clk(clocks: &mut ClockTree) {
            trace!("Releasing BLE_LP_CLK");
            if decrement_reference_count(&mut clocks.ble_lp_clk_refcount) {
                trace!("Disabling BLE_LP_CLK");
                enable_ble_lp_clk_impl(clocks, false);
                match unwrap!(clocks.ble_lp_clk) {
                    BleLpClkConfig::Xtal => release_ble_lp_xtal_clk(clocks),
                    BleLpClkConfig::RtcSlow => release_rtc_slow_clk(clocks),
                }
            }
        }
        pub fn ble_lp_clk_config_frequency(config: BleLpClkConfig) -> u32 {
            match config {
                BleLpClkConfig::Xtal => ble_lp_xtal_clk_frequency(),
                BleLpClkConfig::RtcSlow => rtc_slow_clk_frequency(),
            }
        }
        pub fn ble_lp_clk_frequency() -> u32 {
            BLE_LP_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn ble_lp_clk_source_frequency(source: BleLpClkConfig) -> u32 {
            ble_lp_clk_config_frequency(source)
        }
        pub fn configure_rtc_fast_clk(clocks: &mut ClockTree, new_selector: RtcFastClkConfig) {
            let old_selector = clocks.rtc_fast_clk.replace(new_selector);
            refresh_rtc_fast_clk_downstream(clocks);
            let active = clocks.rtc_fast_clk_refcount > 0;
            if active {
                match new_selector {
                    RtcFastClkConfig::Xtal => request_xtal_div_clk(clocks),
                    RtcFastClkConfig::Rc => request_rc_fast_clk(clocks),
                }
            }
            configure_rtc_fast_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    RtcFastClkConfig::Xtal => release_xtal_div_clk(clocks),
                    RtcFastClkConfig::Rc => release_rc_fast_clk(clocks),
                }
            }
        }
        pub fn rtc_fast_clk_config(clocks: &mut ClockTree) -> Option<RtcFastClkConfig> {
            clocks.rtc_fast_clk
        }
        pub fn request_rtc_fast_clk(clocks: &mut ClockTree) {
            trace!("Requesting RTC_FAST_CLK");
            if increment_reference_count(&mut clocks.rtc_fast_clk_refcount) {
                trace!("Enabling RTC_FAST_CLK");
                match unwrap!(clocks.rtc_fast_clk) {
                    RtcFastClkConfig::Xtal => request_xtal_div_clk(clocks),
                    RtcFastClkConfig::Rc => request_rc_fast_clk(clocks),
                }
                enable_rtc_fast_clk_impl(clocks, true);
            }
        }
        pub fn release_rtc_fast_clk(clocks: &mut ClockTree) {
            trace!("Releasing RTC_FAST_CLK");
            if decrement_reference_count(&mut clocks.rtc_fast_clk_refcount) {
                trace!("Disabling RTC_FAST_CLK");
                enable_rtc_fast_clk_impl(clocks, false);
                match unwrap!(clocks.rtc_fast_clk) {
                    RtcFastClkConfig::Xtal => release_xtal_div_clk(clocks),
                    RtcFastClkConfig::Rc => release_rc_fast_clk(clocks),
                }
            }
        }
        pub fn rtc_fast_clk_config_frequency(config: RtcFastClkConfig) -> u32 {
            match config {
                RtcFastClkConfig::Xtal => xtal_div_clk_frequency(),
                RtcFastClkConfig::Rc => rc_fast_clk_frequency(),
            }
        }
        pub fn rtc_fast_clk_frequency() -> u32 {
            RTC_FAST_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn rtc_fast_clk_source_frequency(source: RtcFastClkConfig) -> u32 {
            rtc_fast_clk_config_frequency(source)
        }
        pub fn request_uart_mem_clk(clocks: &mut ClockTree) {
            trace!("Requesting UART_MEM_CLK");
            if increment_reference_count(&mut clocks.uart_mem_clk_refcount) {
                trace!("Enabling UART_MEM_CLK");
                request_xtal_clk(clocks);
                enable_uart_mem_clk_impl(clocks, true);
            }
        }
        pub fn release_uart_mem_clk(clocks: &mut ClockTree) {
            trace!("Releasing UART_MEM_CLK");
            if decrement_reference_count(&mut clocks.uart_mem_clk_refcount) {
                trace!("Disabling UART_MEM_CLK");
                enable_uart_mem_clk_impl(clocks, false);
                release_xtal_clk(clocks);
            }
        }
        pub fn uart_mem_clk_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn uart_mem_clk_source_frequency(source: UartMemClkConfig) -> u32 {
            match source {
                UartMemClkConfig::Xtal => xtal_clk_frequency(),
            }
        }
        pub fn configure_timg_calibration_clock(
            clocks: &mut ClockTree,
            new_selector: TimgCalibrationClockConfig,
        ) {
            let old_selector = clocks.timg_calibration_clock.replace(new_selector);
            refresh_timg_calibration_clock_downstream(clocks);
            let active = clocks.timg_calibration_clock_refcount > 0;
            if active {
                match new_selector {
                    TimgCalibrationClockConfig::RcSlowClk => request_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => request_rc_fast_div_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => request_xtal32k_clk(clocks),
                }
            }
            configure_timg_calibration_clock_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    TimgCalibrationClockConfig::RcSlowClk => release_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => release_rc_fast_div_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => release_xtal32k_clk(clocks),
                }
            }
        }
        pub fn timg_calibration_clock_config(
            clocks: &mut ClockTree,
        ) -> Option<TimgCalibrationClockConfig> {
            clocks.timg_calibration_clock
        }
        pub fn request_timg_calibration_clock(clocks: &mut ClockTree) {
            trace!("Requesting TIMG_CALIBRATION_CLOCK");
            if increment_reference_count(&mut clocks.timg_calibration_clock_refcount) {
                trace!("Enabling TIMG_CALIBRATION_CLOCK");
                crate::rtc_cntl::WakeLock::acquire();
                match unwrap!(clocks.timg_calibration_clock) {
                    TimgCalibrationClockConfig::RcSlowClk => request_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => request_rc_fast_div_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => request_xtal32k_clk(clocks),
                }
                enable_timg_calibration_clock_impl(clocks, true);
            }
        }
        pub fn release_timg_calibration_clock(clocks: &mut ClockTree) {
            trace!("Releasing TIMG_CALIBRATION_CLOCK");
            if decrement_reference_count(&mut clocks.timg_calibration_clock_refcount) {
                trace!("Disabling TIMG_CALIBRATION_CLOCK");
                crate::rtc_cntl::WakeLock::release();
                enable_timg_calibration_clock_impl(clocks, false);
                match unwrap!(clocks.timg_calibration_clock) {
                    TimgCalibrationClockConfig::RcSlowClk => release_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => release_rc_fast_div_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => release_xtal32k_clk(clocks),
                }
            }
        }
        pub fn timg_calibration_clock_config_frequency(config: TimgCalibrationClockConfig) -> u32 {
            match config {
                TimgCalibrationClockConfig::RcSlowClk => rc_slow_clk_frequency(),
                TimgCalibrationClockConfig::RcFastDivClk => rc_fast_div_clk_frequency(),
                #[cfg(use_xtal32k)]
                TimgCalibrationClockConfig::Xtal32kClk => xtal32k_clk_frequency(),
            }
        }
        pub fn timg_calibration_clock_frequency() -> u32 {
            TIMG_CALIBRATION_CLOCK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn timg_calibration_clock_source_frequency(source: TimgCalibrationClockConfig) -> u32 {
            timg_calibration_clock_config_frequency(source)
        }
        impl SdmInstance {
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(&mut clocks.sdm_function_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    request_apb_clk(clocks);
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(&mut clocks.sdm_function_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    release_apb_clk(clocks);
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                apb_clk_frequency()
            }
            pub fn function_clock_source_frequency() -> u32 {
                apb_clk_frequency()
            }
        }
        impl I2cInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                config: I2cFunctionClockConfig,
            ) {
                let old_config = clocks.i2c_function_clock[self as usize].replace(config);
                refresh_i2c_function_clock_downstream(clocks, self);
                self.configure_function_clock_impl(clocks, old_config, config);
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<I2cFunctionClockConfig> {
                clocks.i2c_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(&mut clocks.i2c_function_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.i2c_function_clock[self as usize]).sclk {
                        I2cFunctionClockSclk::Apb => request_apb_clk(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(&mut clocks.i2c_function_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.i2c_function_clock[self as usize]).sclk {
                        I2cFunctionClockSclk::Apb => release_apb_clk(clocks),
                    }
                }
            }
            #[allow(unused_variables)]
            pub fn function_clock_config_frequency(config: I2cFunctionClockConfig) -> u32 {
                apb_clk_frequency()
            }
            pub fn function_clock_frequency(self) -> u32 {
                apb_clk_frequency()
            }
            pub fn function_clock_source_frequency(sclk: I2cFunctionClockSclk) -> u32 {
                match sclk {
                    I2cFunctionClockSclk::Apb => apb_clk_frequency(),
                }
            }
        }
        impl I2sInstance {
            pub fn configure_mclk(self, clocks: &mut ClockTree, config: I2sMclkConfig) {
                let old_config = clocks.i2s_mclk[self as usize].replace(config);
                refresh_i2s_mclk_downstream(clocks, self);
                let active = clocks.i2s_mclk_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        I2sMclkSclk::PllF160m => request_pll_f160m_clk(clocks),
                        I2sMclkSclk::Apll => request_apll_clk(clocks),
                    }
                }
                self.configure_mclk_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        I2sMclkSclk::PllF160m => release_pll_f160m_clk(clocks),
                        I2sMclkSclk::Apll => release_apll_clk(clocks),
                    }
                }
            }
            pub fn mclk_config(self, clocks: &mut ClockTree) -> Option<I2sMclkConfig> {
                clocks.i2s_mclk[self as usize]
            }
            pub fn request_mclk(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::MCLK", self);
                if increment_reference_count(&mut clocks.i2s_mclk_refcount[self as usize]) {
                    trace!("Enabling {:?}::MCLK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.i2s_mclk[self as usize]).sclk {
                        I2sMclkSclk::PllF160m => request_pll_f160m_clk(clocks),
                        I2sMclkSclk::Apll => request_apll_clk(clocks),
                    }
                    self.enable_mclk_impl(clocks, true);
                }
            }
            pub fn release_mclk(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::MCLK", self);
                if decrement_reference_count(&mut clocks.i2s_mclk_refcount[self as usize]) {
                    trace!("Disabling {:?}::MCLK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_mclk_impl(clocks, false);
                    match unwrap!(clocks.i2s_mclk[self as usize]).sclk {
                        I2sMclkSclk::PllF160m => release_pll_f160m_clk(clocks),
                        I2sMclkSclk::Apll => release_apll_clk(clocks),
                    }
                }
            }
            pub fn mclk_config_frequency(config: I2sMclkConfig) -> u32 {
                (((match config.sclk {
                    I2sMclkSclk::PllF160m => pll_f160m_clk_frequency(),
                    I2sMclkSclk::Apll => apll_clk_frequency(),
                } as u64)
                    * (config.div_a() as u64))
                    / (((config.div_num() * config.div_a()) + config.div_b()) as u64))
                    as u32
            }
            pub fn mclk_frequency(self) -> u32 {
                I2S_MCLK_FREQ_CACHE[self as usize].load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn mclk_source_frequency(sclk: I2sMclkSclk) -> u32 {
                match sclk {
                    I2sMclkSclk::PllF160m => pll_f160m_clk_frequency(),
                    I2sMclkSclk::Apll => apll_clk_frequency(),
                }
            }
        }
        impl McpwmInstance {
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(
                    &mut clocks.mcpwm_function_clock_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    request_pll_f160m_clk(clocks);
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(
                    &mut clocks.mcpwm_function_clock_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_function_clock_impl(clocks, false);
                    release_pll_f160m_clk(clocks);
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                pll_f160m_clk_frequency()
            }
            pub fn function_clock_source_frequency(source: McpwmFunctionClockConfig) -> u32 {
                match source {
                    McpwmFunctionClockConfig::PllF160m => pll_f160m_clk_frequency(),
                }
            }
        }
        impl RmtInstance {
            pub fn configure_sclk(self, clocks: &mut ClockTree, new_selector: RmtSclkConfig) {
                let old_selector = clocks.rmt_sclk[self as usize].replace(new_selector);
                refresh_rmt_sclk_downstream(clocks, self);
                let active = clocks.rmt_sclk_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        RmtSclkConfig::RefTick => request_ref_tick(clocks),
                        RmtSclkConfig::ApbClk => request_apb_clk(clocks),
                    }
                }
                self.configure_sclk_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        RmtSclkConfig::RefTick => release_ref_tick(clocks),
                        RmtSclkConfig::ApbClk => release_apb_clk(clocks),
                    }
                }
            }
            pub fn sclk_config(self, clocks: &mut ClockTree) -> Option<RmtSclkConfig> {
                clocks.rmt_sclk[self as usize]
            }
            pub fn request_sclk(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::SCLK", self);
                if increment_reference_count(&mut clocks.rmt_sclk_refcount[self as usize]) {
                    trace!("Enabling {:?}::SCLK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.rmt_sclk[self as usize]) {
                        RmtSclkConfig::RefTick => request_ref_tick(clocks),
                        RmtSclkConfig::ApbClk => request_apb_clk(clocks),
                    }
                    self.enable_sclk_impl(clocks, true);
                }
            }
            pub fn release_sclk(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::SCLK", self);
                if decrement_reference_count(&mut clocks.rmt_sclk_refcount[self as usize]) {
                    trace!("Disabling {:?}::SCLK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_sclk_impl(clocks, false);
                    match unwrap!(clocks.rmt_sclk[self as usize]) {
                        RmtSclkConfig::RefTick => release_ref_tick(clocks),
                        RmtSclkConfig::ApbClk => release_apb_clk(clocks),
                    }
                }
            }
            pub fn sclk_config_frequency(config: RmtSclkConfig) -> u32 {
                match config {
                    RmtSclkConfig::RefTick => ref_tick_frequency(),
                    RmtSclkConfig::ApbClk => apb_clk_frequency(),
                }
            }
            pub fn sclk_frequency(self) -> u32 {
                RMT_SCLK_FREQ_CACHE[self as usize].load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn sclk_source_frequency(source: RmtSclkConfig) -> u32 {
                Self::sclk_config_frequency(source)
            }
        }
        impl SpiInstance {
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(&mut clocks.spi_function_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    request_apb_clk(clocks);
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(&mut clocks.spi_function_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_function_clock_impl(clocks, false);
                    release_apb_clk(clocks);
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                apb_clk_frequency()
            }
            pub fn function_clock_source_frequency(source: SpiFunctionClockConfig) -> u32 {
                match source {
                    SpiFunctionClockConfig::Apb => apb_clk_frequency(),
                }
            }
        }
        impl UartInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                config: UartFunctionClockConfig,
            ) {
                let old_config = clocks.uart_function_clock[self as usize].replace(config);
                refresh_uart_function_clock_downstream(clocks, self);
                let active = clocks.uart_function_clock_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        UartFunctionClockSclk::Apb => request_apb_clk(clocks),
                        UartFunctionClockSclk::RefTick => request_ref_tick(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        UartFunctionClockSclk::Apb => release_apb_clk(clocks),
                        UartFunctionClockSclk::RefTick => release_ref_tick(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<UartFunctionClockConfig> {
                clocks.uart_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(
                    &mut clocks.uart_function_clock_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.uart_function_clock[self as usize]).sclk {
                        UartFunctionClockSclk::Apb => request_apb_clk(clocks),
                        UartFunctionClockSclk::RefTick => request_ref_tick(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(
                    &mut clocks.uart_function_clock_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.uart_function_clock[self as usize]).sclk {
                        UartFunctionClockSclk::Apb => release_apb_clk(clocks),
                        UartFunctionClockSclk::RefTick => release_ref_tick(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: UartFunctionClockConfig) -> u32 {
                match config.sclk {
                    UartFunctionClockSclk::Apb => apb_clk_frequency(),
                    UartFunctionClockSclk::RefTick => ref_tick_frequency(),
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                UART_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(sclk: UartFunctionClockSclk) -> u32 {
                match sclk {
                    UartFunctionClockSclk::Apb => apb_clk_frequency(),
                    UartFunctionClockSclk::RefTick => ref_tick_frequency(),
                }
            }
            pub fn request_mem_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::MEM_CLOCK", self);
                if increment_reference_count(&mut clocks.uart_mem_clock_refcount[self as usize]) {
                    trace!("Enabling {:?}::MEM_CLOCK", self);
                    request_uart_mem_clk(clocks);
                    self.enable_mem_clock_impl(clocks, true);
                }
            }
            pub fn release_mem_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::MEM_CLOCK", self);
                if decrement_reference_count(&mut clocks.uart_mem_clock_refcount[self as usize]) {
                    trace!("Disabling {:?}::MEM_CLOCK", self);
                    self.enable_mem_clock_impl(clocks, false);
                    release_uart_mem_clk(clocks);
                }
            }
            pub fn mem_clock_frequency(self) -> u32 {
                uart_mem_clk_frequency()
            }
            pub fn mem_clock_source_frequency() -> u32 {
                uart_mem_clk_frequency()
            }
            pub fn configure_baud_rate_generator(
                self,
                clocks: &mut ClockTree,
                config: UartBaudRateGeneratorConfig,
            ) {
                let old_config = clocks.uart_baud_rate_generator[self as usize].replace(config);
                refresh_uart_baud_rate_generator_downstream(clocks, self);
                self.configure_baud_rate_generator_impl(clocks, old_config, config);
            }
            pub fn baud_rate_generator_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<UartBaudRateGeneratorConfig> {
                clocks.uart_baud_rate_generator[self as usize]
            }
            pub fn request_baud_rate_generator(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::BAUD_RATE_GENERATOR", self);
                if increment_reference_count(
                    &mut clocks.uart_baud_rate_generator_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::BAUD_RATE_GENERATOR", self);
                    self.request_function_clock(clocks);
                    self.enable_baud_rate_generator_impl(clocks, true);
                }
            }
            pub fn release_baud_rate_generator(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::BAUD_RATE_GENERATOR", self);
                if decrement_reference_count(
                    &mut clocks.uart_baud_rate_generator_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::BAUD_RATE_GENERATOR", self);
                    self.enable_baud_rate_generator_impl(clocks, false);
                    self.release_function_clock(clocks);
                }
            }
            pub fn baud_rate_generator_config_frequency(
                self,
                config: UartBaudRateGeneratorConfig,
            ) -> u32 {
                ((self.function_clock_frequency() * 16)
                    / ((config.integral() * 16) + config.fractional()))
            }
            pub fn baud_rate_generator_frequency(self) -> u32 {
                UART_BAUD_RATE_GENERATOR_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
        }
        /// Clock tree configuration.
        ///
        /// The fields of this struct are optional, with the following caveats:
        /// - If `XTAL_CLK` is not specified, the crystal frequency will be automatically detected
        ///   if possible.
        /// - The CPU and its upstream clock nodes will be set to a default configuration.
        /// - Other unspecified clock sources will not be useable by peripherals.
        #[derive(Debug, Clone, Copy, PartialEq, Eq)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[instability::unstable]
        pub struct ClockConfig {
            /// `XTAL_CLK` configuration.
            pub xtal_clk: Option<XtalClkConfig>,
            /// `PLL_CLK` configuration.
            pub pll_clk: Option<PllClkConfig>,
            /// `APLL_CLK` configuration.
            pub apll_clk: Option<ApllClkConfig>,
            /// `CPU_PLL_DIV` configuration.
            pub cpu_pll_div: Option<CpuPllDivConfig>,
            /// `SYSCON_PRE_DIV` configuration.
            pub syscon_pre_div: Option<SysconPreDivConfig>,
            /// `CPU_CLK` configuration.
            pub cpu_clk: Option<CpuClkConfig>,
            /// `RTC_SLOW_CLK` configuration.
            pub rtc_slow_clk: Option<RtcSlowClkConfig>,
            /// `BLE_LP_CLK` configuration.
            pub ble_lp_clk: Option<BleLpClkConfig>,
            /// `RTC_FAST_CLK` configuration.
            pub rtc_fast_clk: Option<RtcFastClkConfig>,
            /// `TIMG_CALIBRATION_CLOCK` configuration.
            pub timg_calibration_clock: Option<TimgCalibrationClockConfig>,
        }
        impl ClockConfig {
            fn apply(&self, clocks: &mut ClockTree) {
                if let Some(config) = self.xtal_clk {
                    configure_xtal_clk(clocks, config);
                }
                if let Some(config) = self.pll_clk {
                    configure_pll_clk(clocks, config);
                }
                if let Some(config) = self.apll_clk {
                    configure_apll_clk(clocks, config);
                }
                if let Some(config) = self.cpu_pll_div {
                    configure_cpu_pll_div(clocks, config);
                }
                if let Some(config) = self.syscon_pre_div {
                    configure_syscon_pre_div(clocks, config);
                }
                if let Some(config) = self.cpu_clk {
                    configure_cpu_clk(clocks, config);
                }
                if let Some(config) = self.rtc_slow_clk {
                    configure_rtc_slow_clk(clocks, config);
                }
                if let Some(config) = self.ble_lp_clk {
                    configure_ble_lp_clk(clocks, config);
                }
                if let Some(config) = self.rtc_fast_clk {
                    configure_rtc_fast_clk(clocks, config);
                }
                if let Some(config) = self.timg_calibration_clock {
                    configure_timg_calibration_clock(clocks, config);
                }
            }
        }
        fn increment_reference_count(refcount: &mut u32) -> bool {
            let first = *refcount == 0;
            *refcount = unwrap!(refcount.checked_add(1), "Reference count overflow");
            first
        }
        fn decrement_reference_count(refcount: &mut u32) -> bool {
            *refcount = refcount.saturating_sub(1);
            let last = *refcount == 0;
            last
        }
        fn refresh_xtal_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.xtal_clk {
                XTAL_CLK_FREQ_CACHE.store(
                    xtal_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_pll_clk_downstream(clocks);
            refresh_syscon_pre_div_in_downstream(clocks);
            refresh_ble_lp_clk_downstream(clocks);
            refresh_rtc_fast_clk_downstream(clocks);
        }
        fn refresh_pll_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.pll_clk {
                PLL_CLK_FREQ_CACHE.store(
                    pll_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_apll_clk_downstream(clocks);
            refresh_cpu_pll_div_in_downstream(clocks);
            for child_instance in [I2sInstance::I2s0, I2sInstance::I2s1] {
                refresh_i2s_mclk_downstream(clocks, child_instance);
            }
        }
        fn refresh_apll_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.apll_clk {
                APLL_CLK_FREQ_CACHE.store(
                    apll_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_cpu_pll_div_in_downstream(clocks);
            for child_instance in [I2sInstance::I2s0, I2sInstance::I2s1] {
                refresh_i2s_mclk_downstream(clocks, child_instance);
            }
        }
        fn refresh_rc_fast_clk_downstream(clocks: &mut ClockTree) {
            refresh_syscon_pre_div_in_downstream(clocks);
            refresh_rtc_slow_clk_downstream(clocks);
            refresh_rtc_fast_clk_downstream(clocks);
            refresh_timg_calibration_clock_downstream(clocks);
        }
        fn refresh_cpu_pll_div_in_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.cpu_pll_div_in {
                CPU_PLL_DIV_IN_FREQ_CACHE.store(
                    cpu_pll_div_in_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_cpu_pll_div_downstream(clocks);
        }
        fn refresh_cpu_pll_div_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.cpu_pll_div {
                CPU_PLL_DIV_FREQ_CACHE.store(
                    cpu_pll_div_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_cpu_clk_downstream(clocks);
        }
        fn refresh_syscon_pre_div_in_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.syscon_pre_div_in {
                SYSCON_PRE_DIV_IN_FREQ_CACHE.store(
                    syscon_pre_div_in_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_syscon_pre_div_downstream(clocks);
        }
        fn refresh_syscon_pre_div_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.syscon_pre_div {
                SYSCON_PRE_DIV_FREQ_CACHE.store(
                    syscon_pre_div_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_cpu_clk_downstream(clocks);
        }
        fn refresh_cpu_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.cpu_clk {
                CPU_CLK_FREQ_CACHE.store(
                    cpu_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_apb_clk_downstream(clocks);
        }
        fn refresh_rc_slow_clk_downstream(clocks: &mut ClockTree) {
            refresh_rtc_slow_clk_downstream(clocks);
            refresh_timg_calibration_clock_downstream(clocks);
        }
        fn refresh_rtc_slow_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.rtc_slow_clk {
                RTC_SLOW_CLK_FREQ_CACHE.store(
                    rtc_slow_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_ble_lp_clk_downstream(clocks);
        }
        fn refresh_ble_lp_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.ble_lp_clk {
                BLE_LP_CLK_FREQ_CACHE.store(
                    ble_lp_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_rtc_fast_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.rtc_fast_clk {
                RTC_FAST_CLK_FREQ_CACHE.store(
                    rtc_fast_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_timg_calibration_clock_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.timg_calibration_clock {
                TIMG_CALIBRATION_CLOCK_FREQ_CACHE.store(
                    timg_calibration_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_i2s_mclk_downstream(clocks: &mut ClockTree, instance: I2sInstance) {
            if let Some(config) = clocks.i2s_mclk[instance as usize] {
                I2S_MCLK_FREQ_CACHE[instance as usize].store(
                    I2sInstance::mclk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_apb_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.apb_clk {
                APB_CLK_FREQ_CACHE.store(
                    apb_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_ref_tick_xtal_downstream(clocks);
            refresh_ref_tick_fosc_downstream(clocks);
            refresh_ref_tick_apll_downstream(clocks);
            refresh_ref_tick_pll_downstream(clocks);
            for child_instance in [I2cInstance::I2c0, I2cInstance::I2c1] {
                refresh_i2c_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [RmtInstance::Rmt] {
                refresh_rmt_sclk_downstream(clocks, child_instance);
            }
            for child_instance in [
                UartInstance::Uart0,
                UartInstance::Uart1,
                UartInstance::Uart2,
            ] {
                refresh_uart_function_clock_downstream(clocks, child_instance);
            }
        }
        fn refresh_ref_tick_xtal_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.ref_tick_xtal {
                REF_TICK_XTAL_FREQ_CACHE.store(
                    ref_tick_xtal_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_ref_tick_downstream(clocks);
        }
        fn refresh_ref_tick_fosc_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.ref_tick_fosc {
                REF_TICK_FOSC_FREQ_CACHE.store(
                    ref_tick_fosc_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_ref_tick_downstream(clocks);
        }
        fn refresh_ref_tick_apll_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.ref_tick_apll {
                REF_TICK_APLL_FREQ_CACHE.store(
                    ref_tick_apll_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_ref_tick_downstream(clocks);
        }
        fn refresh_ref_tick_pll_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.ref_tick_pll {
                REF_TICK_PLL_FREQ_CACHE.store(
                    ref_tick_pll_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_ref_tick_downstream(clocks);
        }
        fn refresh_i2c_function_clock_downstream(clocks: &mut ClockTree, instance: I2cInstance) {}
        fn refresh_ref_tick_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.ref_tick {
                REF_TICK_FREQ_CACHE.store(
                    ref_tick_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            for child_instance in [RmtInstance::Rmt] {
                refresh_rmt_sclk_downstream(clocks, child_instance);
            }
            for child_instance in [
                UartInstance::Uart0,
                UartInstance::Uart1,
                UartInstance::Uart2,
            ] {
                refresh_uart_function_clock_downstream(clocks, child_instance);
            }
        }
        fn refresh_rmt_sclk_downstream(clocks: &mut ClockTree, instance: RmtInstance) {
            if let Some(config) = clocks.rmt_sclk[instance as usize] {
                RMT_SCLK_FREQ_CACHE[instance as usize].store(
                    RmtInstance::sclk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_uart_function_clock_downstream(clocks: &mut ClockTree, instance: UartInstance) {
            if let Some(config) = clocks.uart_function_clock[instance as usize] {
                UART_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    UartInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_uart_baud_rate_generator_downstream(clocks, instance);
        }
        fn refresh_uart_baud_rate_generator_downstream(
            clocks: &mut ClockTree,
            instance: UartInstance,
        ) {
            if let Some(config) = clocks.uart_baud_rate_generator[instance as usize] {
                UART_BAUD_RATE_GENERATOR_FREQ_CACHE[instance as usize].store(
                    instance.baud_rate_generator_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
    };
}
/// Implement the `Peripheral` enum and enable/disable/reset functions.
///
/// This macro is intended to be placed in `esp_hal::system`.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! implement_peripheral_clocks {
    () => {
        #[doc(hidden)]
        #[derive(Debug, Clone, Copy, PartialEq, Eq)]
        #[repr(u8)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum Peripheral {
            /// AES peripheral clock signal
            Aes,
            /// EMAC peripheral clock signal
            Emac,
            /// GPIO_SD peripheral clock signal
            GpioSd,
            /// I2C_EXT0 peripheral clock signal
            I2cExt0,
            /// I2C_EXT1 peripheral clock signal
            I2cExt1,
            /// I2S0 peripheral clock signal
            I2s0,
            /// I2S1 peripheral clock signal
            I2s1,
            /// LEDC peripheral clock signal
            Ledc,
            /// MCPWM0 peripheral clock signal
            Mcpwm0,
            /// MCPWM1 peripheral clock signal
            Mcpwm1,
            /// PCNT peripheral clock signal
            Pcnt,
            /// RMT peripheral clock signal
            Rmt,
            /// RSA peripheral clock signal
            Rsa,
            /// SDIO_HOST peripheral clock signal
            SdioHost,
            /// SHA peripheral clock signal
            Sha,
            /// SPI2 peripheral clock signal
            Spi2,
            /// SPI3 peripheral clock signal
            Spi3,
            /// SPI_DMA peripheral clock signal
            SpiDma,
            /// TIMG0 peripheral clock signal
            Timg0,
            /// TIMG1 peripheral clock signal
            Timg1,
            /// TWAI0 peripheral clock signal
            Twai0,
            /// UART0 peripheral clock signal
            Uart0,
            /// UART1 peripheral clock signal
            Uart1,
            /// UART2 peripheral clock signal
            Uart2,
            /// UART_MEM peripheral clock signal
            UartMem,
            /// UHCI0 peripheral clock signal
            Uhci0,
            /// UHCI1 peripheral clock signal
            Uhci1,
        }
        impl Peripheral {
            const KEEP_ENABLED: &[Peripheral] = &[Self::Timg0, Self::Uart0, Self::UartMem];
            const COUNT: usize = Self::ALL.len();
            const ALL: &[Self] = &[
                Self::Aes,
                Self::Emac,
                Self::GpioSd,
                Self::I2cExt0,
                Self::I2cExt1,
                Self::I2s0,
                Self::I2s1,
                Self::Ledc,
                Self::Mcpwm0,
                Self::Mcpwm1,
                Self::Pcnt,
                Self::Rmt,
                Self::Rsa,
                Self::SdioHost,
                Self::Sha,
                Self::Spi2,
                Self::Spi3,
                Self::SpiDma,
                Self::Timg0,
                Self::Timg1,
                Self::Twai0,
                Self::Uart0,
                Self::Uart1,
                Self::Uart2,
                Self::UartMem,
                Self::Uhci0,
                Self::Uhci1,
            ];
        }
        unsafe fn enable_internal_racey(peripheral: Peripheral, enable: bool) {
            match peripheral {
                Peripheral::Aes => {
                    crate::peripherals::SYSTEM::regs()
                        .peri_clk_en()
                        .modify(|_, w| w.crypto_aes_clk_en().bit(enable));
                }
                Peripheral::Emac => {
                    crate::peripherals::SYSTEM::regs()
                        .wifi_clk_en()
                        .modify(|_, w| w.emac_clk_en().bit(enable));
                }
                Peripheral::GpioSd => {
                    let _ = enable;
                }
                Peripheral::I2cExt0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.i2c_ext0_clk_en().bit(enable));
                }
                Peripheral::I2cExt1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.i2c_ext1_clk_en().bit(enable));
                }
                Peripheral::I2s0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.i2s0_clk_en().bit(enable));
                }
                Peripheral::I2s1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.i2s1_clk_en().bit(enable));
                }
                Peripheral::Ledc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.ledc_clk_en().bit(enable));
                }
                Peripheral::Mcpwm0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.pwm0_clk_en().bit(enable));
                }
                Peripheral::Mcpwm1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.pwm1_clk_en().bit(enable));
                }
                Peripheral::Pcnt => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.pcnt_clk_en().bit(enable));
                }
                Peripheral::Rmt => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.rmt_clk_en().bit(enable));
                }
                Peripheral::Rsa => {
                    crate::peripherals::SYSTEM::regs()
                        .peri_clk_en()
                        .modify(|_, w| w.crypto_rsa_clk_en().bit(enable));
                }
                Peripheral::SdioHost => {
                    crate::peripherals::SYSTEM::regs()
                        .wifi_clk_en()
                        .modify(|_, w| w.sdio_host_clk_en().bit(enable));
                }
                Peripheral::Sha => {
                    crate::peripherals::SYSTEM::regs()
                        .peri_clk_en()
                        .modify(|_, w| w.crypto_sha_clk_en().bit(enable));
                }
                Peripheral::Spi2 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.spi2_clk_en().bit(enable));
                }
                Peripheral::Spi3 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.spi3_clk_en().bit(enable));
                }
                Peripheral::SpiDma => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.spi_dma_clk_en().bit(enable));
                }
                Peripheral::Timg0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.timergroup_clk_en().bit(enable));
                }
                Peripheral::Timg1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.timergroup1_clk_en().bit(enable));
                }
                Peripheral::Twai0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.twai_clk_en().bit(enable));
                }
                Peripheral::Uart0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.uart_clk_en().bit(enable));
                }
                Peripheral::Uart1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.uart1_clk_en().bit(enable));
                }
                Peripheral::Uart2 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.uart2_clk_en().bit(enable));
                }
                Peripheral::UartMem => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.uart_mem_clk_en().bit(enable));
                }
                Peripheral::Uhci0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.uhci0_clk_en().bit(enable));
                }
                Peripheral::Uhci1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en()
                        .modify(|_, w| w.uhci1_clk_en().bit(enable));
                }
            }
        }
        unsafe fn assert_peri_reset_racey(peripheral: Peripheral, reset: bool) {
            match peripheral {
                Peripheral::Aes => {
                    crate::peripherals::SYSTEM::regs()
                        .peri_rst_en()
                        .modify(|_, w| w.crypto_aes_rst().bit(reset));
                }
                Peripheral::Emac => {
                    crate::peripherals::SYSTEM::regs()
                        .wifi_rst_en()
                        .modify(|_, w| w.emac_rst().bit(reset));
                }
                Peripheral::GpioSd => {
                    let _ = reset;
                }
                Peripheral::I2cExt0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.i2c_ext0_rst().bit(reset));
                }
                Peripheral::I2cExt1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.i2c_ext1_rst().bit(reset));
                }
                Peripheral::I2s0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.i2s0_rst().bit(reset));
                }
                Peripheral::I2s1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.i2s1_rst().bit(reset));
                }
                Peripheral::Ledc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.ledc_rst().bit(reset));
                }
                Peripheral::Mcpwm0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.pwm0_rst().bit(reset));
                }
                Peripheral::Mcpwm1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.pwm1_rst().bit(reset));
                }
                Peripheral::Pcnt => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.pcnt_rst().bit(reset));
                }
                Peripheral::Rmt => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.rmt_rst().bit(reset));
                }
                Peripheral::Rsa => {
                    crate::peripherals::SYSTEM::regs()
                        .peri_rst_en()
                        .modify(|_, w| w.crypto_rsa_rst().bit(reset));
                }
                Peripheral::SdioHost => {
                    crate::peripherals::SYSTEM::regs()
                        .wifi_rst_en()
                        .modify(|_, w| w.sdio_host_rst().bit(reset));
                }
                Peripheral::Sha => {
                    crate::peripherals::SYSTEM::regs()
                        .peri_rst_en()
                        .modify(|_, w| w.crypto_sha_rst().bit(reset));
                }
                Peripheral::Spi2 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.spi2_rst().bit(reset));
                }
                Peripheral::Spi3 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.spi3_rst().bit(reset));
                }
                Peripheral::SpiDma => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.spi_dma_rst().bit(reset));
                }
                Peripheral::Timg0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.timergroup_rst().bit(reset));
                }
                Peripheral::Timg1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.timergroup1_rst().bit(reset));
                }
                Peripheral::Twai0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.twai_rst().bit(reset));
                }
                Peripheral::Uart0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.uart_rst().bit(reset));
                }
                Peripheral::Uart1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.uart1_rst().bit(reset));
                }
                Peripheral::Uart2 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.uart2_rst().bit(reset));
                }
                Peripheral::UartMem => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.uart_mem_rst().bit(reset));
                }
                Peripheral::Uhci0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.uhci0_rst().bit(reset));
                }
                Peripheral::Uhci1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en()
                        .modify(|_, w| w.uhci1_rst().bit(reset));
                }
            }
        }
    };
}
/// Macro to get the address range of the given memory region.
///
/// This macro provides two syntax options for each memory region:
///
/// - `memory_range!("region_name")` returns the address range as a range expression (`start..end`).
/// - `memory_range!(size as str, "region_name")` returns the size of the region as a string
///   literal.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! memory_range {
    ("DRAM") => {
        0x3FFAE000..0x40000000
    };
    (size as str, "DRAM") => {
        "335872"
    };
    ("DRAM2_UNINIT") => {
        0x3FFE7E30..0x40000000
    };
    (size as str, "DRAM2_UNINIT") => {
        "98768"
    };
    ("IROM") => {
        0x400D0000..0x40400000
    };
    (size as str, "IROM") => {
        "3342336"
    };
    ("DROM") => {
        0x3F400000..0x3F800000
    };
    (size as str, "DROM") => {
        "4194304"
    };
}
/// This macro can be used to generate code for each peripheral instance of the I2C master driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($id:literal, $instance:ident, $sys:ident, $scl:ident, $sda:ident)`
///
/// Macro fragments:
/// - `$id`: the index of the I2C instance
/// - `$instance`: the name of the I2C instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$scl`, `$sda`: peripheral signal names.
///
/// Example data: `(0, I2C0, I2cExt0, I2CEXT0_SCL, I2CEXT0_SDA)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_i2c_master {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_i2c_master { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_i2c_master!((0, I2C0, I2cExt0, I2CEXT0_SCL,
        I2CEXT0_SDA)); _for_each_inner_i2c_master!((1, I2C1, I2cExt1, I2CEXT1_SCL,
        I2CEXT1_SDA)); _for_each_inner_i2c_master!((all(0, I2C0, I2cExt0, I2CEXT0_SCL,
        I2CEXT0_SDA), (1, I2C1, I2cExt1, I2CEXT1_SCL, I2CEXT1_SDA)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the I2S driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $mclk:ident, $bclk:ident, $ws:ident, $bclk_rx:ident,
/// $ws_rx:ident, [$($dout:ident),*], [$($din:ident),*], $pdm_tx:literal, $pdm_rx:literal,
/// $pcm2pdm:literal, $pdm2pcm:literal)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the I2S instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$mclk`: the MCLK output signal (a placeholder on chips without a GPIO-matrix MCLK).
/// - `$bclk`, `$ws`: TX bit clock and word select output signals.
/// - `$bclk_rx`, `$ws_rx`: RX bit clock and word select output signals.
/// - `$dout`, `$din`: data-out and data-in signal names.
/// - `$pdm_tx`, `$pdm_rx`: whether the instance supports PDM TX/RX.
/// - `$pcm2pdm`, `$pdm2pcm`: whether the instance supports the hardware PCM<->PDM format conversion
///   filter on TX/RX.
///
/// Example data:
/// - `(I2S0, I2s0, I2S_MCLK, I2SO_BCK, I2SO_WS, I2SI_BCK, I2SI_WS, [I2SO_SD], [I2SI_SD], true,
///   true, true, true)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_i2s {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_i2s { $(($pattern) => $code;)* ($other : tt) => {} }
        _for_each_inner_i2s!((I2S0)); _for_each_inner_i2s!((I2S1));
        _for_each_inner_i2s!((I2S0, I2s0, __NO_MCLK, I2S0O_BCK, I2S0O_WS, I2S0I_BCK,
        I2S0I_WS, [I2S0O_DATA_23], [I2S0I_DATA_15], true, true, true, true));
        _for_each_inner_i2s!((I2S1, I2s1, __NO_MCLK, I2S1O_BCK, I2S1O_WS, I2S1I_BCK,
        I2S1I_WS, [I2S1O_DATA_23], [I2S1I_DATA_15], true, false, false, false));
        _for_each_inner_i2s!((names(I2S0), (I2S1))); _for_each_inner_i2s!((all(I2S0,
        I2s0, __NO_MCLK, I2S0O_BCK, I2S0O_WS, I2S0I_BCK, I2S0I_WS, [I2S0O_DATA_23],
        [I2S0I_DATA_15], true, true, true, true), (I2S1, I2s1, __NO_MCLK, I2S1O_BCK,
        I2S1O_WS, I2S1I_BCK, I2S1I_WS, [I2S1O_DATA_23], [I2S1I_DATA_15], true, false,
        false, false)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the UART driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($id:literal, $instance:ident, $sys:ident, $rx:ident, $tx:ident, $cts:ident,
/// $rts:ident)`
///
/// Macro fragments:
///
/// - `$id`: the index of the UART instance
/// - `$instance`: the name of the UART instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$rx`, `$tx`, `$cts`, `$rts`: signal names.
///
/// Example data: `(0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_uart {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_uart { $(($pattern) => $code;)* ($other : tt) => {}
        } _for_each_inner_uart!((0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS,
        wakeup_source = true)); _for_each_inner_uart!((1, UART1, Uart1, U1RXD, U1TXD,
        U1CTS, U1RTS, wakeup_source = true)); _for_each_inner_uart!((2, UART2, Uart2,
        U2RXD, U2TXD, U2CTS, U2RTS, wakeup_source = false));
        _for_each_inner_uart!((all(0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS,
        wakeup_source = true), (1, UART1, Uart1, U1RXD, U1TXD, U1CTS, U1RTS,
        wakeup_source = true), (2, UART2, Uart2, U2RXD, U2TXD, U2CTS, U2RTS,
        wakeup_source = false)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the SPI master driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $sclk:ident [$($cs:ident),*] [$($sio:ident),*]
/// $($is_qspi:literal)?)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the SPI instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$cs`, `$sio`: chip select and SIO signal names.
/// - `$is_qspi`: a `true` literal present if the SPI instance supports QSPI.
///
/// Example data:
/// - `(SPI2, Spi2, FSPICLK [FSPICS0, FSPICS1, FSPICS2, FSPICS3, FSPICS4, FSPICS5] [FSPID, FSPIQ,
///   FSPIWP, FSPIHD, FSPIIO4, FSPIIO5, FSPIIO6, FSPIIO7], true)`
/// - `(SPI3, Spi3, SPI3_CLK [SPI3_CS0, SPI3_CS1, SPI3_CS2] [SPI3_D, SPI3_Q])`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_spi_master {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_spi_master { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_spi_master!((SPI2)); _for_each_inner_spi_master!((SPI3));
        _for_each_inner_spi_master!((SPI2, Spi2, HSPICLK[HSPICS0, HSPICS1, HSPICS2]
        [HSPID, HSPIQ, HSPIWP, HSPIHD], true)); _for_each_inner_spi_master!((SPI3, Spi3,
        VSPICLK[VSPICS0, VSPICS1, VSPICS2] [VSPID, VSPIQ, VSPIWP, VSPIHD], true));
        _for_each_inner_spi_master!((names(SPI2), (SPI3)));
        _for_each_inner_spi_master!((all(SPI2, Spi2, HSPICLK[HSPICS0, HSPICS1, HSPICS2]
        [HSPID, HSPIQ, HSPIWP, HSPIHD], true), (SPI3, Spi3, VSPICLK[VSPICS0, VSPICS1,
        VSPICS2] [VSPID, VSPIQ, VSPIWP, VSPIHD], true)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the SPI slave driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $sclk:ident, $mosi:ident, $miso:ident, $cs:ident)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the SPI instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$sclk`, `$mosi`, `$miso`, `$cs`: signal names.
///
/// Example data: `(SPI2, Spi2, FSPICLK, FSPID, FSPIQ, FSPICS0)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_spi_slave {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_spi_slave { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_spi_slave!((SPI2)); _for_each_inner_spi_slave!((SPI3));
        _for_each_inner_spi_slave!((SPI2, Spi2, HSPICLK, HSPID, HSPIQ, HSPICS0));
        _for_each_inner_spi_slave!((SPI3, Spi3, VSPICLK, VSPID, VSPIQ, VSPICS0));
        _for_each_inner_spi_slave!((names(SPI2), (SPI3)));
        _for_each_inner_spi_slave!((all(SPI2, Spi2, HSPICLK, HSPID, HSPIQ, HSPICS0),
        (SPI3, Spi3, VSPICLK, VSPID, VSPIQ, VSPICS0)));
    };
}
/// This macro can be used to generate code for each PCNT unit.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has four options for its "Individual matcher" case:
///
/// - `names`: `($instance:ident)`
/// - `all`: `($peri:ident, $variant:ident, $sys:ident, $regs:ident, $unit:literal,
///   $interrupt:ident, $sig_ch0:ident, $sig_ch1:ident, $ctrl_ch0:ident, $ctrl_ch1:ident)`
/// - `interrupt`: `($interrupt:ident)` (repeated: one ident per unique IRQ)
/// - `regs`: `($regs:ident)` (repeated: one ident per register block)
///
/// Macro fragments:
///
/// - `$peri`: unit singleton name (`PCNT0_UNIT0`, `PCNT1_UNIT0`, …)
/// - `$variant`: `AnyPcntUnit` enum variant (`Pcnt0Unit0`, `Pcnt1Unit0`, …)
/// - `$sys`: `esp_hal::system::Peripheral` variant for clocks
/// - `$regs`: register-block singleton (`PCNT`, `PCNT1`)
/// - `$unit`: hardware unit index within that register block
/// - `$interrupt`: shared peripheral interrupt
/// - `$sig_ch0`, `$sig_ch1`, `$ctrl_ch0`, `$ctrl_ch1`: GPIO matrix input signals
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_pcnt_unit {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_pcnt_unit { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_pcnt_unit!((PCNT0_UNIT0));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT2));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT3));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT4));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT5));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT6));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT7));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT0, Pcnt0Unit0, Pcnt, PCNT, 0, PCNT,
        PCNT0_SIG_CH0, PCNT0_SIG_CH1, PCNT0_CTRL_CH0, PCNT0_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT1, Pcnt0Unit1, Pcnt, PCNT, 1, PCNT,
        PCNT1_SIG_CH0, PCNT1_SIG_CH1, PCNT1_CTRL_CH0, PCNT1_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT2, Pcnt0Unit2, Pcnt, PCNT, 2, PCNT,
        PCNT2_SIG_CH0, PCNT2_SIG_CH1, PCNT2_CTRL_CH0, PCNT2_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT3, Pcnt0Unit3, Pcnt, PCNT, 3, PCNT,
        PCNT3_SIG_CH0, PCNT3_SIG_CH1, PCNT3_CTRL_CH0, PCNT3_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT4, Pcnt0Unit4, Pcnt, PCNT, 4, PCNT,
        PCNT4_SIG_CH0, PCNT4_SIG_CH1, PCNT4_CTRL_CH0, PCNT4_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT5, Pcnt0Unit5, Pcnt, PCNT, 5, PCNT,
        PCNT5_SIG_CH0, PCNT5_SIG_CH1, PCNT5_CTRL_CH0, PCNT5_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT6, Pcnt0Unit6, Pcnt, PCNT, 6, PCNT,
        PCNT6_SIG_CH0, PCNT6_SIG_CH1, PCNT6_CTRL_CH0, PCNT6_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT0_UNIT7, Pcnt0Unit7, Pcnt, PCNT, 7, PCNT,
        PCNT7_SIG_CH0, PCNT7_SIG_CH1, PCNT7_CTRL_CH0, PCNT7_CTRL_CH1));
        _for_each_inner_pcnt_unit!((PCNT)); _for_each_inner_pcnt_unit!((PCNT));
        _for_each_inner_pcnt_unit!((names(PCNT0_UNIT0), (PCNT0_UNIT1), (PCNT0_UNIT2),
        (PCNT0_UNIT3), (PCNT0_UNIT4), (PCNT0_UNIT5), (PCNT0_UNIT6), (PCNT0_UNIT7)));
        _for_each_inner_pcnt_unit!((all(PCNT0_UNIT0, Pcnt0Unit0, Pcnt, PCNT, 0, PCNT,
        PCNT0_SIG_CH0, PCNT0_SIG_CH1, PCNT0_CTRL_CH0, PCNT0_CTRL_CH1), (PCNT0_UNIT1,
        Pcnt0Unit1, Pcnt, PCNT, 1, PCNT, PCNT1_SIG_CH0, PCNT1_SIG_CH1, PCNT1_CTRL_CH0,
        PCNT1_CTRL_CH1), (PCNT0_UNIT2, Pcnt0Unit2, Pcnt, PCNT, 2, PCNT, PCNT2_SIG_CH0,
        PCNT2_SIG_CH1, PCNT2_CTRL_CH0, PCNT2_CTRL_CH1), (PCNT0_UNIT3, Pcnt0Unit3, Pcnt,
        PCNT, 3, PCNT, PCNT3_SIG_CH0, PCNT3_SIG_CH1, PCNT3_CTRL_CH0, PCNT3_CTRL_CH1),
        (PCNT0_UNIT4, Pcnt0Unit4, Pcnt, PCNT, 4, PCNT, PCNT4_SIG_CH0, PCNT4_SIG_CH1,
        PCNT4_CTRL_CH0, PCNT4_CTRL_CH1), (PCNT0_UNIT5, Pcnt0Unit5, Pcnt, PCNT, 5, PCNT,
        PCNT5_SIG_CH0, PCNT5_SIG_CH1, PCNT5_CTRL_CH0, PCNT5_CTRL_CH1), (PCNT0_UNIT6,
        Pcnt0Unit6, Pcnt, PCNT, 6, PCNT, PCNT6_SIG_CH0, PCNT6_SIG_CH1, PCNT6_CTRL_CH0,
        PCNT6_CTRL_CH1), (PCNT0_UNIT7, Pcnt0Unit7, Pcnt, PCNT, 7, PCNT, PCNT7_SIG_CH0,
        PCNT7_SIG_CH1, PCNT7_CTRL_CH0, PCNT7_CTRL_CH1)));
        _for_each_inner_pcnt_unit!((interrupt(PCNT)));
        _for_each_inner_pcnt_unit!((regs(PCNT)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_peripheral {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_peripheral { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO0 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO0 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO1 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO1 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO2 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO2 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO3 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO3 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO4 peripheral singleton"]
        GPIO4 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO5 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO5 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO6 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO6 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO7 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO7 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO8 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO8 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO9 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO9 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO10 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO10 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO11 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO11 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO12 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO12 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO13 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO13 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO14 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO14 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO15 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO15 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO16 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO16 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO17 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO17 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO18 peripheral singleton"]
        GPIO18 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO19 peripheral singleton"] GPIO19 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO20 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc = "<li>This pin is only available on ESP32-PICO-V3.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO20 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO21 peripheral singleton"]
        GPIO21 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO22 peripheral singleton"] GPIO22 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO23 peripheral singleton"]
        GPIO23 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO25 peripheral singleton"] GPIO25 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO26 peripheral singleton"]
        GPIO26 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO27 peripheral singleton"] GPIO27 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO32 peripheral singleton"]
        GPIO32 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO33 peripheral singleton"] GPIO33 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO34 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc = "<li>This pin can only be used as an input.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO34 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO35 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc = "<li>This pin can only be used as an input.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO35 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO36 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc = "<li>This pin can only be used as an input.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO36 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO37 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc = "<li>This pin can only be used as an input.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO37 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO38 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc = "<li>This pin can only be used as an input.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO38 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO39 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc = "<li>This pin can only be used as an input.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO39 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA_SPI2 peripheral singleton"]
        DMA_SPI2 <= SPI2(SPI2_DMA : { bind_dma_interrupt, enable_dma_interrupt,
        disable_dma_interrupt }) (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "DMA_SPI3 peripheral singleton"] DMA_SPI3 <= SPI3(SPI3_DMA : {
        bind_dma_interrupt, enable_dma_interrupt, disable_dma_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA_I2S0 peripheral singleton"]
        DMA_I2S0 <= I2S0(I2S0 : { bind_dma_interrupt, enable_dma_interrupt,
        disable_dma_interrupt }) (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "DMA_I2S1 peripheral singleton"] DMA_I2S1 <= I2S1(I2S1 : {
        bind_dma_interrupt, enable_dma_interrupt, disable_dma_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT0 peripheral singleton"] PCNT0_UNIT0 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT1 peripheral singleton"] PCNT0_UNIT1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT2 peripheral singleton"] PCNT0_UNIT2 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT3 peripheral singleton"] PCNT0_UNIT3 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT4 peripheral singleton"] PCNT0_UNIT4 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT5 peripheral singleton"] PCNT0_UNIT5 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT6 peripheral singleton"] PCNT0_UNIT6 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCNT0_UNIT7 peripheral singleton"] PCNT0_UNIT7 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SDM_CH0 peripheral singleton"]
        SDM_CH0 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "SDM_CH1 peripheral singleton"] SDM_CH1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SDM_CH2 peripheral singleton"]
        SDM_CH2 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "SDM_CH3 peripheral singleton"] SDM_CH3 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SDM_CH4 peripheral singleton"]
        SDM_CH4 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "SDM_CH5 peripheral singleton"] SDM_CH5 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SDM_CH6 peripheral singleton"]
        SDM_CH6 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "SDM_CH7 peripheral singleton"] SDM_CH7 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "AES peripheral singleton"] AES
        <= AES() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "APB_CTRL peripheral singleton"] APB_CTRL <= APB_CTRL() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "BB peripheral singleton"] BB <=
        BB() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "DPORT peripheral singleton"] DPORT <= DPORT() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SYSTEM peripheral singleton"]
        SYSTEM <= DPORT() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "EFUSE peripheral singleton"] EFUSE <= EFUSE() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "ETH peripheral singleton"] ETH
        <= virtual(ETH_MAC : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "EMAC_DMA peripheral singleton"] EMAC_DMA <= GMAC_DMA() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "EMAC_EXT peripheral singleton"]
        EMAC_EXT <= EMAC_EXT() (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "EMAC_MAC peripheral singleton"] EMAC_MAC <= GMAC() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FLASH_ENCRYPTION peripheral singleton"] FLASH_ENCRYPTION <= FLASH_ENCRYPTION()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "FRC_TIMER peripheral singleton"] FRC_TIMER <= FRC_TIMER() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO peripheral singleton"]
        GPIO <= GPIO() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO_SD peripheral singleton"] GPIO_SD <= GPIO_SD() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "HINF peripheral singleton"]
        HINF <= HINF() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "I2C0 peripheral singleton"] I2C0 <= I2C0(I2C_EXT0 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "I2C1 peripheral singleton"]
        I2C1 <= I2C1(I2C_EXT1 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "I2S0 peripheral singleton"] I2S0 <= I2S0(I2S0 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "I2S1 peripheral singleton"]
        I2S1 <= I2S1(I2S1 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "IO_MUX peripheral singleton"] IO_MUX <= IO_MUX() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LEDC peripheral singleton"]
        LEDC <= LEDC() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "MCPWM0 peripheral singleton"] MCPWM0 <= MCPWM0() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "MMU_TABLE peripheral singleton"] MMU_TABLE <= MMU_TABLE() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "MCPWM1 peripheral singleton"]
        MCPWM1 <= MCPWM1() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "NRX peripheral singleton"] NRX <= NRX() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "PCNT peripheral singleton"]
        PCNT <= PCNT(PCNT : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "RMT peripheral singleton"] RMT <= RMT() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "RNG peripheral singleton"] RNG
        <= RNG() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "RSA peripheral singleton"] RSA <= RSA(RSA : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LPWR peripheral singleton"]
        LPWR <= RTC_CNTL() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "RTC_TIMER peripheral singleton"] RTC_TIMER <= RTC_CNTL() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LP_I2C0 peripheral singleton"]
        LP_I2C0 <= RTC_I2C() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "RTC_IO peripheral singleton"] RTC_IO <= RTC_IO() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SDHOST peripheral singleton"]
        SDHOST <= SDHOST() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SENS peripheral singleton"] SENS <= SENS() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SHA peripheral singleton"] SHA
        <= SHA() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SLC peripheral singleton"] SLC <= SLC() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SLCHOST peripheral singleton"]
        SLCHOST <= SLCHOST() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "SPI0 peripheral singleton"] SPI0 <= SPI0() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SPI1 peripheral singleton"]
        SPI1 <= SPI1() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SPI2 peripheral singleton"] SPI2 <= SPI2(SPI2_DMA : { bind_dma_interrupt,
        enable_dma_interrupt, disable_dma_interrupt }, SPI2 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SPI3 peripheral singleton"]
        SPI3 <= SPI3(SPI3_DMA : { bind_dma_interrupt, enable_dma_interrupt,
        disable_dma_interrupt }, SPI3 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "TIMG0 peripheral singleton"] TIMG0 <= TIMG0() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "TIMG1 peripheral singleton"]
        TIMG1 <= TIMG1() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "TWAI0 peripheral singleton"] TWAI0 <= TWAI0() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "UART0 peripheral singleton"]
        UART0 <= UART0(UART0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "UART1 peripheral singleton"] UART1 <= UART1(UART1 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "UART2 peripheral singleton"]
        UART2 <= UART2(UART2 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "UHCI0 peripheral singleton"] UHCI0 <= UHCI0() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "UHCI1 peripheral singleton"]
        UHCI1 <= UHCI1() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "WIFI peripheral singleton"] WIFI <= WIFI(WIFI_MAC : { bind_mac_interrupt,
        enable_mac_interrupt, disable_mac_interrupt }))); _for_each_inner_peripheral!((@
        peri_type #[doc = "ADC1 peripheral singleton"] ADC1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "ADC2 peripheral singleton"]
        ADC2 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "BT peripheral singleton"] BT <= virtual(BT_BB : { bind_bb_interrupt,
        enable_bb_interrupt, disable_bb_interrupt }, RWBLE : { bind_rwble_interrupt,
        enable_rwble_interrupt, disable_rwble_interrupt }, RWBT : { bind_rwbt_interrupt,
        enable_rwbt_interrupt, disable_rwbt_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "CPU_CTRL peripheral singleton"]
        CPU_CTRL <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "DAC1 peripheral singleton"] DAC1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DAC2 peripheral singleton"]
        DAC2 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "FLASH peripheral singleton"] FLASH <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "PSRAM peripheral singleton"]
        PSRAM <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "TOUCH peripheral singleton"] TOUCH <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "IPC peripheral singleton"] IPC
        <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR0 peripheral singleton"] FROM_CPU_INTR0 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR1 peripheral singleton"] FROM_CPU_INTR1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR2 peripheral singleton"] FROM_CPU_INTR2 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR3 peripheral singleton"] FROM_CPU_INTR3 <= virtual() (unstable)));
        _for_each_inner_peripheral!((GPIO0)); _for_each_inner_peripheral!((GPIO1));
        _for_each_inner_peripheral!((GPIO2)); _for_each_inner_peripheral!((GPIO3));
        _for_each_inner_peripheral!((GPIO4)); _for_each_inner_peripheral!((GPIO5));
        _for_each_inner_peripheral!((GPIO6)); _for_each_inner_peripheral!((GPIO7));
        _for_each_inner_peripheral!((GPIO8)); _for_each_inner_peripheral!((GPIO9));
        _for_each_inner_peripheral!((GPIO10)); _for_each_inner_peripheral!((GPIO11));
        _for_each_inner_peripheral!((GPIO12)); _for_each_inner_peripheral!((GPIO13));
        _for_each_inner_peripheral!((GPIO14)); _for_each_inner_peripheral!((GPIO15));
        _for_each_inner_peripheral!((GPIO16)); _for_each_inner_peripheral!((GPIO17));
        _for_each_inner_peripheral!((GPIO18)); _for_each_inner_peripheral!((GPIO19));
        _for_each_inner_peripheral!((GPIO20)); _for_each_inner_peripheral!((GPIO21));
        _for_each_inner_peripheral!((GPIO22)); _for_each_inner_peripheral!((GPIO23));
        _for_each_inner_peripheral!((GPIO25)); _for_each_inner_peripheral!((GPIO26));
        _for_each_inner_peripheral!((GPIO27));
        _for_each_inner_peripheral!((#[cfg(not(use_xtal32k))] GPIO32));
        _for_each_inner_peripheral!((#[cfg(not(use_xtal32k))] GPIO33));
        _for_each_inner_peripheral!((GPIO34)); _for_each_inner_peripheral!((GPIO35));
        _for_each_inner_peripheral!((GPIO36)); _for_each_inner_peripheral!((GPIO37));
        _for_each_inner_peripheral!((GPIO38)); _for_each_inner_peripheral!((GPIO39));
        _for_each_inner_peripheral!((DMA_SPI2(unstable)));
        _for_each_inner_peripheral!((DMA_SPI3(unstable)));
        _for_each_inner_peripheral!((DMA_I2S0(unstable)));
        _for_each_inner_peripheral!((DMA_I2S1(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT0(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT1(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT2(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT3(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT4(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT5(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT6(unstable)));
        _for_each_inner_peripheral!((PCNT0_UNIT7(unstable)));
        _for_each_inner_peripheral!((SDM_CH0(unstable)));
        _for_each_inner_peripheral!((SDM_CH1(unstable)));
        _for_each_inner_peripheral!((SDM_CH2(unstable)));
        _for_each_inner_peripheral!((SDM_CH3(unstable)));
        _for_each_inner_peripheral!((SDM_CH4(unstable)));
        _for_each_inner_peripheral!((SDM_CH5(unstable)));
        _for_each_inner_peripheral!((SDM_CH6(unstable)));
        _for_each_inner_peripheral!((SDM_CH7(unstable)));
        _for_each_inner_peripheral!((AES(unstable)));
        _for_each_inner_peripheral!((APB_CTRL(unstable)));
        _for_each_inner_peripheral!((BB(unstable)));
        _for_each_inner_peripheral!((DPORT(unstable)));
        _for_each_inner_peripheral!((SYSTEM(unstable)));
        _for_each_inner_peripheral!((ETH(unstable)));
        _for_each_inner_peripheral!((FLASH_ENCRYPTION(unstable)));
        _for_each_inner_peripheral!((FRC_TIMER(unstable)));
        _for_each_inner_peripheral!((GPIO(unstable)));
        _for_each_inner_peripheral!((GPIO_SD(unstable)));
        _for_each_inner_peripheral!((HINF(unstable)));
        _for_each_inner_peripheral!((I2C0)); _for_each_inner_peripheral!((I2C1));
        _for_each_inner_peripheral!((I2S0(unstable)));
        _for_each_inner_peripheral!((I2S1(unstable)));
        _for_each_inner_peripheral!((IO_MUX(unstable)));
        _for_each_inner_peripheral!((LEDC(unstable)));
        _for_each_inner_peripheral!((MCPWM0(unstable)));
        _for_each_inner_peripheral!((MCPWM1(unstable)));
        _for_each_inner_peripheral!((NRX(unstable)));
        _for_each_inner_peripheral!((PCNT(unstable)));
        _for_each_inner_peripheral!((RMT(unstable)));
        _for_each_inner_peripheral!((RNG(unstable)));
        _for_each_inner_peripheral!((RSA(unstable)));
        _for_each_inner_peripheral!((LPWR(unstable)));
        _for_each_inner_peripheral!((RTC_TIMER(unstable)));
        _for_each_inner_peripheral!((LP_I2C0(unstable)));
        _for_each_inner_peripheral!((RTC_IO(unstable)));
        _for_each_inner_peripheral!((SDHOST(unstable)));
        _for_each_inner_peripheral!((SENS(unstable)));
        _for_each_inner_peripheral!((SHA(unstable)));
        _for_each_inner_peripheral!((SLC(unstable)));
        _for_each_inner_peripheral!((SLCHOST(unstable)));
        _for_each_inner_peripheral!((SPI0(unstable)));
        _for_each_inner_peripheral!((SPI1(unstable)));
        _for_each_inner_peripheral!((SPI2)); _for_each_inner_peripheral!((SPI3));
        _for_each_inner_peripheral!((TIMG0(unstable)));
        _for_each_inner_peripheral!((TIMG1(unstable)));
        _for_each_inner_peripheral!((TWAI0(unstable)));
        _for_each_inner_peripheral!((UART0)); _for_each_inner_peripheral!((UART1));
        _for_each_inner_peripheral!((UART2));
        _for_each_inner_peripheral!((UHCI0(unstable)));
        _for_each_inner_peripheral!((UHCI1(unstable)));
        _for_each_inner_peripheral!((WIFI));
        _for_each_inner_peripheral!((ADC1(unstable)));
        _for_each_inner_peripheral!((ADC2(unstable)));
        _for_each_inner_peripheral!((BT(unstable)));
        _for_each_inner_peripheral!((CPU_CTRL(unstable)));
        _for_each_inner_peripheral!((DAC1(unstable)));
        _for_each_inner_peripheral!((DAC2(unstable)));
        _for_each_inner_peripheral!((FLASH(unstable)));
        _for_each_inner_peripheral!((PSRAM(unstable)));
        _for_each_inner_peripheral!((TOUCH(unstable)));
        _for_each_inner_peripheral!((IPC(unstable)));
        _for_each_inner_peripheral!((FROM_CPU_INTR2(unstable)));
        _for_each_inner_peripheral!((FROM_CPU_INTR3(unstable)));
        _for_each_inner_peripheral!((SPI2, Spi2, 0, SpiDmaChannel));
        _for_each_inner_peripheral!((I2S0, I2s0, 0, I2sDmaChannel));
        _for_each_inner_peripheral!((SPI3, Spi3, 1, SpiDmaChannel));
        _for_each_inner_peripheral!((I2S1, I2s1, 1, I2sDmaChannel));
        _for_each_inner_peripheral!((all(@ peri_type #[doc =
        "GPIO0 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO0 <= virtual()), (@ peri_type #[doc =
        "GPIO1 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO1 <= virtual()), (@ peri_type #[doc =
        "GPIO2 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO2 <= virtual()), (@ peri_type #[doc =
        "GPIO3 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO3 <= virtual()), (@ peri_type #[doc =
        "GPIO4 peripheral singleton"] GPIO4 <= virtual()), (@ peri_type #[doc =
        "GPIO5 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO5 <= virtual()), (@ peri_type #[doc =
        "GPIO6 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO6 <= virtual()), (@ peri_type #[doc =
        "GPIO7 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO7 <= virtual()), (@ peri_type #[doc =
        "GPIO8 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO8 <= virtual()), (@ peri_type #[doc =
        "GPIO9 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO9 <= virtual()), (@ peri_type #[doc =
        "GPIO10 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO10 <= virtual()), (@ peri_type #[doc =
        "GPIO11 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO11 <= virtual()), (@ peri_type #[doc =
        "GPIO12 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO12 <= virtual()), (@ peri_type #[doc =
        "GPIO13 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO13 <= virtual()), (@ peri_type #[doc =
        "GPIO14 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO14 <= virtual()), (@ peri_type #[doc =
        "GPIO15 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO15 <= virtual()), (@ peri_type #[doc =
        "GPIO16 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO16 <= virtual()), (@ peri_type #[doc =
        "GPIO17 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO17 <= virtual()), (@ peri_type #[doc =
        "GPIO18 peripheral singleton"] GPIO18 <= virtual()), (@ peri_type #[doc =
        "GPIO19 peripheral singleton"] GPIO19 <= virtual()), (@ peri_type #[doc =
        "GPIO20 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc = "<li>This pin is only available on ESP32-PICO-V3.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO20 <= virtual()), (@ peri_type #[doc =
        "GPIO21 peripheral singleton"] GPIO21 <= virtual()), (@ peri_type #[doc =
        "GPIO22 peripheral singleton"] GPIO22 <= virtual()), (@ peri_type #[doc =
        "GPIO23 peripheral singleton"] GPIO23 <= virtual()), (@ peri_type #[doc =
        "GPIO25 peripheral singleton"] GPIO25 <= virtual()), (@ peri_type #[doc =
        "GPIO26 peripheral singleton"] GPIO26 <= virtual()), (@ peri_type #[doc =
        "GPIO27 peripheral singleton"] GPIO27 <= virtual()), (@ peri_type #[doc =
        "GPIO32 peripheral singleton"] GPIO32 <= virtual()), (@ peri_type #[doc =
        "GPIO33 peripheral singleton"] GPIO33 <= virtual()), (@ peri_type #[doc =
        "GPIO34 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc = "<li>This pin can only be used as an input.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO34 <= virtual()), (@ peri_type #[doc =
        "GPIO35 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc = "<li>This pin can only be used as an input.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO35 <= virtual()), (@ peri_type #[doc =
        "GPIO36 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc = "<li>This pin can only be used as an input.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO36 <= virtual()), (@ peri_type #[doc =
        "GPIO37 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc = "<li>This pin can only be used as an input.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO37 <= virtual()), (@ peri_type #[doc =
        "GPIO38 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc = "<li>This pin can only be used as an input.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO38 <= virtual()), (@ peri_type #[doc =
        "GPIO39 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc = "<li>This pin can only be used as an input.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO39 <= virtual()), (@ peri_type #[doc =
        "DMA_SPI2 peripheral singleton"] DMA_SPI2 <= SPI2(SPI2_DMA : {
        bind_dma_interrupt, enable_dma_interrupt, disable_dma_interrupt }) (unstable)),
        (@ peri_type #[doc = "DMA_SPI3 peripheral singleton"] DMA_SPI3 <= SPI3(SPI3_DMA :
        { bind_dma_interrupt, enable_dma_interrupt, disable_dma_interrupt }) (unstable)),
        (@ peri_type #[doc = "DMA_I2S0 peripheral singleton"] DMA_I2S0 <= I2S0(I2S0 : {
        bind_dma_interrupt, enable_dma_interrupt, disable_dma_interrupt }) (unstable)),
        (@ peri_type #[doc = "DMA_I2S1 peripheral singleton"] DMA_I2S1 <= I2S1(I2S1 : {
        bind_dma_interrupt, enable_dma_interrupt, disable_dma_interrupt }) (unstable)),
        (@ peri_type #[doc = "PCNT0_UNIT0 peripheral singleton"] PCNT0_UNIT0 <= virtual()
        (unstable)), (@ peri_type #[doc = "PCNT0_UNIT1 peripheral singleton"] PCNT0_UNIT1
        <= virtual() (unstable)), (@ peri_type #[doc =
        "PCNT0_UNIT2 peripheral singleton"] PCNT0_UNIT2 <= virtual() (unstable)), (@
        peri_type #[doc = "PCNT0_UNIT3 peripheral singleton"] PCNT0_UNIT3 <= virtual()
        (unstable)), (@ peri_type #[doc = "PCNT0_UNIT4 peripheral singleton"] PCNT0_UNIT4
        <= virtual() (unstable)), (@ peri_type #[doc =
        "PCNT0_UNIT5 peripheral singleton"] PCNT0_UNIT5 <= virtual() (unstable)), (@
        peri_type #[doc = "PCNT0_UNIT6 peripheral singleton"] PCNT0_UNIT6 <= virtual()
        (unstable)), (@ peri_type #[doc = "PCNT0_UNIT7 peripheral singleton"] PCNT0_UNIT7
        <= virtual() (unstable)), (@ peri_type #[doc = "SDM_CH0 peripheral singleton"]
        SDM_CH0 <= virtual() (unstable)), (@ peri_type #[doc =
        "SDM_CH1 peripheral singleton"] SDM_CH1 <= virtual() (unstable)), (@ peri_type
        #[doc = "SDM_CH2 peripheral singleton"] SDM_CH2 <= virtual() (unstable)), (@
        peri_type #[doc = "SDM_CH3 peripheral singleton"] SDM_CH3 <= virtual()
        (unstable)), (@ peri_type #[doc = "SDM_CH4 peripheral singleton"] SDM_CH4 <=
        virtual() (unstable)), (@ peri_type #[doc = "SDM_CH5 peripheral singleton"]
        SDM_CH5 <= virtual() (unstable)), (@ peri_type #[doc =
        "SDM_CH6 peripheral singleton"] SDM_CH6 <= virtual() (unstable)), (@ peri_type
        #[doc = "SDM_CH7 peripheral singleton"] SDM_CH7 <= virtual() (unstable)), (@
        peri_type #[doc = "AES peripheral singleton"] AES <= AES() (unstable)), (@
        peri_type #[doc = "APB_CTRL peripheral singleton"] APB_CTRL <= APB_CTRL()
        (unstable)), (@ peri_type #[doc = "BB peripheral singleton"] BB <= BB()
        (unstable)), (@ peri_type #[doc = "DPORT peripheral singleton"] DPORT <= DPORT()
        (unstable)), (@ peri_type #[doc = "SYSTEM peripheral singleton"] SYSTEM <=
        DPORT() (unstable)), (@ peri_type #[doc = "EFUSE peripheral singleton"] EFUSE <=
        EFUSE() (unstable)), (@ peri_type #[doc = "ETH peripheral singleton"] ETH <=
        virtual(ETH_MAC : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable)), (@ peri_type #[doc =
        "EMAC_DMA peripheral singleton"] EMAC_DMA <= GMAC_DMA() (unstable)), (@ peri_type
        #[doc = "EMAC_EXT peripheral singleton"] EMAC_EXT <= EMAC_EXT() (unstable)), (@
        peri_type #[doc = "EMAC_MAC peripheral singleton"] EMAC_MAC <= GMAC()
        (unstable)), (@ peri_type #[doc = "FLASH_ENCRYPTION peripheral singleton"]
        FLASH_ENCRYPTION <= FLASH_ENCRYPTION() (unstable)), (@ peri_type #[doc =
        "FRC_TIMER peripheral singleton"] FRC_TIMER <= FRC_TIMER() (unstable)), (@
        peri_type #[doc = "GPIO peripheral singleton"] GPIO <= GPIO() (unstable)), (@
        peri_type #[doc = "GPIO_SD peripheral singleton"] GPIO_SD <= GPIO_SD()
        (unstable)), (@ peri_type #[doc = "HINF peripheral singleton"] HINF <= HINF()
        (unstable)), (@ peri_type #[doc = "I2C0 peripheral singleton"] I2C0 <=
        I2C0(I2C_EXT0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "I2C1 peripheral singleton"]
        I2C1 <= I2C1(I2C_EXT1 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "I2S0 peripheral singleton"]
        I2S0 <= I2S0(I2S0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }) (unstable)), (@ peri_type #[doc =
        "I2S1 peripheral singleton"] I2S1 <= I2S1(I2S1 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)), (@ peri_type #[doc
        = "IO_MUX peripheral singleton"] IO_MUX <= IO_MUX() (unstable)), (@ peri_type
        #[doc = "LEDC peripheral singleton"] LEDC <= LEDC() (unstable)), (@ peri_type
        #[doc = "MCPWM0 peripheral singleton"] MCPWM0 <= MCPWM0() (unstable)), (@
        peri_type #[doc = "MMU_TABLE peripheral singleton"] MMU_TABLE <= MMU_TABLE()
        (unstable)), (@ peri_type #[doc = "MCPWM1 peripheral singleton"] MCPWM1 <=
        MCPWM1() (unstable)), (@ peri_type #[doc = "NRX peripheral singleton"] NRX <=
        NRX() (unstable)), (@ peri_type #[doc = "PCNT peripheral singleton"] PCNT <=
        PCNT(PCNT : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt
        }) (unstable)), (@ peri_type #[doc = "RMT peripheral singleton"] RMT <= RMT()
        (unstable)), (@ peri_type #[doc = "RNG peripheral singleton"] RNG <= RNG()
        (unstable)), (@ peri_type #[doc = "RSA peripheral singleton"] RSA <= RSA(RSA : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "LPWR peripheral singleton"] LPWR <= RTC_CNTL()
        (unstable)), (@ peri_type #[doc = "RTC_TIMER peripheral singleton"] RTC_TIMER <=
        RTC_CNTL() (unstable)), (@ peri_type #[doc = "LP_I2C0 peripheral singleton"]
        LP_I2C0 <= RTC_I2C() (unstable)), (@ peri_type #[doc =
        "RTC_IO peripheral singleton"] RTC_IO <= RTC_IO() (unstable)), (@ peri_type #[doc
        = "SDHOST peripheral singleton"] SDHOST <= SDHOST() (unstable)), (@ peri_type
        #[doc = "SENS peripheral singleton"] SENS <= SENS() (unstable)), (@ peri_type
        #[doc = "SHA peripheral singleton"] SHA <= SHA() (unstable)), (@ peri_type #[doc
        = "SLC peripheral singleton"] SLC <= SLC() (unstable)), (@ peri_type #[doc =
        "SLCHOST peripheral singleton"] SLCHOST <= SLCHOST() (unstable)), (@ peri_type
        #[doc = "SPI0 peripheral singleton"] SPI0 <= SPI0() (unstable)), (@ peri_type
        #[doc = "SPI1 peripheral singleton"] SPI1 <= SPI1() (unstable)), (@ peri_type
        #[doc = "SPI2 peripheral singleton"] SPI2 <= SPI2(SPI2_DMA : {
        bind_dma_interrupt, enable_dma_interrupt, disable_dma_interrupt }, SPI2 : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (@
        peri_type #[doc = "SPI3 peripheral singleton"] SPI3 <= SPI3(SPI3_DMA : {
        bind_dma_interrupt, enable_dma_interrupt, disable_dma_interrupt }, SPI3 : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (@
        peri_type #[doc = "TIMG0 peripheral singleton"] TIMG0 <= TIMG0() (unstable)), (@
        peri_type #[doc = "TIMG1 peripheral singleton"] TIMG1 <= TIMG1() (unstable)), (@
        peri_type #[doc = "TWAI0 peripheral singleton"] TWAI0 <= TWAI0() (unstable)), (@
        peri_type #[doc = "UART0 peripheral singleton"] UART0 <= UART0(UART0 : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (@
        peri_type #[doc = "UART1 peripheral singleton"] UART1 <= UART1(UART1 : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (@
        peri_type #[doc = "UART2 peripheral singleton"] UART2 <= UART2(UART2 : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (@
        peri_type #[doc = "UHCI0 peripheral singleton"] UHCI0 <= UHCI0() (unstable)), (@
        peri_type #[doc = "UHCI1 peripheral singleton"] UHCI1 <= UHCI1() (unstable)), (@
        peri_type #[doc = "WIFI peripheral singleton"] WIFI <= WIFI(WIFI_MAC : {
        bind_mac_interrupt, enable_mac_interrupt, disable_mac_interrupt })), (@ peri_type
        #[doc = "ADC1 peripheral singleton"] ADC1 <= virtual() (unstable)), (@ peri_type
        #[doc = "ADC2 peripheral singleton"] ADC2 <= virtual() (unstable)), (@ peri_type
        #[doc = "BT peripheral singleton"] BT <= virtual(BT_BB : { bind_bb_interrupt,
        enable_bb_interrupt, disable_bb_interrupt }, RWBLE : { bind_rwble_interrupt,
        enable_rwble_interrupt, disable_rwble_interrupt }, RWBT : { bind_rwbt_interrupt,
        enable_rwbt_interrupt, disable_rwbt_interrupt }) (unstable)), (@ peri_type #[doc
        = "CPU_CTRL peripheral singleton"] CPU_CTRL <= virtual() (unstable)), (@
        peri_type #[doc = "DAC1 peripheral singleton"] DAC1 <= virtual() (unstable)), (@
        peri_type #[doc = "DAC2 peripheral singleton"] DAC2 <= virtual() (unstable)), (@
        peri_type #[doc = "FLASH peripheral singleton"] FLASH <= virtual() (unstable)),
        (@ peri_type #[doc = "PSRAM peripheral singleton"] PSRAM <= virtual()
        (unstable)), (@ peri_type #[doc = "TOUCH peripheral singleton"] TOUCH <=
        virtual() (unstable)), (@ peri_type #[doc = "IPC peripheral singleton"] IPC <=
        virtual() (unstable)), (@ peri_type #[doc =
        "FROM_CPU_INTR0 peripheral singleton"] FROM_CPU_INTR0 <= virtual() (unstable)),
        (@ peri_type #[doc = "FROM_CPU_INTR1 peripheral singleton"] FROM_CPU_INTR1 <=
        virtual() (unstable)), (@ peri_type #[doc =
        "FROM_CPU_INTR2 peripheral singleton"] FROM_CPU_INTR2 <= virtual() (unstable)),
        (@ peri_type #[doc = "FROM_CPU_INTR3 peripheral singleton"] FROM_CPU_INTR3 <=
        virtual() (unstable)))); _for_each_inner_peripheral!((singletons(GPIO0), (GPIO1),
        (GPIO2), (GPIO3), (GPIO4), (GPIO5), (GPIO6), (GPIO7), (GPIO8), (GPIO9), (GPIO10),
        (GPIO11), (GPIO12), (GPIO13), (GPIO14), (GPIO15), (GPIO16), (GPIO17), (GPIO18),
        (GPIO19), (GPIO20), (GPIO21), (GPIO22), (GPIO23), (GPIO25), (GPIO26), (GPIO27),
        (#[cfg(not(use_xtal32k))] GPIO32), (#[cfg(not(use_xtal32k))] GPIO33), (GPIO34),
        (GPIO35), (GPIO36), (GPIO37), (GPIO38), (GPIO39), (DMA_SPI2(unstable)),
        (DMA_SPI3(unstable)), (DMA_I2S0(unstable)), (DMA_I2S1(unstable)),
        (PCNT0_UNIT0(unstable)), (PCNT0_UNIT1(unstable)), (PCNT0_UNIT2(unstable)),
        (PCNT0_UNIT3(unstable)), (PCNT0_UNIT4(unstable)), (PCNT0_UNIT5(unstable)),
        (PCNT0_UNIT6(unstable)), (PCNT0_UNIT7(unstable)), (SDM_CH0(unstable)),
        (SDM_CH1(unstable)), (SDM_CH2(unstable)), (SDM_CH3(unstable)),
        (SDM_CH4(unstable)), (SDM_CH5(unstable)), (SDM_CH6(unstable)),
        (SDM_CH7(unstable)), (AES(unstable)), (APB_CTRL(unstable)), (BB(unstable)),
        (DPORT(unstable)), (SYSTEM(unstable)), (ETH(unstable)),
        (FLASH_ENCRYPTION(unstable)), (FRC_TIMER(unstable)), (GPIO(unstable)),
        (GPIO_SD(unstable)), (HINF(unstable)), (I2C0), (I2C1), (I2S0(unstable)),
        (I2S1(unstable)), (IO_MUX(unstable)), (LEDC(unstable)), (MCPWM0(unstable)),
        (MCPWM1(unstable)), (NRX(unstable)), (PCNT(unstable)), (RMT(unstable)),
        (RNG(unstable)), (RSA(unstable)), (LPWR(unstable)), (RTC_TIMER(unstable)),
        (LP_I2C0(unstable)), (RTC_IO(unstable)), (SDHOST(unstable)), (SENS(unstable)),
        (SHA(unstable)), (SLC(unstable)), (SLCHOST(unstable)), (SPI0(unstable)),
        (SPI1(unstable)), (SPI2), (SPI3), (TIMG0(unstable)), (TIMG1(unstable)),
        (TWAI0(unstable)), (UART0), (UART1), (UART2), (UHCI0(unstable)),
        (UHCI1(unstable)), (WIFI), (ADC1(unstable)), (ADC2(unstable)), (BT(unstable)),
        (CPU_CTRL(unstable)), (DAC1(unstable)), (DAC2(unstable)), (FLASH(unstable)),
        (PSRAM(unstable)), (TOUCH(unstable)), (IPC(unstable)),
        (FROM_CPU_INTR2(unstable)), (FROM_CPU_INTR3(unstable))));
        _for_each_inner_peripheral!((dma_eligible(SPI2, Spi2, 0, SpiDmaChannel), (I2S0,
        I2s0, 0, I2sDmaChannel), (SPI3, Spi3, 1, SpiDmaChannel), (I2S1, I2s1, 1,
        I2sDmaChannel)));
    };
}
/// This macro can be used to generate code for each `GPIOn` instance.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($n:literal, $gpio:ident ($($digital_input_function:ident =>
/// $digital_input_signal:ident)*) ($($digital_output_function:ident =>
/// $digital_output_signal:ident)*) ($([$pin_attribute:ident])*))`
///
/// Macro fragments:
///
/// - `$n`: the number of the GPIO. For `GPIO0`, `$n` is 0.
/// - `$gpio`: the name of the GPIO.
/// - `$digital_input_function`: the number of the digital function, as an identifier (i.e. for
///   function 0 this is `_0`).
/// - `$digital_input_function`: the name of the digital function, as an identifier.
/// - `$digital_output_function`: the number of the digital function, as an identifier (i.e. for
///   function 0 this is `_0`).
/// - `$digital_output_function`: the name of the digital function, as an identifier.
/// - `$pin_attribute`: `Input` and/or `Output`, marks the possible directions of the GPIO.
///   Bracketed so that they can also be matched as optional fragments. Order is always Input first.
///
/// Example data: `(0, GPIO0 (_5 => EMAC_TX_CLK) (_1 => CLK_OUT1 _5 => EMAC_TX_CLK) ([Input]
/// [Output]))`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_gpio {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_gpio { $(($pattern) => $code;)* ($other : tt) => {}
        } _for_each_inner_gpio!((0, GPIO0(_5 => EMAC_TX_CLK) (_1 => CLK_OUT1 _5 =>
        EMAC_TX_CLK) ([Input] [Output]))); _for_each_inner_gpio!((1, GPIO1(_5 =>
        EMAC_RXD2) (_0 => U0TXD _1 => CLK_OUT3) ([Input] [Output])));
        _for_each_inner_gpio!((2, GPIO2(_1 => HSPIWP _3 => SD2_DATA0 _4 => SD_DATA0) (_1
        => HSPIWP _3 => SD2_DATA0 _4 => SD_DATA0) ([Input] [Output])));
        _for_each_inner_gpio!((3, GPIO3(_0 => U0RXD) (_1 => CLK_OUT2) ([Input]
        [Output]))); _for_each_inner_gpio!((4, GPIO4(_1 => HSPIHD _3 => SD2_DATA1 _4 =>
        SD_DATA1 _5 => EMAC_TXER) (_1 => HSPIHD _3 => SD2_DATA1 _4 => SD_DATA1 _5 =>
        EMAC_TXER) ([Input] [Output]))); _for_each_inner_gpio!((5, GPIO5(_1 => VSPICS0 _3
        => SD1_DATA6 _5 => EMAC_RX_CLK) (_1 => VSPICS0 _3 => SD1_DATA6) ([Input]
        [Output]))); _for_each_inner_gpio!((6, GPIO6(_1 => SPICLK _4 => U1CTS) (_0 =>
        SD_CLK _1 => SPICLK _3 => SD1_CLK) ([Input] [Output])));
        _for_each_inner_gpio!((7, GPIO7(_0 => SD_DATA0 _1 => SPIQ _3 => SD1_DATA0) (_0 =>
        SD_DATA0 _1 => SPIQ _3 => SD1_DATA0 _4 => U2RTS) ([Input] [Output])));
        _for_each_inner_gpio!((8, GPIO8(_0 => SD_DATA1 _1 => SPID _3 => SD1_DATA1 _4 =>
        U2CTS) (_0 => SD_DATA1 _1 => SPID _3 => SD1_DATA1) ([Input] [Output])));
        _for_each_inner_gpio!((9, GPIO9(_0 => SD_DATA2 _1 => SPIHD _3 => SD1_DATA2 _4 =>
        U1RXD) (_0 => SD_DATA2 _1 => SPIHD _3 => SD1_DATA2) ([Input] [Output])));
        _for_each_inner_gpio!((10, GPIO10(_0 => SD_DATA3 _1 => SPIWP _3 => SD1_DATA3) (_0
        => SD_DATA3 _1 => SPIWP _3 => SD1_DATA3 _4 => U1TXD) ([Input] [Output])));
        _for_each_inner_gpio!((11, GPIO11(_0 => SD_CMD _1 => SPICS0) (_0 => SD_CMD _1 =>
        SPICS0 _3 => SD1_CMD _4 => U1RTS) ([Input] [Output])));
        _for_each_inner_gpio!((12, GPIO12(_0 => MTDI _1 => HSPIQ _3 => SD2_DATA2 _4 =>
        SD_DATA2) (_1 => HSPIQ _3 => SD2_DATA2 _4 => SD_DATA2 _5 => EMAC_TXD3) ([Input]
        [Output]))); _for_each_inner_gpio!((13, GPIO13(_0 => MTCK _1 => HSPID _3 =>
        SD2_DATA3 _4 => SD_DATA3 _5 => EMAC_RXER) (_1 => HSPID _3 => SD2_DATA3 _4 =>
        SD_DATA3 _5 => EMAC_RXER) ([Input] [Output]))); _for_each_inner_gpio!((14,
        GPIO14(_0 => MTMS _1 => HSPICLK) (_1 => HSPICLK _3 => SD2_CLK _4 => SD_CLK _5 =>
        EMAC_TXD2) ([Input] [Output]))); _for_each_inner_gpio!((15, GPIO15(_1 => HSPICS0
        _4 => SD_CMD _5 => EMAC_RXD3) (_0 => MTDO _1 => HSPICS0 _3 => SD2_CMD _4 =>
        SD_CMD) ([Input] [Output]))); _for_each_inner_gpio!((16, GPIO16(_3 => SD1_DATA4
        _4 => U2RXD) (_3 => SD1_DATA4 _5 => EMAC_CLK_OUT) ([Input] [Output])));
        _for_each_inner_gpio!((17, GPIO17(_3 => SD1_DATA5) (_3 => SD1_DATA5 _4 => U2TXD
        _5 => EMAC_CLK_180) ([Input] [Output]))); _for_each_inner_gpio!((18, GPIO18(_1 =>
        VSPICLK _3 => SD1_DATA7) (_1 => VSPICLK _3 => SD1_DATA7) ([Input] [Output])));
        _for_each_inner_gpio!((19, GPIO19(_1 => VSPIQ _3 => U0CTS) (_1 => VSPIQ _5 =>
        EMAC_TXD0) ([Input] [Output]))); _for_each_inner_gpio!((20, GPIO20() () ([Input]
        [Output]))); _for_each_inner_gpio!((21, GPIO21(_1 => VSPIHD) (_1 => VSPIHD _5 =>
        EMAC_TXEN) ([Input] [Output]))); _for_each_inner_gpio!((22, GPIO22(_1 => VSPIWP)
        (_1 => VSPIWP _3 => U0RTS _5 => EMAC_TXD1) ([Input] [Output])));
        _for_each_inner_gpio!((23, GPIO23(_1 => VSPID) (_1 => VSPID _3 => SD1_STROBE)
        ([Input] [Output]))); _for_each_inner_gpio!((25, GPIO25(_5 => EMAC_RXD0) ()
        ([Input] [Output]))); _for_each_inner_gpio!((26, GPIO26(_5 => EMAC_RXD1) ()
        ([Input] [Output]))); _for_each_inner_gpio!((27, GPIO27(_5 => EMAC_RXDV) ()
        ([Input] [Output]))); _for_each_inner_gpio!((32, GPIO32() () ([Input]
        [Output]))); _for_each_inner_gpio!((33, GPIO33() () ([Input] [Output])));
        _for_each_inner_gpio!((34, GPIO34() () ([Input] []))); _for_each_inner_gpio!((35,
        GPIO35() () ([Input] []))); _for_each_inner_gpio!((36, GPIO36() () ([Input]
        []))); _for_each_inner_gpio!((37, GPIO37() () ([Input] [])));
        _for_each_inner_gpio!((38, GPIO38() () ([Input] []))); _for_each_inner_gpio!((39,
        GPIO39() () ([Input] []))); _for_each_inner_gpio!((all(0, GPIO0(_5 =>
        EMAC_TX_CLK) (_1 => CLK_OUT1 _5 => EMAC_TX_CLK) ([Input] [Output])), (1, GPIO1(_5
        => EMAC_RXD2) (_0 => U0TXD _1 => CLK_OUT3) ([Input] [Output])), (2, GPIO2(_1 =>
        HSPIWP _3 => SD2_DATA0 _4 => SD_DATA0) (_1 => HSPIWP _3 => SD2_DATA0 _4 =>
        SD_DATA0) ([Input] [Output])), (3, GPIO3(_0 => U0RXD) (_1 => CLK_OUT2) ([Input]
        [Output])), (4, GPIO4(_1 => HSPIHD _3 => SD2_DATA1 _4 => SD_DATA1 _5 =>
        EMAC_TXER) (_1 => HSPIHD _3 => SD2_DATA1 _4 => SD_DATA1 _5 => EMAC_TXER) ([Input]
        [Output])), (5, GPIO5(_1 => VSPICS0 _3 => SD1_DATA6 _5 => EMAC_RX_CLK) (_1 =>
        VSPICS0 _3 => SD1_DATA6) ([Input] [Output])), (6, GPIO6(_1 => SPICLK _4 => U1CTS)
        (_0 => SD_CLK _1 => SPICLK _3 => SD1_CLK) ([Input] [Output])), (7, GPIO7(_0 =>
        SD_DATA0 _1 => SPIQ _3 => SD1_DATA0) (_0 => SD_DATA0 _1 => SPIQ _3 => SD1_DATA0
        _4 => U2RTS) ([Input] [Output])), (8, GPIO8(_0 => SD_DATA1 _1 => SPID _3 =>
        SD1_DATA1 _4 => U2CTS) (_0 => SD_DATA1 _1 => SPID _3 => SD1_DATA1) ([Input]
        [Output])), (9, GPIO9(_0 => SD_DATA2 _1 => SPIHD _3 => SD1_DATA2 _4 => U1RXD) (_0
        => SD_DATA2 _1 => SPIHD _3 => SD1_DATA2) ([Input] [Output])), (10, GPIO10(_0 =>
        SD_DATA3 _1 => SPIWP _3 => SD1_DATA3) (_0 => SD_DATA3 _1 => SPIWP _3 => SD1_DATA3
        _4 => U1TXD) ([Input] [Output])), (11, GPIO11(_0 => SD_CMD _1 => SPICS0) (_0 =>
        SD_CMD _1 => SPICS0 _3 => SD1_CMD _4 => U1RTS) ([Input] [Output])), (12,
        GPIO12(_0 => MTDI _1 => HSPIQ _3 => SD2_DATA2 _4 => SD_DATA2) (_1 => HSPIQ _3 =>
        SD2_DATA2 _4 => SD_DATA2 _5 => EMAC_TXD3) ([Input] [Output])), (13, GPIO13(_0 =>
        MTCK _1 => HSPID _3 => SD2_DATA3 _4 => SD_DATA3 _5 => EMAC_RXER) (_1 => HSPID _3
        => SD2_DATA3 _4 => SD_DATA3 _5 => EMAC_RXER) ([Input] [Output])), (14, GPIO14(_0
        => MTMS _1 => HSPICLK) (_1 => HSPICLK _3 => SD2_CLK _4 => SD_CLK _5 => EMAC_TXD2)
        ([Input] [Output])), (15, GPIO15(_1 => HSPICS0 _4 => SD_CMD _5 => EMAC_RXD3) (_0
        => MTDO _1 => HSPICS0 _3 => SD2_CMD _4 => SD_CMD) ([Input] [Output])), (16,
        GPIO16(_3 => SD1_DATA4 _4 => U2RXD) (_3 => SD1_DATA4 _5 => EMAC_CLK_OUT) ([Input]
        [Output])), (17, GPIO17(_3 => SD1_DATA5) (_3 => SD1_DATA5 _4 => U2TXD _5 =>
        EMAC_CLK_180) ([Input] [Output])), (18, GPIO18(_1 => VSPICLK _3 => SD1_DATA7) (_1
        => VSPICLK _3 => SD1_DATA7) ([Input] [Output])), (19, GPIO19(_1 => VSPIQ _3 =>
        U0CTS) (_1 => VSPIQ _5 => EMAC_TXD0) ([Input] [Output])), (20, GPIO20() ()
        ([Input] [Output])), (21, GPIO21(_1 => VSPIHD) (_1 => VSPIHD _5 => EMAC_TXEN)
        ([Input] [Output])), (22, GPIO22(_1 => VSPIWP) (_1 => VSPIWP _3 => U0RTS _5 =>
        EMAC_TXD1) ([Input] [Output])), (23, GPIO23(_1 => VSPID) (_1 => VSPID _3 =>
        SD1_STROBE) ([Input] [Output])), (25, GPIO25(_5 => EMAC_RXD0) () ([Input]
        [Output])), (26, GPIO26(_5 => EMAC_RXD1) () ([Input] [Output])), (27, GPIO27(_5
        => EMAC_RXDV) () ([Input] [Output])), (32, GPIO32() () ([Input] [Output])), (33,
        GPIO33() () ([Input] [Output])), (34, GPIO34() () ([Input] [])), (35, GPIO35() ()
        ([Input] [])), (36, GPIO36() () ([Input] [])), (37, GPIO37() () ([Input] [])),
        (38, GPIO38() () ([Input] [])), (39, GPIO39() () ([Input] []))));
    };
}
/// This macro can be used to generate code for each analog function of each GPIO.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident)` - simple case where you only need identifiers
/// - group: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident)` - expanded signal
///   case, where you need the number(s) of a signal, or the general group to which the signal
///   belongs. For example, in case of `ADC2_CH3` the expanded form looks like `(ADC2_CH3, ADCn_CHm,
///   2, 3)`.
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders. For `ADC2_CH3` this
///   is `ADCn_CHm`.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
///
/// Example data:
/// - `(ADC2_CH5, GPIO12)`
/// - `((ADC2_CH5, ADCn_CHm, 2, 5), GPIO12)`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_analog_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_analog_function { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_analog_function!((ADC2_CH1, GPIO0));
        _for_each_inner_analog_function!((TOUCH1, GPIO0));
        _for_each_inner_analog_function!((ADC2_CH2, GPIO2));
        _for_each_inner_analog_function!((TOUCH2, GPIO2));
        _for_each_inner_analog_function!((ADC2_CH0, GPIO4));
        _for_each_inner_analog_function!((TOUCH0, GPIO4));
        _for_each_inner_analog_function!((ADC2_CH5, GPIO12));
        _for_each_inner_analog_function!((TOUCH5, GPIO12));
        _for_each_inner_analog_function!((ADC2_CH4, GPIO13));
        _for_each_inner_analog_function!((TOUCH4, GPIO13));
        _for_each_inner_analog_function!((ADC2_CH6, GPIO14));
        _for_each_inner_analog_function!((TOUCH6, GPIO14));
        _for_each_inner_analog_function!((ADC2_CH3, GPIO15));
        _for_each_inner_analog_function!((TOUCH3, GPIO15));
        _for_each_inner_analog_function!((DAC1, GPIO25));
        _for_each_inner_analog_function!((ADC2_CH8, GPIO25));
        _for_each_inner_analog_function!((DAC2, GPIO26));
        _for_each_inner_analog_function!((ADC2_CH9, GPIO26));
        _for_each_inner_analog_function!((ADC2_CH7, GPIO27));
        _for_each_inner_analog_function!((TOUCH7, GPIO27));
        _for_each_inner_analog_function!((XTAL_32K_P, GPIO32));
        _for_each_inner_analog_function!((ADC1_CH4, GPIO32));
        _for_each_inner_analog_function!((TOUCH9, GPIO32));
        _for_each_inner_analog_function!((XTAL_32K_N, GPIO33));
        _for_each_inner_analog_function!((ADC1_CH5, GPIO33));
        _for_each_inner_analog_function!((TOUCH8, GPIO33));
        _for_each_inner_analog_function!((ADC1_CH6, GPIO34));
        _for_each_inner_analog_function!((ADC1_CH7, GPIO35));
        _for_each_inner_analog_function!((ADC_H, GPIO36));
        _for_each_inner_analog_function!((ADC1_CH0, GPIO36));
        _for_each_inner_analog_function!((ADC_H, GPIO37));
        _for_each_inner_analog_function!((ADC1_CH1, GPIO37));
        _for_each_inner_analog_function!((ADC_H, GPIO38));
        _for_each_inner_analog_function!((ADC1_CH2, GPIO38));
        _for_each_inner_analog_function!((ADC_H, GPIO39));
        _for_each_inner_analog_function!((ADC1_CH3, GPIO39));
        _for_each_inner_analog_function!(((ADC2_CH1, ADCn_CHm, 2, 1), GPIO0));
        _for_each_inner_analog_function!(((ADC2_CH2, ADCn_CHm, 2, 2), GPIO2));
        _for_each_inner_analog_function!(((ADC2_CH0, ADCn_CHm, 2, 0), GPIO4));
        _for_each_inner_analog_function!(((ADC2_CH5, ADCn_CHm, 2, 5), GPIO12));
        _for_each_inner_analog_function!(((ADC2_CH4, ADCn_CHm, 2, 4), GPIO13));
        _for_each_inner_analog_function!(((ADC2_CH6, ADCn_CHm, 2, 6), GPIO14));
        _for_each_inner_analog_function!(((ADC2_CH3, ADCn_CHm, 2, 3), GPIO15));
        _for_each_inner_analog_function!(((ADC2_CH8, ADCn_CHm, 2, 8), GPIO25));
        _for_each_inner_analog_function!(((ADC2_CH9, ADCn_CHm, 2, 9), GPIO26));
        _for_each_inner_analog_function!(((ADC2_CH7, ADCn_CHm, 2, 7), GPIO27));
        _for_each_inner_analog_function!(((ADC1_CH4, ADCn_CHm, 1, 4), GPIO32));
        _for_each_inner_analog_function!(((ADC1_CH5, ADCn_CHm, 1, 5), GPIO33));
        _for_each_inner_analog_function!(((ADC1_CH6, ADCn_CHm, 1, 6), GPIO34));
        _for_each_inner_analog_function!(((ADC1_CH7, ADCn_CHm, 1, 7), GPIO35));
        _for_each_inner_analog_function!(((ADC1_CH0, ADCn_CHm, 1, 0), GPIO36));
        _for_each_inner_analog_function!(((ADC1_CH1, ADCn_CHm, 1, 1), GPIO37));
        _for_each_inner_analog_function!(((ADC1_CH2, ADCn_CHm, 1, 2), GPIO38));
        _for_each_inner_analog_function!(((ADC1_CH3, ADCn_CHm, 1, 3), GPIO39));
        _for_each_inner_analog_function!(((TOUCH1, TOUCHn, 1), GPIO0));
        _for_each_inner_analog_function!(((TOUCH2, TOUCHn, 2), GPIO2));
        _for_each_inner_analog_function!(((TOUCH0, TOUCHn, 0), GPIO4));
        _for_each_inner_analog_function!(((TOUCH5, TOUCHn, 5), GPIO12));
        _for_each_inner_analog_function!(((TOUCH4, TOUCHn, 4), GPIO13));
        _for_each_inner_analog_function!(((TOUCH6, TOUCHn, 6), GPIO14));
        _for_each_inner_analog_function!(((TOUCH3, TOUCHn, 3), GPIO15));
        _for_each_inner_analog_function!(((TOUCH7, TOUCHn, 7), GPIO27));
        _for_each_inner_analog_function!(((TOUCH9, TOUCHn, 9), GPIO32));
        _for_each_inner_analog_function!(((TOUCH8, TOUCHn, 8), GPIO33));
        _for_each_inner_analog_function!(((DAC1, DACn, 1), GPIO25));
        _for_each_inner_analog_function!(((DAC2, DACn, 2), GPIO26));
        _for_each_inner_analog_function!((all(ADC2_CH1, GPIO0), (TOUCH1, GPIO0),
        (ADC2_CH2, GPIO2), (TOUCH2, GPIO2), (ADC2_CH0, GPIO4), (TOUCH0, GPIO4),
        (ADC2_CH5, GPIO12), (TOUCH5, GPIO12), (ADC2_CH4, GPIO13), (TOUCH4, GPIO13),
        (ADC2_CH6, GPIO14), (TOUCH6, GPIO14), (ADC2_CH3, GPIO15), (TOUCH3, GPIO15),
        (DAC1, GPIO25), (ADC2_CH8, GPIO25), (DAC2, GPIO26), (ADC2_CH9, GPIO26),
        (ADC2_CH7, GPIO27), (TOUCH7, GPIO27), (XTAL_32K_P, GPIO32), (ADC1_CH4, GPIO32),
        (TOUCH9, GPIO32), (XTAL_32K_N, GPIO33), (ADC1_CH5, GPIO33), (TOUCH8, GPIO33),
        (ADC1_CH6, GPIO34), (ADC1_CH7, GPIO35), (ADC_H, GPIO36), (ADC1_CH0, GPIO36),
        (ADC_H, GPIO37), (ADC1_CH1, GPIO37), (ADC_H, GPIO38), (ADC1_CH2, GPIO38), (ADC_H,
        GPIO39), (ADC1_CH3, GPIO39)));
        _for_each_inner_analog_function!((ADCn_CHm((ADC2_CH1, ADCn_CHm, 2, 1), GPIO0),
        ((ADC2_CH2, ADCn_CHm, 2, 2), GPIO2), ((ADC2_CH0, ADCn_CHm, 2, 0), GPIO4),
        ((ADC2_CH5, ADCn_CHm, 2, 5), GPIO12), ((ADC2_CH4, ADCn_CHm, 2, 4), GPIO13),
        ((ADC2_CH6, ADCn_CHm, 2, 6), GPIO14), ((ADC2_CH3, ADCn_CHm, 2, 3), GPIO15),
        ((ADC2_CH8, ADCn_CHm, 2, 8), GPIO25), ((ADC2_CH9, ADCn_CHm, 2, 9), GPIO26),
        ((ADC2_CH7, ADCn_CHm, 2, 7), GPIO27), ((ADC1_CH4, ADCn_CHm, 1, 4), GPIO32),
        ((ADC1_CH5, ADCn_CHm, 1, 5), GPIO33), ((ADC1_CH6, ADCn_CHm, 1, 6), GPIO34),
        ((ADC1_CH7, ADCn_CHm, 1, 7), GPIO35), ((ADC1_CH0, ADCn_CHm, 1, 0), GPIO36),
        ((ADC1_CH1, ADCn_CHm, 1, 1), GPIO37), ((ADC1_CH2, ADCn_CHm, 1, 2), GPIO38),
        ((ADC1_CH3, ADCn_CHm, 1, 3), GPIO39)));
        _for_each_inner_analog_function!((TOUCHn((TOUCH1, TOUCHn, 1), GPIO0), ((TOUCH2,
        TOUCHn, 2), GPIO2), ((TOUCH0, TOUCHn, 0), GPIO4), ((TOUCH5, TOUCHn, 5), GPIO12),
        ((TOUCH4, TOUCHn, 4), GPIO13), ((TOUCH6, TOUCHn, 6), GPIO14), ((TOUCH3, TOUCHn,
        3), GPIO15), ((TOUCH7, TOUCHn, 7), GPIO27), ((TOUCH9, TOUCHn, 9), GPIO32),
        ((TOUCH8, TOUCHn, 8), GPIO33))); _for_each_inner_analog_function!((DACn((DAC1,
        DACn, 1), GPIO25), ((DAC2, DACn, 2), GPIO26)));
    };
}
/// This macro can be used to generate code for each LP function of each GPIO.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident, $af:ident)` - simple case where you only need
///   identifiers, and maybe the function.
/// - group: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident, $af:ident, ($(
///   $lp_input_af:ident => $lp_input_signal:ident )*) ($( $lp_output_af:ident =>
///   $lp_output_signal:ident )*))` - expanded signal case, where you need the number(s) of a
///   signal, or the general group to which the signal belongs. Every expanded branch ends with the
///   pad's LP input and output function groups (empty on chips without an LP GPIO matrix).
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders. For `ADC2_CH3` this
///   is `ADCn_CHm`.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
/// - `$af`: the LP IO MUX function, as an identifier (i.e. for function 0 this is `_0`). This is
///   the name of an `LpFunction` variant, and its number is the value to write to the pad's
///   function select field.
/// - `$lp_input_af`: the LP IO MUX function for an LP peripheral input on this pad.
/// - `$lp_input_signal`: the LP peripheral input signal name.
/// - `$lp_output_af`: the LP IO MUX function for an LP peripheral output on this pad.
/// - `$lp_output_signal`: the LP peripheral output signal name.
///
/// Example data:
/// - `(LP_GPIO15, GPIO12, _0)`
/// - `((LP_GPIO15, LP_GPIOn, 15), GPIO12, _0, () ())`
/// - `((LP_GPIO14, LP_GPIOn, 14), GPIO14, _1, () (_0 => LP_UART_TXD))`
/// - `((SAR_I2C_SCL_1, SAR_I2C_SCL_n, 1), GPIO2, _3, () ())`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_lp_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_lp_function { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_lp_function!((LP_GPIO11, GPIO0, _0));
        _for_each_inner_lp_function!((SAR_I2C_SDA, GPIO0, _3));
        _for_each_inner_lp_function!((LP_GPIO12, GPIO2, _0));
        _for_each_inner_lp_function!((SAR_I2C_SCL, GPIO2, _3));
        _for_each_inner_lp_function!((LP_GPIO10, GPIO4, _0));
        _for_each_inner_lp_function!((SAR_I2C_SCL, GPIO4, _3));
        _for_each_inner_lp_function!((LP_GPIO15, GPIO12, _0));
        _for_each_inner_lp_function!((LP_GPIO14, GPIO13, _0));
        _for_each_inner_lp_function!((LP_GPIO16, GPIO14, _0));
        _for_each_inner_lp_function!((LP_GPIO13, GPIO15, _0));
        _for_each_inner_lp_function!((SAR_I2C_SDA, GPIO15, _3));
        _for_each_inner_lp_function!((LP_GPIO6, GPIO25, _0));
        _for_each_inner_lp_function!((LP_GPIO7, GPIO26, _0));
        _for_each_inner_lp_function!((LP_GPIO17, GPIO27, _0));
        _for_each_inner_lp_function!((LP_GPIO9, GPIO32, _0));
        _for_each_inner_lp_function!((LP_GPIO8, GPIO33, _0));
        _for_each_inner_lp_function!((LP_GPIO4, GPIO34, _0));
        _for_each_inner_lp_function!((LP_GPIO5, GPIO35, _0));
        _for_each_inner_lp_function!((LP_GPIO0, GPIO36, _0));
        _for_each_inner_lp_function!((LP_GPIO1, GPIO37, _0));
        _for_each_inner_lp_function!((LP_GPIO2, GPIO38, _0));
        _for_each_inner_lp_function!((LP_GPIO3, GPIO39, _0));
        _for_each_inner_lp_function!(((LP_GPIO11, LP_GPIOn, 11), GPIO0, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO12, LP_GPIOn, 12), GPIO2, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO10, LP_GPIOn, 10), GPIO4, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO15, LP_GPIOn, 15), GPIO12, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO14, LP_GPIOn, 14), GPIO13, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO16, LP_GPIOn, 16), GPIO14, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO13, LP_GPIOn, 13), GPIO15, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO6, LP_GPIOn, 6), GPIO25, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO7, LP_GPIOn, 7), GPIO26, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO17, LP_GPIOn, 17), GPIO27, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO9, LP_GPIOn, 9), GPIO32, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO8, LP_GPIOn, 8), GPIO33, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO4, LP_GPIOn, 4), GPIO34, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO5, LP_GPIOn, 5), GPIO35, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO0, LP_GPIOn, 0), GPIO36, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO1, LP_GPIOn, 1), GPIO37, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO2, LP_GPIOn, 2), GPIO38, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO3, LP_GPIOn, 3), GPIO39, _0, () ()));
        _for_each_inner_lp_function!((all(LP_GPIO11, GPIO0, _0), (SAR_I2C_SDA, GPIO0,
        _3), (LP_GPIO12, GPIO2, _0), (SAR_I2C_SCL, GPIO2, _3), (LP_GPIO10, GPIO4, _0),
        (SAR_I2C_SCL, GPIO4, _3), (LP_GPIO15, GPIO12, _0), (LP_GPIO14, GPIO13, _0),
        (LP_GPIO16, GPIO14, _0), (LP_GPIO13, GPIO15, _0), (SAR_I2C_SDA, GPIO15, _3),
        (LP_GPIO6, GPIO25, _0), (LP_GPIO7, GPIO26, _0), (LP_GPIO17, GPIO27, _0),
        (LP_GPIO9, GPIO32, _0), (LP_GPIO8, GPIO33, _0), (LP_GPIO4, GPIO34, _0),
        (LP_GPIO5, GPIO35, _0), (LP_GPIO0, GPIO36, _0), (LP_GPIO1, GPIO37, _0),
        (LP_GPIO2, GPIO38, _0), (LP_GPIO3, GPIO39, _0)));
        _for_each_inner_lp_function!((LP_GPIOn((LP_GPIO11, LP_GPIOn, 11), GPIO0, _0, ()
        ()), ((LP_GPIO12, LP_GPIOn, 12), GPIO2, _0, () ()), ((LP_GPIO10, LP_GPIOn, 10),
        GPIO4, _0, () ()), ((LP_GPIO15, LP_GPIOn, 15), GPIO12, _0, () ()), ((LP_GPIO14,
        LP_GPIOn, 14), GPIO13, _0, () ()), ((LP_GPIO16, LP_GPIOn, 16), GPIO14, _0, ()
        ()), ((LP_GPIO13, LP_GPIOn, 13), GPIO15, _0, () ()), ((LP_GPIO6, LP_GPIOn, 6),
        GPIO25, _0, () ()), ((LP_GPIO7, LP_GPIOn, 7), GPIO26, _0, () ()), ((LP_GPIO17,
        LP_GPIOn, 17), GPIO27, _0, () ()), ((LP_GPIO9, LP_GPIOn, 9), GPIO32, _0, () ()),
        ((LP_GPIO8, LP_GPIOn, 8), GPIO33, _0, () ()), ((LP_GPIO4, LP_GPIOn, 4), GPIO34,
        _0, () ()), ((LP_GPIO5, LP_GPIOn, 5), GPIO35, _0, () ()), ((LP_GPIO0, LP_GPIOn,
        0), GPIO36, _0, () ()), ((LP_GPIO1, LP_GPIOn, 1), GPIO37, _0, () ()), ((LP_GPIO2,
        LP_GPIOn, 2), GPIO38, _0, () ()), ((LP_GPIO3, LP_GPIOn, 3), GPIO39, _0, () ())));
    };
}
/// This macro can be used to generate code for each IOMUX digital function of each GPIO.
///
/// IOMUX functions are the alternate digital functions configured via the IO_MUX registers.
/// Use this to implement signal-specific traits for peripherals whose pins must bypass the
/// GPIO matrix (e.g., EMAC, USB).
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident, $af:ident)` - simple case where you only need
///   identifiers, and maybe the alternate function.
/// - group: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident, $af:ident)` -
///   expanded signal case, where you need the number(s) of a signal, or the general group to which
///   the signal belongs.
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
/// - `$af`: the alternate function number, as an identifier (e.g. `_5`).
///
/// Example data:
/// - `(EMAC_RXD0, GPIO25, _5)`
/// - `((EMAC_RXDn, EMAC_RXDn, 0), GPIO25, _5)`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_iomux_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_iomux_function { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_iomux_function!((CLK_OUT1, GPIO0, _1));
        _for_each_inner_iomux_function!((EMAC_TX_CLK, GPIO0, _5));
        _for_each_inner_iomux_function!((U0TXD, GPIO1, _0));
        _for_each_inner_iomux_function!((CLK_OUT3, GPIO1, _1));
        _for_each_inner_iomux_function!((EMAC_RXD2, GPIO1, _5));
        _for_each_inner_iomux_function!((HSPIWP, GPIO2, _1));
        _for_each_inner_iomux_function!((SD2_DATA0, GPIO2, _3));
        _for_each_inner_iomux_function!((SD_DATA0, GPIO2, _4));
        _for_each_inner_iomux_function!((U0RXD, GPIO3, _0));
        _for_each_inner_iomux_function!((CLK_OUT2, GPIO3, _1));
        _for_each_inner_iomux_function!((HSPIHD, GPIO4, _1));
        _for_each_inner_iomux_function!((SD2_DATA1, GPIO4, _3));
        _for_each_inner_iomux_function!((SD_DATA1, GPIO4, _4));
        _for_each_inner_iomux_function!((EMAC_TXER, GPIO4, _5));
        _for_each_inner_iomux_function!((VSPICS0, GPIO5, _1));
        _for_each_inner_iomux_function!((SD1_DATA6, GPIO5, _3));
        _for_each_inner_iomux_function!((EMAC_RX_CLK, GPIO5, _5));
        _for_each_inner_iomux_function!((SD_CLK, GPIO6, _0));
        _for_each_inner_iomux_function!((SPICLK, GPIO6, _1));
        _for_each_inner_iomux_function!((SD1_CLK, GPIO6, _3));
        _for_each_inner_iomux_function!((U1CTS, GPIO6, _4));
        _for_each_inner_iomux_function!((SD_DATA0, GPIO7, _0));
        _for_each_inner_iomux_function!((SPIQ, GPIO7, _1));
        _for_each_inner_iomux_function!((SD1_DATA0, GPIO7, _3));
        _for_each_inner_iomux_function!((U2RTS, GPIO7, _4));
        _for_each_inner_iomux_function!((SD_DATA1, GPIO8, _0));
        _for_each_inner_iomux_function!((SPID, GPIO8, _1));
        _for_each_inner_iomux_function!((SD1_DATA1, GPIO8, _3));
        _for_each_inner_iomux_function!((U2CTS, GPIO8, _4));
        _for_each_inner_iomux_function!((SD_DATA2, GPIO9, _0));
        _for_each_inner_iomux_function!((SPIHD, GPIO9, _1));
        _for_each_inner_iomux_function!((SD1_DATA2, GPIO9, _3));
        _for_each_inner_iomux_function!((U1RXD, GPIO9, _4));
        _for_each_inner_iomux_function!((SD_DATA3, GPIO10, _0));
        _for_each_inner_iomux_function!((SPIWP, GPIO10, _1));
        _for_each_inner_iomux_function!((SD1_DATA3, GPIO10, _3));
        _for_each_inner_iomux_function!((U1TXD, GPIO10, _4));
        _for_each_inner_iomux_function!((SD_CMD, GPIO11, _0));
        _for_each_inner_iomux_function!((SPICS0, GPIO11, _1));
        _for_each_inner_iomux_function!((SD1_CMD, GPIO11, _3));
        _for_each_inner_iomux_function!((U1RTS, GPIO11, _4));
        _for_each_inner_iomux_function!((MTDI, GPIO12, _0));
        _for_each_inner_iomux_function!((HSPIQ, GPIO12, _1));
        _for_each_inner_iomux_function!((SD2_DATA2, GPIO12, _3));
        _for_each_inner_iomux_function!((SD_DATA2, GPIO12, _4));
        _for_each_inner_iomux_function!((EMAC_TXD3, GPIO12, _5));
        _for_each_inner_iomux_function!((MTCK, GPIO13, _0));
        _for_each_inner_iomux_function!((HSPID, GPIO13, _1));
        _for_each_inner_iomux_function!((SD2_DATA3, GPIO13, _3));
        _for_each_inner_iomux_function!((SD_DATA3, GPIO13, _4));
        _for_each_inner_iomux_function!((EMAC_RXER, GPIO13, _5));
        _for_each_inner_iomux_function!((MTMS, GPIO14, _0));
        _for_each_inner_iomux_function!((HSPICLK, GPIO14, _1));
        _for_each_inner_iomux_function!((SD2_CLK, GPIO14, _3));
        _for_each_inner_iomux_function!((SD_CLK, GPIO14, _4));
        _for_each_inner_iomux_function!((EMAC_TXD2, GPIO14, _5));
        _for_each_inner_iomux_function!((MTDO, GPIO15, _0));
        _for_each_inner_iomux_function!((HSPICS0, GPIO15, _1));
        _for_each_inner_iomux_function!((SD2_CMD, GPIO15, _3));
        _for_each_inner_iomux_function!((SD_CMD, GPIO15, _4));
        _for_each_inner_iomux_function!((EMAC_RXD3, GPIO15, _5));
        _for_each_inner_iomux_function!((SD1_DATA4, GPIO16, _3));
        _for_each_inner_iomux_function!((U2RXD, GPIO16, _4));
        _for_each_inner_iomux_function!((EMAC_CLK_OUT, GPIO16, _5));
        _for_each_inner_iomux_function!((SD1_DATA5, GPIO17, _3));
        _for_each_inner_iomux_function!((U2TXD, GPIO17, _4));
        _for_each_inner_iomux_function!((EMAC_CLK_180, GPIO17, _5));
        _for_each_inner_iomux_function!((VSPICLK, GPIO18, _1));
        _for_each_inner_iomux_function!((SD1_DATA7, GPIO18, _3));
        _for_each_inner_iomux_function!((VSPIQ, GPIO19, _1));
        _for_each_inner_iomux_function!((U0CTS, GPIO19, _3));
        _for_each_inner_iomux_function!((EMAC_TXD0, GPIO19, _5));
        _for_each_inner_iomux_function!((VSPIHD, GPIO21, _1));
        _for_each_inner_iomux_function!((EMAC_TXEN, GPIO21, _5));
        _for_each_inner_iomux_function!((VSPIWP, GPIO22, _1));
        _for_each_inner_iomux_function!((U0RTS, GPIO22, _3));
        _for_each_inner_iomux_function!((EMAC_TXD1, GPIO22, _5));
        _for_each_inner_iomux_function!((VSPID, GPIO23, _1));
        _for_each_inner_iomux_function!((SD1_STROBE, GPIO23, _3));
        _for_each_inner_iomux_function!((EMAC_RXD0, GPIO25, _5));
        _for_each_inner_iomux_function!((EMAC_RXD1, GPIO26, _5));
        _for_each_inner_iomux_function!((EMAC_RXDV, GPIO27, _5));
        _for_each_inner_iomux_function!(((CLK_OUT1, CLK_OUTn, 1), GPIO0, _1));
        _for_each_inner_iomux_function!(((CLK_OUT3, CLK_OUTn, 3), GPIO1, _1));
        _for_each_inner_iomux_function!(((CLK_OUT2, CLK_OUTn, 2), GPIO3, _1));
        _for_each_inner_iomux_function!(((EMAC_RXD2, EMAC_RXDn, 2), GPIO1, _5));
        _for_each_inner_iomux_function!(((EMAC_RXD3, EMAC_RXDn, 3), GPIO15, _5));
        _for_each_inner_iomux_function!(((EMAC_RXD0, EMAC_RXDn, 0), GPIO25, _5));
        _for_each_inner_iomux_function!(((EMAC_RXD1, EMAC_RXDn, 1), GPIO26, _5));
        _for_each_inner_iomux_function!(((SD2_DATA0, SDn_DATAm, 2, 0), GPIO2, _3));
        _for_each_inner_iomux_function!(((SD2_DATA1, SDn_DATAm, 2, 1), GPIO4, _3));
        _for_each_inner_iomux_function!(((SD1_DATA6, SDn_DATAm, 1, 6), GPIO5, _3));
        _for_each_inner_iomux_function!(((SD1_DATA0, SDn_DATAm, 1, 0), GPIO7, _3));
        _for_each_inner_iomux_function!(((SD1_DATA1, SDn_DATAm, 1, 1), GPIO8, _3));
        _for_each_inner_iomux_function!(((SD1_DATA2, SDn_DATAm, 1, 2), GPIO9, _3));
        _for_each_inner_iomux_function!(((SD1_DATA3, SDn_DATAm, 1, 3), GPIO10, _3));
        _for_each_inner_iomux_function!(((SD2_DATA2, SDn_DATAm, 2, 2), GPIO12, _3));
        _for_each_inner_iomux_function!(((SD2_DATA3, SDn_DATAm, 2, 3), GPIO13, _3));
        _for_each_inner_iomux_function!(((SD1_DATA4, SDn_DATAm, 1, 4), GPIO16, _3));
        _for_each_inner_iomux_function!(((SD1_DATA5, SDn_DATAm, 1, 5), GPIO17, _3));
        _for_each_inner_iomux_function!(((SD1_DATA7, SDn_DATAm, 1, 7), GPIO18, _3));
        _for_each_inner_iomux_function!(((SD_DATA0, SD_DATAn, 0), GPIO2, _4));
        _for_each_inner_iomux_function!(((SD_DATA1, SD_DATAn, 1), GPIO4, _4));
        _for_each_inner_iomux_function!(((SD_DATA0, SD_DATAn, 0), GPIO7, _0));
        _for_each_inner_iomux_function!(((SD_DATA1, SD_DATAn, 1), GPIO8, _0));
        _for_each_inner_iomux_function!(((SD_DATA2, SD_DATAn, 2), GPIO9, _0));
        _for_each_inner_iomux_function!(((SD_DATA3, SD_DATAn, 3), GPIO10, _0));
        _for_each_inner_iomux_function!(((SD_DATA2, SD_DATAn, 2), GPIO12, _4));
        _for_each_inner_iomux_function!(((SD_DATA3, SD_DATAn, 3), GPIO13, _4));
        _for_each_inner_iomux_function!(((VSPICS0, VSPICSn, 0), GPIO5, _1));
        _for_each_inner_iomux_function!(((SD1_CLK, SDn_CLK, 1), GPIO6, _3));
        _for_each_inner_iomux_function!(((SD2_CLK, SDn_CLK, 2), GPIO14, _3));
        _for_each_inner_iomux_function!(((SPICS0, SPICSn, 0), GPIO11, _1));
        _for_each_inner_iomux_function!(((SD1_CMD, SDn_CMD, 1), GPIO11, _3));
        _for_each_inner_iomux_function!(((SD2_CMD, SDn_CMD, 2), GPIO15, _3));
        _for_each_inner_iomux_function!(((EMAC_TXD3, EMAC_TXDn, 3), GPIO12, _5));
        _for_each_inner_iomux_function!(((EMAC_TXD2, EMAC_TXDn, 2), GPIO14, _5));
        _for_each_inner_iomux_function!(((EMAC_TXD0, EMAC_TXDn, 0), GPIO19, _5));
        _for_each_inner_iomux_function!(((EMAC_TXD1, EMAC_TXDn, 1), GPIO22, _5));
        _for_each_inner_iomux_function!(((HSPICS0, HSPICSn, 0), GPIO15, _1));
        _for_each_inner_iomux_function!(((EMAC_CLK_180, EMAC_CLK_n, 180), GPIO17, _5));
        _for_each_inner_iomux_function!(((SD1_STROBE, SDn_STROBE, 1), GPIO23, _3));
        _for_each_inner_iomux_function!((all(CLK_OUT1, GPIO0, _1), (EMAC_TX_CLK, GPIO0,
        _5), (U0TXD, GPIO1, _0), (CLK_OUT3, GPIO1, _1), (EMAC_RXD2, GPIO1, _5), (HSPIWP,
        GPIO2, _1), (SD2_DATA0, GPIO2, _3), (SD_DATA0, GPIO2, _4), (U0RXD, GPIO3, _0),
        (CLK_OUT2, GPIO3, _1), (HSPIHD, GPIO4, _1), (SD2_DATA1, GPIO4, _3), (SD_DATA1,
        GPIO4, _4), (EMAC_TXER, GPIO4, _5), (VSPICS0, GPIO5, _1), (SD1_DATA6, GPIO5, _3),
        (EMAC_RX_CLK, GPIO5, _5), (SD_CLK, GPIO6, _0), (SPICLK, GPIO6, _1), (SD1_CLK,
        GPIO6, _3), (U1CTS, GPIO6, _4), (SD_DATA0, GPIO7, _0), (SPIQ, GPIO7, _1),
        (SD1_DATA0, GPIO7, _3), (U2RTS, GPIO7, _4), (SD_DATA1, GPIO8, _0), (SPID, GPIO8,
        _1), (SD1_DATA1, GPIO8, _3), (U2CTS, GPIO8, _4), (SD_DATA2, GPIO9, _0), (SPIHD,
        GPIO9, _1), (SD1_DATA2, GPIO9, _3), (U1RXD, GPIO9, _4), (SD_DATA3, GPIO10, _0),
        (SPIWP, GPIO10, _1), (SD1_DATA3, GPIO10, _3), (U1TXD, GPIO10, _4), (SD_CMD,
        GPIO11, _0), (SPICS0, GPIO11, _1), (SD1_CMD, GPIO11, _3), (U1RTS, GPIO11, _4),
        (MTDI, GPIO12, _0), (HSPIQ, GPIO12, _1), (SD2_DATA2, GPIO12, _3), (SD_DATA2,
        GPIO12, _4), (EMAC_TXD3, GPIO12, _5), (MTCK, GPIO13, _0), (HSPID, GPIO13, _1),
        (SD2_DATA3, GPIO13, _3), (SD_DATA3, GPIO13, _4), (EMAC_RXER, GPIO13, _5), (MTMS,
        GPIO14, _0), (HSPICLK, GPIO14, _1), (SD2_CLK, GPIO14, _3), (SD_CLK, GPIO14, _4),
        (EMAC_TXD2, GPIO14, _5), (MTDO, GPIO15, _0), (HSPICS0, GPIO15, _1), (SD2_CMD,
        GPIO15, _3), (SD_CMD, GPIO15, _4), (EMAC_RXD3, GPIO15, _5), (SD1_DATA4, GPIO16,
        _3), (U2RXD, GPIO16, _4), (EMAC_CLK_OUT, GPIO16, _5), (SD1_DATA5, GPIO17, _3),
        (U2TXD, GPIO17, _4), (EMAC_CLK_180, GPIO17, _5), (VSPICLK, GPIO18, _1),
        (SD1_DATA7, GPIO18, _3), (VSPIQ, GPIO19, _1), (U0CTS, GPIO19, _3), (EMAC_TXD0,
        GPIO19, _5), (VSPIHD, GPIO21, _1), (EMAC_TXEN, GPIO21, _5), (VSPIWP, GPIO22, _1),
        (U0RTS, GPIO22, _3), (EMAC_TXD1, GPIO22, _5), (VSPID, GPIO23, _1), (SD1_STROBE,
        GPIO23, _3), (EMAC_RXD0, GPIO25, _5), (EMAC_RXD1, GPIO26, _5), (EMAC_RXDV,
        GPIO27, _5))); _for_each_inner_iomux_function!((CLK_OUTn((CLK_OUT1, CLK_OUTn, 1),
        GPIO0, _1), ((CLK_OUT3, CLK_OUTn, 3), GPIO1, _1), ((CLK_OUT2, CLK_OUTn, 2),
        GPIO3, _1))); _for_each_inner_iomux_function!((EMAC_RXDn((EMAC_RXD2, EMAC_RXDn,
        2), GPIO1, _5), ((EMAC_RXD3, EMAC_RXDn, 3), GPIO15, _5), ((EMAC_RXD0, EMAC_RXDn,
        0), GPIO25, _5), ((EMAC_RXD1, EMAC_RXDn, 1), GPIO26, _5)));
        _for_each_inner_iomux_function!((SDn_DATAm((SD2_DATA0, SDn_DATAm, 2, 0), GPIO2,
        _3), ((SD2_DATA1, SDn_DATAm, 2, 1), GPIO4, _3), ((SD1_DATA6, SDn_DATAm, 1, 6),
        GPIO5, _3), ((SD1_DATA0, SDn_DATAm, 1, 0), GPIO7, _3), ((SD1_DATA1, SDn_DATAm, 1,
        1), GPIO8, _3), ((SD1_DATA2, SDn_DATAm, 1, 2), GPIO9, _3), ((SD1_DATA3,
        SDn_DATAm, 1, 3), GPIO10, _3), ((SD2_DATA2, SDn_DATAm, 2, 2), GPIO12, _3),
        ((SD2_DATA3, SDn_DATAm, 2, 3), GPIO13, _3), ((SD1_DATA4, SDn_DATAm, 1, 4),
        GPIO16, _3), ((SD1_DATA5, SDn_DATAm, 1, 5), GPIO17, _3), ((SD1_DATA7, SDn_DATAm,
        1, 7), GPIO18, _3))); _for_each_inner_iomux_function!((SD_DATAn((SD_DATA0,
        SD_DATAn, 0), GPIO2, _4), ((SD_DATA1, SD_DATAn, 1), GPIO4, _4), ((SD_DATA0,
        SD_DATAn, 0), GPIO7, _0), ((SD_DATA1, SD_DATAn, 1), GPIO8, _0), ((SD_DATA2,
        SD_DATAn, 2), GPIO9, _0), ((SD_DATA3, SD_DATAn, 3), GPIO10, _0), ((SD_DATA2,
        SD_DATAn, 2), GPIO12, _4), ((SD_DATA3, SD_DATAn, 3), GPIO13, _4)));
        _for_each_inner_iomux_function!((VSPICSn((VSPICS0, VSPICSn, 0), GPIO5, _1)));
        _for_each_inner_iomux_function!((SDn_CLK((SD1_CLK, SDn_CLK, 1), GPIO6, _3),
        ((SD2_CLK, SDn_CLK, 2), GPIO14, _3)));
        _for_each_inner_iomux_function!((SPICSn((SPICS0, SPICSn, 0), GPIO11, _1)));
        _for_each_inner_iomux_function!((SDn_CMD((SD1_CMD, SDn_CMD, 1), GPIO11, _3),
        ((SD2_CMD, SDn_CMD, 2), GPIO15, _3)));
        _for_each_inner_iomux_function!((EMAC_TXDn((EMAC_TXD3, EMAC_TXDn, 3), GPIO12,
        _5), ((EMAC_TXD2, EMAC_TXDn, 2), GPIO14, _5), ((EMAC_TXD0, EMAC_TXDn, 0), GPIO19,
        _5), ((EMAC_TXD1, EMAC_TXDn, 1), GPIO22, _5)));
        _for_each_inner_iomux_function!((HSPICSn((HSPICS0, HSPICSn, 0), GPIO15, _1)));
        _for_each_inner_iomux_function!((EMAC_CLK_n((EMAC_CLK_180, EMAC_CLK_n, 180),
        GPIO17, _5))); _for_each_inner_iomux_function!((SDn_STROBE((SD1_STROBE,
        SDn_STROBE, 1), GPIO23, _3)));
    };
}
/// Returns the name of the GPIO that provides the given signal, as a string.
///
/// The macro takes the name of a direct function - a digital IO MUX function, an analog
/// function, or an LP IO MUX function - and expands to a string literal like `"GPIO4"`. It
/// is meant to keep documentation free of per-chip pin lists.
///
/// Signals that are not wired to a pad on this chip have to be routed through the GPIO
/// matrix, which can reach any pad. The macro has no pad to return for those, so it accepts
/// an optional fallback to expand to instead. The fallback is not validated.
///
/// If multiple pads provide the signal, the macro returns one that is not reserved for some
/// other purpose, such as booting or interfacing with flash.
///
/// Example usage:
/// - `gpio_for_signal!(ADC1_CH0)`
/// - `gpio_for_signal!(LP_I2C_SDA, "GPIO6")`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! gpio_for_signal {
    (CLK_OUT1 $(, $_fallback:literal)?) => {
        "GPIO0"
    };
    (EMAC_TX_CLK $(, $_fallback:literal)?) => {
        "GPIO0"
    };
    (ADC2_CH1 $(, $_fallback:literal)?) => {
        "GPIO0"
    };
    (TOUCH1 $(, $_fallback:literal)?) => {
        "GPIO0"
    };
    (LP_GPIO11 $(, $_fallback:literal)?) => {
        "GPIO0"
    };
    (SAR_I2C_SDA $(, $_fallback:literal)?) => {
        "GPIO0"
    };
    (U0TXD $(, $_fallback:literal)?) => {
        "GPIO1"
    };
    (CLK_OUT3 $(, $_fallback:literal)?) => {
        "GPIO1"
    };
    (EMAC_RXD2 $(, $_fallback:literal)?) => {
        "GPIO1"
    };
    (HSPIWP $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (SD2_DATA0 $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (SD_DATA0 $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (ADC2_CH2 $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (TOUCH2 $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (LP_GPIO12 $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (SAR_I2C_SCL $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (U0RXD $(, $_fallback:literal)?) => {
        "GPIO3"
    };
    (CLK_OUT2 $(, $_fallback:literal)?) => {
        "GPIO3"
    };
    (HSPIHD $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (SD2_DATA1 $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (SD_DATA1 $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (EMAC_TXER $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (ADC2_CH0 $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (TOUCH0 $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (LP_GPIO10 $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (VSPICS0 $(, $_fallback:literal)?) => {
        "GPIO5"
    };
    (SD1_DATA6 $(, $_fallback:literal)?) => {
        "GPIO5"
    };
    (EMAC_RX_CLK $(, $_fallback:literal)?) => {
        "GPIO5"
    };
    (SD_CLK $(, $_fallback:literal)?) => {
        "GPIO6"
    };
    (SPICLK $(, $_fallback:literal)?) => {
        "GPIO6"
    };
    (SD1_CLK $(, $_fallback:literal)?) => {
        "GPIO6"
    };
    (U1CTS $(, $_fallback:literal)?) => {
        "GPIO6"
    };
    (SPIQ $(, $_fallback:literal)?) => {
        "GPIO7"
    };
    (SD1_DATA0 $(, $_fallback:literal)?) => {
        "GPIO7"
    };
    (U2RTS $(, $_fallback:literal)?) => {
        "GPIO7"
    };
    (SPID $(, $_fallback:literal)?) => {
        "GPIO8"
    };
    (SD1_DATA1 $(, $_fallback:literal)?) => {
        "GPIO8"
    };
    (U2CTS $(, $_fallback:literal)?) => {
        "GPIO8"
    };
    (SD_DATA2 $(, $_fallback:literal)?) => {
        "GPIO9"
    };
    (SPIHD $(, $_fallback:literal)?) => {
        "GPIO9"
    };
    (SD1_DATA2 $(, $_fallback:literal)?) => {
        "GPIO9"
    };
    (U1RXD $(, $_fallback:literal)?) => {
        "GPIO9"
    };
    (SD_DATA3 $(, $_fallback:literal)?) => {
        "GPIO10"
    };
    (SPIWP $(, $_fallback:literal)?) => {
        "GPIO10"
    };
    (SD1_DATA3 $(, $_fallback:literal)?) => {
        "GPIO10"
    };
    (U1TXD $(, $_fallback:literal)?) => {
        "GPIO10"
    };
    (SD_CMD $(, $_fallback:literal)?) => {
        "GPIO11"
    };
    (SPICS0 $(, $_fallback:literal)?) => {
        "GPIO11"
    };
    (SD1_CMD $(, $_fallback:literal)?) => {
        "GPIO11"
    };
    (U1RTS $(, $_fallback:literal)?) => {
        "GPIO11"
    };
    (MTDI $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (HSPIQ $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (SD2_DATA2 $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (EMAC_TXD3 $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (ADC2_CH5 $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (TOUCH5 $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (LP_GPIO15 $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (MTCK $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (HSPID $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (SD2_DATA3 $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (EMAC_RXER $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (ADC2_CH4 $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (TOUCH4 $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (LP_GPIO14 $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (MTMS $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (HSPICLK $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (SD2_CLK $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (EMAC_TXD2 $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (ADC2_CH6 $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (TOUCH6 $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (LP_GPIO16 $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (MTDO $(, $_fallback:literal)?) => {
        "GPIO15"
    };
    (HSPICS0 $(, $_fallback:literal)?) => {
        "GPIO15"
    };
    (SD2_CMD $(, $_fallback:literal)?) => {
        "GPIO15"
    };
    (EMAC_RXD3 $(, $_fallback:literal)?) => {
        "GPIO15"
    };
    (ADC2_CH3 $(, $_fallback:literal)?) => {
        "GPIO15"
    };
    (TOUCH3 $(, $_fallback:literal)?) => {
        "GPIO15"
    };
    (LP_GPIO13 $(, $_fallback:literal)?) => {
        "GPIO15"
    };
    (SD1_DATA4 $(, $_fallback:literal)?) => {
        "GPIO16"
    };
    (U2RXD $(, $_fallback:literal)?) => {
        "GPIO16"
    };
    (EMAC_CLK_OUT $(, $_fallback:literal)?) => {
        "GPIO16"
    };
    (SD1_DATA5 $(, $_fallback:literal)?) => {
        "GPIO17"
    };
    (U2TXD $(, $_fallback:literal)?) => {
        "GPIO17"
    };
    (EMAC_CLK_180 $(, $_fallback:literal)?) => {
        "GPIO17"
    };
    (VSPICLK $(, $_fallback:literal)?) => {
        "GPIO18"
    };
    (SD1_DATA7 $(, $_fallback:literal)?) => {
        "GPIO18"
    };
    (VSPIQ $(, $_fallback:literal)?) => {
        "GPIO19"
    };
    (U0CTS $(, $_fallback:literal)?) => {
        "GPIO19"
    };
    (EMAC_TXD0 $(, $_fallback:literal)?) => {
        "GPIO19"
    };
    (VSPIHD $(, $_fallback:literal)?) => {
        "GPIO21"
    };
    (EMAC_TXEN $(, $_fallback:literal)?) => {
        "GPIO21"
    };
    (VSPIWP $(, $_fallback:literal)?) => {
        "GPIO22"
    };
    (U0RTS $(, $_fallback:literal)?) => {
        "GPIO22"
    };
    (EMAC_TXD1 $(, $_fallback:literal)?) => {
        "GPIO22"
    };
    (VSPID $(, $_fallback:literal)?) => {
        "GPIO23"
    };
    (SD1_STROBE $(, $_fallback:literal)?) => {
        "GPIO23"
    };
    (EMAC_RXD0 $(, $_fallback:literal)?) => {
        "GPIO25"
    };
    (DAC1 $(, $_fallback:literal)?) => {
        "GPIO25"
    };
    (ADC2_CH8 $(, $_fallback:literal)?) => {
        "GPIO25"
    };
    (LP_GPIO6 $(, $_fallback:literal)?) => {
        "GPIO25"
    };
    (EMAC_RXD1 $(, $_fallback:literal)?) => {
        "GPIO26"
    };
    (DAC2 $(, $_fallback:literal)?) => {
        "GPIO26"
    };
    (ADC2_CH9 $(, $_fallback:literal)?) => {
        "GPIO26"
    };
    (LP_GPIO7 $(, $_fallback:literal)?) => {
        "GPIO26"
    };
    (EMAC_RXDV $(, $_fallback:literal)?) => {
        "GPIO27"
    };
    (ADC2_CH7 $(, $_fallback:literal)?) => {
        "GPIO27"
    };
    (TOUCH7 $(, $_fallback:literal)?) => {
        "GPIO27"
    };
    (LP_GPIO17 $(, $_fallback:literal)?) => {
        "GPIO27"
    };
    (XTAL_32K_P $(, $_fallback:literal)?) => {
        "GPIO32"
    };
    (ADC1_CH4 $(, $_fallback:literal)?) => {
        "GPIO32"
    };
    (TOUCH9 $(, $_fallback:literal)?) => {
        "GPIO32"
    };
    (LP_GPIO9 $(, $_fallback:literal)?) => {
        "GPIO32"
    };
    (XTAL_32K_N $(, $_fallback:literal)?) => {
        "GPIO33"
    };
    (ADC1_CH5 $(, $_fallback:literal)?) => {
        "GPIO33"
    };
    (TOUCH8 $(, $_fallback:literal)?) => {
        "GPIO33"
    };
    (LP_GPIO8 $(, $_fallback:literal)?) => {
        "GPIO33"
    };
    (ADC1_CH6 $(, $_fallback:literal)?) => {
        "GPIO34"
    };
    (LP_GPIO4 $(, $_fallback:literal)?) => {
        "GPIO34"
    };
    (ADC1_CH7 $(, $_fallback:literal)?) => {
        "GPIO35"
    };
    (LP_GPIO5 $(, $_fallback:literal)?) => {
        "GPIO35"
    };
    (ADC_H $(, $_fallback:literal)?) => {
        "GPIO36"
    };
    (ADC1_CH0 $(, $_fallback:literal)?) => {
        "GPIO36"
    };
    (LP_GPIO0 $(, $_fallback:literal)?) => {
        "GPIO36"
    };
    (ADC1_CH1 $(, $_fallback:literal)?) => {
        "GPIO37"
    };
    (LP_GPIO1 $(, $_fallback:literal)?) => {
        "GPIO37"
    };
    (ADC1_CH2 $(, $_fallback:literal)?) => {
        "GPIO38"
    };
    (LP_GPIO2 $(, $_fallback:literal)?) => {
        "GPIO38"
    };
    (ADC1_CH3 $(, $_fallback:literal)?) => {
        "GPIO39"
    };
    (LP_GPIO3 $(, $_fallback:literal)?) => {
        "GPIO39"
    };
    ($_signal:ident, $fallback:literal) => {
        $fallback
    };
}
/// Defines the `InputSignal` and `OutputSignal` enums.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_io_mux_signals {
    () => {
        #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
        #[derive(Debug, PartialEq, Copy, Clone)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum InputSignal {
            SPICLK                = 0,
            SPIQ                  = 1,
            SPID                  = 2,
            SPIHD                 = 3,
            SPIWP                 = 4,
            SPICS0                = 5,
            SPICS1                = 6,
            SPICS2                = 7,
            HSPICLK               = 8,
            HSPIQ                 = 9,
            HSPID                 = 10,
            HSPICS0               = 11,
            HSPIHD                = 12,
            HSPIWP                = 13,
            U0RXD                 = 14,
            U0CTS                 = 15,
            U0DSR                 = 16,
            U1RXD                 = 17,
            U1CTS                 = 18,
            I2S0O_BCK             = 23,
            I2S1O_BCK             = 24,
            I2S0O_WS              = 25,
            I2S1O_WS              = 26,
            I2S0I_BCK             = 27,
            I2S0I_WS              = 28,
            I2CEXT0_SCL           = 29,
            I2CEXT0_SDA           = 30,
            PWM0_SYNC0            = 31,
            PWM0_SYNC1            = 32,
            PWM0_SYNC2            = 33,
            PWM0_F0               = 34,
            PWM0_F1               = 35,
            PWM0_F2               = 36,
            PCNT0_SIG_CH0         = 39,
            PCNT0_SIG_CH1         = 40,
            PCNT0_CTRL_CH0        = 41,
            PCNT0_CTRL_CH1        = 42,
            PCNT1_SIG_CH0         = 43,
            PCNT1_SIG_CH1         = 44,
            PCNT1_CTRL_CH0        = 45,
            PCNT1_CTRL_CH1        = 46,
            PCNT2_SIG_CH0         = 47,
            PCNT2_SIG_CH1         = 48,
            PCNT2_CTRL_CH0        = 49,
            PCNT2_CTRL_CH1        = 50,
            PCNT3_SIG_CH0         = 51,
            PCNT3_SIG_CH1         = 52,
            PCNT3_CTRL_CH0        = 53,
            PCNT3_CTRL_CH1        = 54,
            PCNT4_SIG_CH0         = 55,
            PCNT4_SIG_CH1         = 56,
            PCNT4_CTRL_CH0        = 57,
            PCNT4_CTRL_CH1        = 58,
            HSPICS1               = 61,
            HSPICS2               = 62,
            VSPICLK               = 63,
            VSPIQ                 = 64,
            VSPID                 = 65,
            VSPIHD                = 66,
            VSPIWP                = 67,
            VSPICS0               = 68,
            VSPICS1               = 69,
            VSPICS2               = 70,
            PCNT5_SIG_CH0         = 71,
            PCNT5_SIG_CH1         = 72,
            PCNT5_CTRL_CH0        = 73,
            PCNT5_CTRL_CH1        = 74,
            PCNT6_SIG_CH0         = 75,
            PCNT6_SIG_CH1         = 76,
            PCNT6_CTRL_CH0        = 77,
            PCNT6_CTRL_CH1        = 78,
            PCNT7_SIG_CH0         = 79,
            PCNT7_SIG_CH1         = 80,
            PCNT7_CTRL_CH0        = 81,
            PCNT7_CTRL_CH1        = 82,
            RMT_SIG_0             = 83,
            RMT_SIG_1             = 84,
            RMT_SIG_2             = 85,
            RMT_SIG_3             = 86,
            RMT_SIG_4             = 87,
            RMT_SIG_5             = 88,
            RMT_SIG_6             = 89,
            RMT_SIG_7             = 90,
            TWAI_RX               = 94,
            I2CEXT1_SCL           = 95,
            I2CEXT1_SDA           = 96,
            HOST_CARD_DETECT_N_1  = 97,
            HOST_CARD_DETECT_N_2  = 98,
            HOST_CARD_WRITE_PRT_1 = 99,
            HOST_CARD_WRITE_PRT_2 = 100,
            HOST_CARD_INT_N_1     = 101,
            HOST_CARD_INT_N_2     = 102,
            PWM1_SYNC0            = 103,
            PWM1_SYNC1            = 104,
            PWM1_SYNC2            = 105,
            PWM1_F0               = 106,
            PWM1_F1               = 107,
            PWM1_F2               = 108,
            PWM0_CAP0             = 109,
            PWM0_CAP1             = 110,
            PWM0_CAP2             = 111,
            PWM1_CAP0             = 112,
            PWM1_CAP1             = 113,
            PWM1_CAP2             = 114,
            I2S0I_DATA_0          = 140,
            I2S0I_DATA_1          = 141,
            I2S0I_DATA_2          = 142,
            I2S0I_DATA_3          = 143,
            I2S0I_DATA_4          = 144,
            I2S0I_DATA_5          = 145,
            I2S0I_DATA_6          = 146,
            I2S0I_DATA_7          = 147,
            I2S0I_DATA_8          = 148,
            I2S0I_DATA_9          = 149,
            I2S0I_DATA_10         = 150,
            I2S0I_DATA_11         = 151,
            I2S0I_DATA_12         = 152,
            I2S0I_DATA_13         = 153,
            I2S0I_DATA_14         = 154,
            I2S0I_DATA_15         = 155,
            I2S1I_BCK             = 164,
            I2S1I_WS              = 165,
            I2S1I_DATA_0          = 166,
            I2S1I_DATA_1          = 167,
            I2S1I_DATA_2          = 168,
            I2S1I_DATA_3          = 169,
            I2S1I_DATA_4          = 170,
            I2S1I_DATA_5          = 171,
            I2S1I_DATA_6          = 172,
            I2S1I_DATA_7          = 173,
            I2S1I_DATA_8          = 174,
            I2S1I_DATA_9          = 175,
            I2S1I_DATA_10         = 176,
            I2S1I_DATA_11         = 177,
            I2S1I_DATA_12         = 178,
            I2S1I_DATA_13         = 179,
            I2S1I_DATA_14         = 180,
            I2S1I_DATA_15         = 181,
            I2S0I_H_SYNC          = 190,
            I2S0I_V_SYNC          = 191,
            I2S0I_H_ENABLE        = 192,
            I2S1I_H_SYNC          = 193,
            I2S1I_V_SYNC          = 194,
            I2S1I_H_ENABLE        = 195,
            U2RXD                 = 198,
            U2CTS                 = 199,
            EMAC_MDC              = 200,
            EMAC_MDI              = 201,
            EMAC_CRS              = 202,
            EMAC_COL              = 203,
            PCMFSYNC              = 204,
            PCMCLK                = 205,
            PCMDIN                = 206,
            SD_CMD,
            SD_DATA0,
            SD_DATA1,
            SD_DATA2,
            SD_DATA3,
            SD1_DATA0,
            SD1_DATA1,
            SD1_DATA2,
            SD1_DATA3,
            SD1_DATA4,
            SD1_DATA5,
            SD1_DATA6,
            SD1_DATA7,
            SD2_DATA0,
            SD2_DATA1,
            SD2_DATA2,
            SD2_DATA3,
            EMAC_TX_CLK,
            EMAC_RXD2,
            EMAC_TXER,
            EMAC_RX_CLK,
            EMAC_RXER,
            EMAC_RXD3,
            EMAC_RXD0,
            EMAC_RXD1,
            EMAC_RXDV,
            MTDI,
            MTCK,
            MTMS,
        }
        #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
        #[derive(Debug, PartialEq, Copy, Clone)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum OutputSignal {
            SPICLK                   = 0,
            SPIQ                     = 1,
            SPID                     = 2,
            SPIHD                    = 3,
            SPIWP                    = 4,
            SPICS0                   = 5,
            SPICS1                   = 6,
            SPICS2                   = 7,
            HSPICLK                  = 8,
            HSPIQ                    = 9,
            HSPID                    = 10,
            HSPICS0                  = 11,
            HSPIHD                   = 12,
            HSPIWP                   = 13,
            U0TXD                    = 14,
            U0RTS                    = 15,
            U0DTR                    = 16,
            U1TXD                    = 17,
            U1RTS                    = 18,
            I2S0O_BCK                = 23,
            I2S1O_BCK                = 24,
            I2S0O_WS                 = 25,
            I2S1O_WS                 = 26,
            I2S0I_BCK                = 27,
            I2S0I_WS                 = 28,
            I2CEXT0_SCL              = 29,
            I2CEXT0_SDA              = 30,
            SDIO_TOHOST_INT          = 31,
            PWM0_0A                  = 32,
            PWM0_0B                  = 33,
            PWM0_1A                  = 34,
            PWM0_1B                  = 35,
            PWM0_2A                  = 36,
            PWM0_2B                  = 37,
            HSPICS1                  = 61,
            HSPICS2                  = 62,
            VSPICLK                  = 63,
            VSPIQ                    = 64,
            VSPID                    = 65,
            VSPIHD                   = 66,
            VSPIWP                   = 67,
            VSPICS0                  = 68,
            VSPICS1                  = 69,
            VSPICS2                  = 70,
            LEDC_HS_SIG0             = 71,
            LEDC_HS_SIG1             = 72,
            LEDC_HS_SIG2             = 73,
            LEDC_HS_SIG3             = 74,
            LEDC_HS_SIG4             = 75,
            LEDC_HS_SIG5             = 76,
            LEDC_HS_SIG6             = 77,
            LEDC_HS_SIG7             = 78,
            LEDC_LS_SIG0             = 79,
            LEDC_LS_SIG1             = 80,
            LEDC_LS_SIG2             = 81,
            LEDC_LS_SIG3             = 82,
            LEDC_LS_SIG4             = 83,
            LEDC_LS_SIG5             = 84,
            LEDC_LS_SIG6             = 85,
            LEDC_LS_SIG7             = 86,
            RMT_SIG_0                = 87,
            RMT_SIG_1                = 88,
            RMT_SIG_2                = 89,
            RMT_SIG_3                = 90,
            RMT_SIG_4                = 91,
            RMT_SIG_5                = 92,
            RMT_SIG_6                = 93,
            RMT_SIG_7                = 94,
            I2CEXT1_SCL              = 95,
            I2CEXT1_SDA              = 96,
            HOST_CCMD_OD_PULLUP_EN_N = 97,
            HOST_RST_N_1             = 98,
            HOST_RST_N_2             = 99,
            GPIO_SD0                 = 100,
            GPIO_SD1                 = 101,
            GPIO_SD2                 = 102,
            GPIO_SD3                 = 103,
            GPIO_SD4                 = 104,
            GPIO_SD5                 = 105,
            GPIO_SD6                 = 106,
            GPIO_SD7                 = 107,
            PWM1_0A                  = 108,
            PWM1_0B                  = 109,
            PWM1_1A                  = 110,
            PWM1_1B                  = 111,
            PWM1_2A                  = 112,
            PWM1_2B                  = 113,
            TWAI_TX                  = 123,
            TWAI_BUS_OFF_ON          = 124,
            TWAI_CLKOUT              = 125,
            I2S0O_DATA_0             = 140,
            I2S0O_DATA_1             = 141,
            I2S0O_DATA_2             = 142,
            I2S0O_DATA_3             = 143,
            I2S0O_DATA_4             = 144,
            I2S0O_DATA_5             = 145,
            I2S0O_DATA_6             = 146,
            I2S0O_DATA_7             = 147,
            I2S0O_DATA_8             = 148,
            I2S0O_DATA_9             = 149,
            I2S0O_DATA_10            = 150,
            I2S0O_DATA_11            = 151,
            I2S0O_DATA_12            = 152,
            I2S0O_DATA_13            = 153,
            I2S0O_DATA_14            = 154,
            I2S0O_DATA_15            = 155,
            I2S0O_DATA_16            = 156,
            I2S0O_DATA_17            = 157,
            I2S0O_DATA_18            = 158,
            I2S0O_DATA_19            = 159,
            I2S0O_DATA_20            = 160,
            I2S0O_DATA_21            = 161,
            I2S0O_DATA_22            = 162,
            I2S0O_DATA_23            = 163,
            I2S1I_BCK                = 164,
            I2S1I_WS                 = 165,
            I2S1O_DATA_0             = 166,
            I2S1O_DATA_1             = 167,
            I2S1O_DATA_2             = 168,
            I2S1O_DATA_3             = 169,
            I2S1O_DATA_4             = 170,
            I2S1O_DATA_5             = 171,
            I2S1O_DATA_6             = 172,
            I2S1O_DATA_7             = 173,
            I2S1O_DATA_8             = 174,
            I2S1O_DATA_9             = 175,
            I2S1O_DATA_10            = 176,
            I2S1O_DATA_11            = 177,
            I2S1O_DATA_12            = 178,
            I2S1O_DATA_13            = 179,
            I2S1O_DATA_14            = 180,
            I2S1O_DATA_15            = 181,
            I2S1O_DATA_16            = 182,
            I2S1O_DATA_17            = 183,
            I2S1O_DATA_18            = 184,
            I2S1O_DATA_19            = 185,
            I2S1O_DATA_20            = 186,
            I2S1O_DATA_21            = 187,
            I2S1O_DATA_22            = 188,
            I2S1O_DATA_23            = 189,
            U2TXD                    = 198,
            U2RTS                    = 199,
            EMAC_MDC                 = 200,
            EMAC_MDO                 = 201,
            EMAC_CRS                 = 202,
            EMAC_COL                 = 203,
            BT_AUDIO0RQ              = 204,
            BT_AUDIO1RQ              = 205,
            BT_AUDIO2RQ              = 206,
            BLE_AUDIO0RQ             = 207,
            BLE_AUDIO1RQ             = 208,
            BLE_AUDIO2RQ             = 209,
            PCMFSYNC                 = 210,
            PCMCLK                   = 211,
            PCMDOUT                  = 212,
            BLE_AUDIO_SYNC0_P        = 213,
            BLE_AUDIO_SYNC1_P        = 214,
            BLE_AUDIO_SYNC2_P        = 215,
            ANT_SEL0                 = 216,
            ANT_SEL1                 = 217,
            ANT_SEL2                 = 218,
            ANT_SEL3                 = 219,
            ANT_SEL4                 = 220,
            ANT_SEL5                 = 221,
            ANT_SEL6                 = 222,
            ANT_SEL7                 = 223,
            SIGNAL_224               = 224,
            SIGNAL_225               = 225,
            SIGNAL_226               = 226,
            SIGNAL_227               = 227,
            SIGNAL_228               = 228,
            GPIO                     = 256,
            CLK_OUT1,
            CLK_OUT2,
            CLK_OUT3,
            SD_CLK,
            SD_CMD,
            SD_DATA0,
            SD_DATA1,
            SD_DATA2,
            SD_DATA3,
            SD1_CLK,
            SD1_CMD,
            SD1_DATA0,
            SD1_DATA1,
            SD1_DATA2,
            SD1_DATA3,
            SD1_DATA4,
            SD1_DATA5,
            SD1_DATA6,
            SD1_DATA7,
            SD1_STROBE,
            SD2_CLK,
            SD2_CMD,
            SD2_DATA0,
            SD2_DATA1,
            SD2_DATA2,
            SD2_DATA3,
            EMAC_TX_CLK,
            EMAC_TXER,
            EMAC_TXD3,
            EMAC_RXER,
            EMAC_TXD2,
            EMAC_CLK_OUT,
            EMAC_CLK_180,
            EMAC_TXD0,
            EMAC_TXEN,
            EMAC_TXD1,
            MTDO,
        }
    };
}
/// Defines the `LpFunction` enum.
///
/// The enum only contains the LP IO MUX functions that the chip implements. It is
/// empty on chips without an LP IO peripheral.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_lp_functions {
    () => {
        /// LP IO MUX function of a pad.
        ///
        /// This is the low-power counterpart of `AlternateFunction`: it selects which function
        /// drives a pad while the pad belongs to the low-power domain.
        #[derive(Debug, Eq, PartialEq, Copy, Clone, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum LpFunction {
            /// LP IO MUX function 0.
            _0 = 0,
            /// LP IO MUX function 3.
            _3 = 3,
        }
        impl LpFunction {
            /// The function that connects the pad to the LP GPIO peripheral.
            pub const LP_GPIO: Self = Self::_0;
        }
    };
}
/// Defines and implements the `io_mux_reg` function.
///
/// The generated function has the following signature:
///
/// ```rust,ignore
/// pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO0 {
///     // ...
/// # unimplemented!()
/// }
/// ```
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[expect(clippy::crate_in_macro_def)]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_io_mux_reg {
    () => {
        pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO0 {
            let iomux = crate::peripherals::IO_MUX::regs();
            match gpio_num {
                0 => iomux.gpio0(),
                1 => iomux.gpio1(),
                2 => iomux.gpio2(),
                3 => iomux.gpio3(),
                4 => iomux.gpio4(),
                5 => iomux.gpio5(),
                6 => iomux.gpio6(),
                7 => iomux.gpio7(),
                8 => iomux.gpio8(),
                9 => iomux.gpio9(),
                10 => iomux.gpio10(),
                11 => iomux.gpio11(),
                12 => iomux.gpio12(),
                13 => iomux.gpio13(),
                14 => iomux.gpio14(),
                15 => iomux.gpio15(),
                16 => iomux.gpio16(),
                17 => iomux.gpio17(),
                18 => iomux.gpio18(),
                19 => iomux.gpio19(),
                20 => iomux.gpio20(),
                21 => iomux.gpio21(),
                22 => iomux.gpio22(),
                23 => iomux.gpio23(),
                25 => iomux.gpio25(),
                26 => iomux.gpio26(),
                27 => iomux.gpio27(),
                32 => iomux.gpio32(),
                33 => iomux.gpio33(),
                34 => iomux.gpio34(),
                35 => iomux.gpio35(),
                36 => iomux.gpio36(),
                37 => iomux.gpio37(),
                38 => iomux.gpio38(),
                39 => iomux.gpio39(),
                other => panic!("GPIO {} does not exist", other),
            }
        }
    };
}