esp_metadata_generated/

_generated_esp32c2.rs

// Do NOT edit this file directly. Make your changes to esp-metadata,
// then run `cargo update-metadata`.

/// The name of the chip as `&str`
///
/// # Example
///
/// ```rust, no_run
/// use esp_hal::chip;
/// let chip_name = chip!();
#[doc = concat!("assert_eq!(chip_name, ", chip!(), ")")]
/// ```
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! chip {
    () => {
        "esp32c2"
    };
}
/// The pretty name of the chip as `&str`
///
/// # Example
///
/// ```rust, no_run
/// use esp_hal::chip;
/// let chip_name = chip_pretty!();
#[doc = concat!("assert_eq!(chip_name, ", chip_pretty!(), ")")]
/// ```
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! chip_pretty {
    () => {
        "ESP32-C2"
    };
}
/// The properties of this chip and its drivers.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! property {
    ("chip") => {
        "esp32c2"
    };
    ("arch") => {
        "riscv"
    };
    ("cores") => {
        1
    };
    ("cores", str) => {
        stringify!(1)
    };
    ("trm") => {
        "https://www.espressif.com/sites/default/files/documentation/esp8684_technical_reference_manual_en.pdf"
    };
    ("gpio.version") => {
        2
    };
    ("gpio.version", str) => {
        stringify!(2)
    };
    ("gpio.has_input_sync") => {
        true
    };
    ("gpio.gpio_function") => {
        1
    };
    ("gpio.gpio_function", str) => {
        stringify!(1)
    };
    ("gpio.constant_0_input") => {
        31
    };
    ("gpio.constant_0_input", str) => {
        stringify!(31)
    };
    ("gpio.constant_1_input") => {
        30
    };
    ("gpio.constant_1_input", str) => {
        stringify!(30)
    };
    ("gpio.remap_iomux_pin_registers") => {
        false
    };
    ("gpio.func_in_sel_offset") => {
        0
    };
    ("gpio.func_in_sel_offset", str) => {
        stringify!(0)
    };
    ("gpio.need_soft_isolate_during_pd") => {
        false
    };
    ("gpio.has_bank_1") => {
        false
    };
    ("gpio.input_signal_max") => {
        100
    };
    ("gpio.input_signal_max", str) => {
        stringify!(100)
    };
    ("gpio.output_signal_max") => {
        128
    };
    ("gpio.output_signal_max", str) => {
        stringify!(128)
    };
    ("dedicated_gpio.version") => {
        "riscv_v1"
    };
    ("dedicated_gpio.needs_initialization") => {
        false
    };
    ("dedicated_gpio.channel_count") => {
        8
    };
    ("dedicated_gpio.channel_count", str) => {
        stringify!(8)
    };
    ("lp_io.version") => {
        "v3"
    };
    ("lp_io.has_gpio_matrix") => {
        false
    };
    ("uart.ram_size") => {
        128
    };
    ("uart.ram_size", str) => {
        stringify!(128)
    };
    ("uart.version") => {
        1
    };
    ("uart.version", str) => {
        stringify!(1)
    };
    ("uart.peripheral_controls_mem_clk") => {
        false
    };
    ("uart.has_sclk_divider") => {
        true
    };
    ("uart.has_sclk_enable") => {
        true
    };
    ("i2c_master.version") => {
        3
    };
    ("i2c_master.version", str) => {
        stringify!(3)
    };
    ("i2c_master.has_fsm_timeouts") => {
        true
    };
    ("i2c_master.has_hw_bus_clear") => {
        true
    };
    ("i2c_master.has_bus_timeout_enable") => {
        true
    };
    ("i2c_master.separate_filter_config_registers") => {
        false
    };
    ("i2c_master.can_estimate_nack_reason") => {
        false
    };
    ("i2c_master.has_conf_update") => {
        true
    };
    ("i2c_master.has_reliable_fsm_reset") => {
        false
    };
    ("i2c_master.has_arbitration_en") => {
        true
    };
    ("i2c_master.has_tx_fifo_watermark") => {
        true
    };
    ("i2c_master.bus_timeout_is_exponential") => {
        true
    };
    ("i2c_master.has_pd_en") => {
        true
    };
    ("i2c_master.max_bus_timeout") => {
        31
    };
    ("i2c_master.max_bus_timeout", str) => {
        stringify!(31)
    };
    ("i2c_master.ll_intr_mask") => {
        262143
    };
    ("i2c_master.ll_intr_mask", str) => {
        stringify!(262143)
    };
    ("i2c_master.fifo_size") => {
        16
    };
    ("i2c_master.fifo_size", str) => {
        stringify!(16)
    };
    ("spi_master.version") => {
        3
    };
    ("spi_master.version", str) => {
        stringify!(3)
    };
    ("spi_master.fifo_size") => {
        64
    };
    ("spi_master.fifo_size", str) => {
        stringify!(64)
    };
    ("spi_master.bit_order_is_bool") => {
        false
    };
    ("spi_master.has_octal") => {
        false
    };
    ("spi_master.has_app_interrupts") => {
        true
    };
    ("spi_master.has_dma_segmented_transfer") => {
        true
    };
    ("spi_master.has_clk_pre_div") => {
        false
    };
    ("spi_master.dma_can_access_flash") => {
        false
    };
    ("bt.controller") => {
        "npl"
    };
    ("wifi.has_wifi6") => {
        false
    };
    ("wifi.mac_version") => {
        1
    };
    ("wifi.mac_version", str) => {
        stringify!(1)
    };
    ("wifi.has_5g") => {
        false
    };
    ("wifi.csi_supported") => {
        false
    };
    ("wifi.has_nan") => {
        false
    };
    ("wifi.has_ftm") => {
        true
    };
    ("phy.combo_module") => {
        true
    };
    ("adc.controller") => {
        "digital"
    };
    ("adc.channel_count") => {
        5
    };
    ("adc.channel_count", str) => {
        stringify!(5)
    };
    ("adc.line_calibration") => {
        true
    };
    ("adc.curve_calibration") => {
        false
    };
    ("adc.basic_calibration") => {
        true
    };
    ("adc.calibration_v1_scheme_supported") => {
        true
    };
    ("adc.channel_compensation") => {
        false
    };
    ("adc.pcr_clock") => {
        false
    };
    ("adc.pcr_sar_clk_div") => {
        false
    };
    ("adc.sar_power_override") => {
        false
    };
    ("ledc.version") => {
        2
    };
    ("ledc.version", str) => {
        stringify!(2)
    };
    ("ledc.channel_count") => {
        6
    };
    ("ledc.channel_count", str) => {
        stringify!(6)
    };
    ("timergroup.timg_has_timer1") => {
        false
    };
    ("timergroup.timg_has_divcnt_rst") => {
        true
    };
    ("timergroup.wdt_has_conf_update") => {
        true
    };
    ("ecc.zero_extend_writes") => {
        true
    };
    ("ecc.separate_jacobian_point_memory") => {
        false
    };
    ("ecc.has_memory_clock_gate") => {
        false
    };
    ("ecc.supports_enhanced_security") => {
        false
    };
    ("ecc.mem_block_size") => {
        32
    };
    ("rng.apb_cycle_wait_num") => {
        16
    };
    ("rng.apb_cycle_wait_num", str) => {
        stringify!(16)
    };
    ("rng.trng_supported") => {
        true
    };
    ("rng.is_lp_sys") => {
        false
    };
    ("sleep.light_sleep") => {
        true
    };
    ("sleep.deep_sleep") => {
        true
    };
    ("sleep.rejectable_mask") => {
        1852
    };
    ("sleep.pin_wakeup_version") => {
        2
    };
    ("sleep.pin_wakeup_version", str) => {
        stringify!(2)
    };
    ("sleep.deep_sleep_needs_gpio_isolation") => {
        true
    };
    ("assist_debug.has_sp_monitor") => {
        true
    };
    ("assist_debug.has_region_monitor") => {
        false
    };
    ("dma.mem2mem_requires_peripheral") => {
        false
    };
    ("dma.ext_mem_configurable_block_size") => {
        false
    };
    ("dma.separate_in_out_interrupts") => {
        false
    };
    ("dma.gdma_version") => {
        1
    };
    ("dma.gdma_version", str) => {
        stringify!(1)
    };
    ("interrupts.status_registers") => {
        2
    };
    ("interrupts.status_registers", str) => {
        stringify!(2)
    };
    ("interrupts.disabled_interrupt") => {
        0
    };
    ("mmu.page_size") => {
        65536
    };
    ("mmu.page_size", str) => {
        stringify!(65536)
    };
    ("mmu.entry_num") => {
        64
    };
    ("mmu.entry_num", str) => {
        stringify!(64)
    };
    ("rom.has_crc_le") => {
        true
    };
    ("rom.has_crc_be") => {
        true
    };
    ("rom.has_md5_bsd") => {
        false
    };
    ("rom.has_md5_mbedtls") => {
        true
    };
    ("soc.cpu_has_branch_predictor") => {
        false
    };
    ("soc.cpu_has_csr_pc") => {
        true
    };
    ("soc.cpu_has_zcmp_workaround") => {
        false
    };
    ("soc.multi_core_enabled") => {
        false
    };
    ("soc.internal_memory_cached") => {
        false
    };
    ("soc.has_swd_watchdog") => {
        true
    };
    ("soc.cpu_mcause_mask") => {
        31
    };
    ("soc.cpu_mcause_mask", str) => {
        stringify!(31)
    };
    ("soc.cpu_pmp_granularity") => {
        4
    };
    ("soc.cpu_pmp_granularity", str) => {
        stringify!(4)
    };
    ("clock_tree.system_pre_div_in") => {
        [crate ::soc::clocks::SystemPreDivInConfig::Xtal, crate
        ::soc::clocks::SystemPreDivInConfig::RcFast]
    };
    ("clock_tree.system_pre_div.divisor") => {
        (0, 1023)
    };
    ("clock_tree.cpu_pll_div.divisor") => {
        [4, 6]
    };
    ("clock_tree.cpu_clk") => {
        [crate ::soc::clocks::CpuClkConfig::Xtal, crate
        ::soc::clocks::CpuClkConfig::RcFast, crate ::soc::clocks::CpuClkConfig::Pll]
    };
    ("clock_tree.apb_clk") => {
        [crate ::soc::clocks::ApbClkConfig::Pll40m, crate
        ::soc::clocks::ApbClkConfig::Cpu]
    };
    ("clock_tree.crypto_clk") => {
        [crate ::soc::clocks::CryptoClkConfig::Pll80m, crate
        ::soc::clocks::CryptoClkConfig::Cpu]
    };
    ("clock_tree.mspi_clk") => {
        [crate ::soc::clocks::MspiClkConfig::CpuDiv2, crate
        ::soc::clocks::MspiClkConfig::Cpu]
    };
    ("clock_tree.rc_fast_clk_div_n.divisor") => {
        (0, 3)
    };
    ("clock_tree.rtc_slow_clk") => {
        [crate ::soc::clocks::RtcSlowClkConfig::OscSlow, crate
        ::soc::clocks::RtcSlowClkConfig::RcSlow, crate
        ::soc::clocks::RtcSlowClkConfig::RcFast]
    };
    ("clock_tree.ble_lp_clk.sclk") => {
        [crate ::soc::clocks::BleLpClkSclk::Xtal, crate
        ::soc::clocks::BleLpClkSclk::RcSlow]
    };
    ("clock_tree.ble_lp_clk.divisor") => {
        (0, 255)
    };
    ("clock_tree.rtc_fast_clk") => {
        [crate ::soc::clocks::RtcFastClkConfig::Xtal, crate
        ::soc::clocks::RtcFastClkConfig::Rc]
    };
    ("clock_tree.low_power_clk") => {
        [crate ::soc::clocks::LowPowerClkConfig::Xtal, crate
        ::soc::clocks::LowPowerClkConfig::RcFast, crate
        ::soc::clocks::LowPowerClkConfig::OscSlow, crate
        ::soc::clocks::LowPowerClkConfig::RtcSlow]
    };
    ("clock_tree.timg_calibration_clock") => {
        [crate ::soc::clocks::TimgCalibrationClockConfig::RcSlowClk, crate
        ::soc::clocks::TimgCalibrationClockConfig::RcFastDivClk, crate
        ::soc::clocks::TimgCalibrationClockConfig::Osc32kClk]
    };
    ("clock_tree.timg.function_clock") => {
        [crate ::soc::clocks::TimgFunctionClockConfig::XtalClk, crate
        ::soc::clocks::TimgFunctionClockConfig::Pll40m]
    };
    ("clock_tree.timg.wdt_clock") => {
        [crate ::soc::clocks::TimgWdtClockConfig::Pll40m, crate
        ::soc::clocks::TimgWdtClockConfig::XtalClk]
    };
    ("clock_tree.uart.function_clock.sclk") => {
        [crate ::soc::clocks::UartFunctionClockSclk::PllF40m, crate
        ::soc::clocks::UartFunctionClockSclk::RcFast, crate
        ::soc::clocks::UartFunctionClockSclk::Xtal]
    };
    ("clock_tree.uart.function_clock.div_num") => {
        (0, 255)
    };
    ("clock_tree.uart.baud_rate_generator.fractional") => {
        (0, 15)
    };
    ("clock_tree.uart.baud_rate_generator.integral") => {
        (0, 4095)
    };
    ("clock_tree.i2c.function_clock.sclk") => {
        [crate ::soc::clocks::I2cFunctionClockSclk::Xtal, crate
        ::soc::clocks::I2cFunctionClockSclk::RcFast]
    };
    ("clock_tree.i2c.function_clock.div_num") => {
        (0, 255)
    };
    ("clock_tree.spi.function_clock") => {
        [crate ::soc::clocks::SpiFunctionClockConfig::Xtal, crate
        ::soc::clocks::SpiFunctionClockConfig::Pll40m]
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dedicated_gpio {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dedicated_gpio { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_dedicated_gpio!((0));
        _for_each_inner_dedicated_gpio!((1)); _for_each_inner_dedicated_gpio!((2));
        _for_each_inner_dedicated_gpio!((3)); _for_each_inner_dedicated_gpio!((4));
        _for_each_inner_dedicated_gpio!((5)); _for_each_inner_dedicated_gpio!((6));
        _for_each_inner_dedicated_gpio!((7)); _for_each_inner_dedicated_gpio!((0, 0,
        CPU_GPIO_0)); _for_each_inner_dedicated_gpio!((0, 1, CPU_GPIO_1));
        _for_each_inner_dedicated_gpio!((0, 2, CPU_GPIO_2));
        _for_each_inner_dedicated_gpio!((0, 3, CPU_GPIO_3));
        _for_each_inner_dedicated_gpio!((0, 4, CPU_GPIO_4));
        _for_each_inner_dedicated_gpio!((0, 5, CPU_GPIO_5));
        _for_each_inner_dedicated_gpio!((0, 6, CPU_GPIO_6));
        _for_each_inner_dedicated_gpio!((0, 7, CPU_GPIO_7));
        _for_each_inner_dedicated_gpio!((channels(0), (1), (2), (3), (4), (5), (6),
        (7))); _for_each_inner_dedicated_gpio!((signals(0, 0, CPU_GPIO_0), (0, 1,
        CPU_GPIO_1), (0, 2, CPU_GPIO_2), (0, 3, CPU_GPIO_3), (0, 4, CPU_GPIO_4), (0, 5,
        CPU_GPIO_5), (0, 6, CPU_GPIO_6), (0, 7, CPU_GPIO_7)));
    };
}
/// Defines the `LpInputSignal` and `LpOutputSignal` enums.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_lp_io_signals {
    () => {};
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_ecc_working_mode {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_ecc_working_mode { $(($pattern) => $code;)* ($other
        : tt) => {} } _for_each_inner_ecc_working_mode!((0, AffinePointMultiplication));
        _for_each_inner_ecc_working_mode!((1, FiniteFieldDivision));
        _for_each_inner_ecc_working_mode!((2, AffinePointVerification));
        _for_each_inner_ecc_working_mode!((3, AffinePointVerificationAndMultiplication));
        _for_each_inner_ecc_working_mode!((4, JacobianPointMultiplication));
        _for_each_inner_ecc_working_mode!((6, JacobianPointVerification));
        _for_each_inner_ecc_working_mode!((7,
        AffinePointVerificationAndJacobianPointMultiplication));
        _for_each_inner_ecc_working_mode!((all(0, AffinePointMultiplication), (1,
        FiniteFieldDivision), (2, AffinePointVerification), (3,
        AffinePointVerificationAndMultiplication), (4, JacobianPointMultiplication), (6,
        JacobianPointVerification), (7,
        AffinePointVerificationAndJacobianPointMultiplication)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_ecc_curve {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_ecc_curve { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_ecc_curve!((0, P192, 192));
        _for_each_inner_ecc_curve!((1, P256, 256)); _for_each_inner_ecc_curve!((all(0,
        P192, 192), (1, P256, 256)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sha_algorithm {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sha_algorithm { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_sha_algorithm!((Sha1, "SHA-1"(sizes : 64, 20, 8)
        (insecure_against : "collision", "length extension"), 0));
        _for_each_inner_sha_algorithm!((Sha224, "SHA-224"(sizes : 64, 28, 8)
        (insecure_against : "length extension"), 1));
        _for_each_inner_sha_algorithm!((Sha256, "SHA-256"(sizes : 64, 32, 8)
        (insecure_against : "length extension"), 2));
        _for_each_inner_sha_algorithm!((algos(Sha1, "SHA-1"(sizes : 64, 20, 8)
        (insecure_against : "collision", "length extension"), 0), (Sha224,
        "SHA-224"(sizes : 64, 28, 8) (insecure_against : "length extension"), 1),
        (Sha256, "SHA-256"(sizes : 64, 32, 8) (insecure_against : "length extension"),
        2)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_wakeup_source {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_wakeup_source { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_wakeup_source!((Gpio, 2));
        _for_each_inner_wakeup_source!((Timer, 3)); _for_each_inner_wakeup_source!((Sdio,
        4)); _for_each_inner_wakeup_source!((Wifi, 5));
        _for_each_inner_wakeup_source!((Uart0, 6));
        _for_each_inner_wakeup_source!((Uart1, 7));
        _for_each_inner_wakeup_source!((Touch, 8)); _for_each_inner_wakeup_source!((Ulp,
        9)); _for_each_inner_wakeup_source!((Bt, 10));
        _for_each_inner_wakeup_source!((all(Gpio, 2), (Timer, 3), (Sdio, 4), (Wifi, 5),
        (Uart0, 6), (Uart1, 7), (Touch, 8), (Ulp, 9), (Bt, 10)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_dma_engine!(("AHB_GDMA"));
        _for_each_inner_dma_engine!((all("AHB_GDMA")));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dma_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dma_channel { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH0));
        _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH0, 0, interrupt = DMA_CH0,
        compatible = [SPI2, SHA])); _for_each_inner_dma_channel!((names("AHB_GDMA",
        DMA_CH0))); _for_each_inner_dma_channel!((separate_any_type));
        _for_each_inner_dma_channel!((shared("AHB_GDMA", DMA_CH0, 0, interrupt = DMA_CH0,
        compatible = [SPI2, SHA]))); _for_each_inner_dma_channel!((split));
        _for_each_inner_dma_channel!((no_own_interrupt));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dma_channel_peri_pair {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dma_channel_peri_pair { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA",
        DMA_CH0, SPI2)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH0,
        SHA)); _for_each_inner_dma_channel_peri_pair!((channels("AHB_GDMA", DMA_CH0,
        SPI2), ("AHB_GDMA", DMA_CH0, SHA)));
        _for_each_inner_dma_channel_peri_pair!((any_channels));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_mem2mem_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_mem2mem_channel { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_mem2mem_channel!(("AHB_GDMA", AhbGdma,
        AhbGdmaChannel, DMA_CH0, 2)); _for_each_inner_mem2mem_channel!(("AHB_GDMA",
        AhbGdma, AhbGdmaChannel, 0, 2)); _for_each_inner_mem2mem_channel!(("AHB_GDMA",
        AhbGdma, AhbGdmaChannel)); _for_each_inner_mem2mem_channel!((channels("AHB_GDMA",
        AhbGdma, AhbGdmaChannel, DMA_CH0, 2)));
        _for_each_inner_mem2mem_channel!((erased("AHB_GDMA", AhbGdma, AhbGdmaChannel, 0,
        2))); _for_each_inner_mem2mem_channel!((engines("AHB_GDMA", AhbGdma,
        AhbGdmaChannel)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_sha_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_sha_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _with_inner_sha_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_spi_master_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_spi_master_dma_engine { $(($pattern) => $code;)* ($other
        : tt) => {} } _with_inner_spi_master_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_spi_slave_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_spi_slave_dma_engine { $(($pattern) => $code;)* ($other
        : tt) => {} } _with_inner_spi_slave_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_interrupt {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_interrupt { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_interrupt!(([disabled 0] 0));
        _for_each_inner_interrupt!(([reserved 0] 1));
        _for_each_inner_interrupt!(([context_switch 0] 2));
        _for_each_inner_interrupt!(([direct_bindable 0] 3));
        _for_each_inner_interrupt!(([direct_bindable 1] 4));
        _for_each_inner_interrupt!(([direct_bindable 2] 5));
        _for_each_inner_interrupt!(([direct_bindable 3] 6));
        _for_each_inner_interrupt!(([direct_bindable 4] 7));
        _for_each_inner_interrupt!(([direct_bindable 5] 8));
        _for_each_inner_interrupt!(([direct_bindable 6] 9));
        _for_each_inner_interrupt!(([direct_bindable 7] 10));
        _for_each_inner_interrupt!(([direct_bindable 8] 11));
        _for_each_inner_interrupt!(([direct_bindable 9] 12));
        _for_each_inner_interrupt!(([direct_bindable 10] 13));
        _for_each_inner_interrupt!(([direct_bindable 11] 14));
        _for_each_inner_interrupt!(([direct_bindable 12] 15));
        _for_each_inner_interrupt!(([direct_bindable 13] 16));
        _for_each_inner_interrupt!(([vector 0] 17)); _for_each_inner_interrupt!(([vector
        1] 18)); _for_each_inner_interrupt!(([vector 2] 19));
        _for_each_inner_interrupt!(([vector 3] 20)); _for_each_inner_interrupt!(([vector
        4] 21)); _for_each_inner_interrupt!(([vector 5] 22));
        _for_each_inner_interrupt!(([vector 6] 23)); _for_each_inner_interrupt!(([vector
        7] 24)); _for_each_inner_interrupt!(([vector 8] 25));
        _for_each_inner_interrupt!(([vector 9] 26)); _for_each_inner_interrupt!(([vector
        10] 27)); _for_each_inner_interrupt!(([vector 11] 28));
        _for_each_inner_interrupt!(([vector 12] 29)); _for_each_inner_interrupt!(([vector
        13] 30)); _for_each_inner_interrupt!(([vector 14] 31));
        _for_each_inner_interrupt!((all([disabled 0] 0), ([reserved 0] 1),
        ([context_switch 0] 2), ([direct_bindable 0] 3), ([direct_bindable 1] 4),
        ([direct_bindable 2] 5), ([direct_bindable 3] 6), ([direct_bindable 4] 7),
        ([direct_bindable 5] 8), ([direct_bindable 6] 9), ([direct_bindable 7] 10),
        ([direct_bindable 8] 11), ([direct_bindable 9] 12), ([direct_bindable 10] 13),
        ([direct_bindable 11] 14), ([direct_bindable 12] 15), ([direct_bindable 13] 16),
        ([vector 0] 17), ([vector 1] 18), ([vector 2] 19), ([vector 3] 20), ([vector 4]
        21), ([vector 5] 22), ([vector 6] 23), ([vector 7] 24), ([vector 8] 25), ([vector
        9] 26), ([vector 10] 27), ([vector 11] 28), ([vector 12] 29), ([vector 13] 30),
        ([vector 14] 31)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_classified_interrupt {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_classified_interrupt { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_classified_interrupt!(([direct_bindable 0]
        3)); _for_each_inner_classified_interrupt!(([direct_bindable 1] 4));
        _for_each_inner_classified_interrupt!(([direct_bindable 2] 5));
        _for_each_inner_classified_interrupt!(([direct_bindable 3] 6));
        _for_each_inner_classified_interrupt!(([direct_bindable 4] 7));
        _for_each_inner_classified_interrupt!(([direct_bindable 5] 8));
        _for_each_inner_classified_interrupt!(([direct_bindable 6] 9));
        _for_each_inner_classified_interrupt!(([direct_bindable 7] 10));
        _for_each_inner_classified_interrupt!(([direct_bindable 8] 11));
        _for_each_inner_classified_interrupt!(([direct_bindable 9] 12));
        _for_each_inner_classified_interrupt!(([direct_bindable 10] 13));
        _for_each_inner_classified_interrupt!(([direct_bindable 11] 14));
        _for_each_inner_classified_interrupt!(([direct_bindable 12] 15));
        _for_each_inner_classified_interrupt!(([direct_bindable 13] 16));
        _for_each_inner_classified_interrupt!(([vector 0] 17));
        _for_each_inner_classified_interrupt!(([vector 1] 18));
        _for_each_inner_classified_interrupt!(([vector 2] 19));
        _for_each_inner_classified_interrupt!(([vector 3] 20));
        _for_each_inner_classified_interrupt!(([vector 4] 21));
        _for_each_inner_classified_interrupt!(([vector 5] 22));
        _for_each_inner_classified_interrupt!(([vector 6] 23));
        _for_each_inner_classified_interrupt!(([vector 7] 24));
        _for_each_inner_classified_interrupt!(([vector 8] 25));
        _for_each_inner_classified_interrupt!(([vector 9] 26));
        _for_each_inner_classified_interrupt!(([vector 10] 27));
        _for_each_inner_classified_interrupt!(([vector 11] 28));
        _for_each_inner_classified_interrupt!(([vector 12] 29));
        _for_each_inner_classified_interrupt!(([vector 13] 30));
        _for_each_inner_classified_interrupt!(([vector 14] 31));
        _for_each_inner_classified_interrupt!(([reserved 0] 1));
        _for_each_inner_classified_interrupt!(([context_switch 0] 2));
        _for_each_inner_classified_interrupt!((direct_bindable([direct_bindable 0] 3),
        ([direct_bindable 1] 4), ([direct_bindable 2] 5), ([direct_bindable 3] 6),
        ([direct_bindable 4] 7), ([direct_bindable 5] 8), ([direct_bindable 6] 9),
        ([direct_bindable 7] 10), ([direct_bindable 8] 11), ([direct_bindable 9] 12),
        ([direct_bindable 10] 13), ([direct_bindable 11] 14), ([direct_bindable 12] 15),
        ([direct_bindable 13] 16)));
        _for_each_inner_classified_interrupt!((vector([vector 0] 17), ([vector 1] 18),
        ([vector 2] 19), ([vector 3] 20), ([vector 4] 21), ([vector 5] 22), ([vector 6]
        23), ([vector 7] 24), ([vector 8] 25), ([vector 9] 26), ([vector 10] 27),
        ([vector 11] 28), ([vector 12] 29), ([vector 13] 30), ([vector 14] 31)));
        _for_each_inner_classified_interrupt!((reserved([reserved 0] 1)));
        _for_each_inner_classified_interrupt!((context_switch([context_switch 0] 2)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_interrupt_priority {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_interrupt_priority { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_interrupt_priority!((0, 1, Priority1,
        Level1)); _for_each_inner_interrupt_priority!((1, 2, Priority2, Level2));
        _for_each_inner_interrupt_priority!((2, 3, Priority3, Level3));
        _for_each_inner_interrupt_priority!((3, 4, Priority4, Level4));
        _for_each_inner_interrupt_priority!((4, 5, Priority5, Level5));
        _for_each_inner_interrupt_priority!((5, 6, Priority6, Level6));
        _for_each_inner_interrupt_priority!((6, 7, Priority7, Level7));
        _for_each_inner_interrupt_priority!((7, 8, Priority8, Level8));
        _for_each_inner_interrupt_priority!((8, 9, Priority9, Level9));
        _for_each_inner_interrupt_priority!((9, 10, Priority10, Level10));
        _for_each_inner_interrupt_priority!((10, 11, Priority11, Level11));
        _for_each_inner_interrupt_priority!((11, 12, Priority12, Level12));
        _for_each_inner_interrupt_priority!((12, 13, Priority13, Level13));
        _for_each_inner_interrupt_priority!((13, 14, Priority14, Level14));
        _for_each_inner_interrupt_priority!((14, 15, Priority15, Level15));
        _for_each_inner_interrupt_priority!((all(0, 1, Priority1, Level1), (1, 2,
        Priority2, Level2), (2, 3, Priority3, Level3), (3, 4, Priority4, Level4), (4, 5,
        Priority5, Level5), (5, 6, Priority6, Level6), (6, 7, Priority7, Level7), (7, 8,
        Priority8, Level8), (8, 9, Priority9, Level9), (9, 10, Priority10, Level10), (10,
        11, Priority11, Level11), (11, 12, Priority12, Level12), (12, 13, Priority13,
        Level13), (13, 14, Priority14, Level14), (14, 15, Priority15, Level15)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sw_interrupt {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sw_interrupt { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_sw_interrupt!((0, FROM_CPU_INTR0,
        software_interrupt0)); _for_each_inner_sw_interrupt!((1, FROM_CPU_INTR1,
        software_interrupt1)); _for_each_inner_sw_interrupt!((2, FROM_CPU_INTR2,
        software_interrupt2)); _for_each_inner_sw_interrupt!((3, FROM_CPU_INTR3,
        software_interrupt3)); _for_each_inner_sw_interrupt!((all(0, FROM_CPU_INTR0,
        software_interrupt0), (1, FROM_CPU_INTR1, software_interrupt1), (2,
        FROM_CPU_INTR2, software_interrupt2), (3, FROM_CPU_INTR3, software_interrupt3)));
    };
}
#[macro_export]
/// ESP-HAL must provide implementation for the following functions:
/// ```rust, no_run
/// // XTAL_CLK
///
/// fn configure_xtal_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<XtalClkConfig>,
///     _new_config: XtalClkConfig,
/// ) {
///     todo!()
/// }
///
/// // PLL_CLK
///
/// fn enable_pll_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RC_FAST_CLK
///
/// fn enable_rc_fast_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // OSC_SLOW_CLK
///
/// fn enable_osc_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RC_SLOW_CLK
///
/// fn enable_rc_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RC_FAST_DIV_CLK
///
/// fn enable_rc_fast_div_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // SYSTEM_PRE_DIV_IN
///
/// fn enable_system_pre_div_in_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_system_pre_div_in_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<SystemPreDivInConfig>,
///     _new_config: SystemPreDivInConfig,
/// ) {
///     todo!()
/// }
///
/// // SYSTEM_PRE_DIV
///
/// fn enable_system_pre_div_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_system_pre_div_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<SystemPreDivConfig>,
///     _new_config: SystemPreDivConfig,
/// ) {
///     todo!()
/// }
///
/// // CPU_PLL_DIV
///
/// fn enable_cpu_pll_div_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_cpu_pll_div_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CpuPllDivConfig>,
///     _new_config: CpuPllDivConfig,
/// ) {
///     todo!()
/// }
///
/// // APB_CLK
///
/// fn enable_apb_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_apb_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<ApbClkConfig>,
///     _new_config: ApbClkConfig,
/// ) {
///     todo!()
/// }
///
/// // CRYPTO_CLK
///
/// fn enable_crypto_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_crypto_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CryptoClkConfig>,
///     _new_config: CryptoClkConfig,
/// ) {
///     todo!()
/// }
///
/// // MSPI_CLK
///
/// fn enable_mspi_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_mspi_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<MspiClkConfig>,
///     _new_config: MspiClkConfig,
/// ) {
///     todo!()
/// }
///
/// // CPU_CLK
///
/// fn configure_cpu_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CpuClkConfig>,
///     _new_config: CpuClkConfig,
/// ) {
///     todo!()
/// }
///
/// // PLL_40M
///
/// fn enable_pll_40m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_60M
///
/// fn enable_pll_60m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_80M
///
/// fn enable_pll_80m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // CPU_DIV2
///
/// fn enable_cpu_div2_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RC_FAST_CLK_DIV_N
///
/// fn enable_rc_fast_clk_div_n_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_rc_fast_clk_div_n_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RcFastClkDivNConfig>,
///     _new_config: RcFastClkDivNConfig,
/// ) {
///     todo!()
/// }
///
/// // XTAL_DIV_CLK
///
/// fn enable_xtal_div_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RTC_SLOW_CLK
///
/// fn enable_rtc_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_rtc_slow_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RtcSlowClkConfig>,
///     _new_config: RtcSlowClkConfig,
/// ) {
///     todo!()
/// }
///
/// // BLE_LP_XTAL_CLK
///
/// fn enable_ble_lp_xtal_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // BLE_LP_RC_SLOW_CLK
///
/// fn enable_ble_lp_rc_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // BLE_LP_CLK
///
/// fn enable_ble_lp_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_ble_lp_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<BleLpClkConfig>,
///     _new_config: BleLpClkConfig,
/// ) {
///     todo!()
/// }
///
/// // RTC_FAST_CLK
///
/// fn enable_rtc_fast_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_rtc_fast_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<RtcFastClkConfig>,
///     _new_config: RtcFastClkConfig,
/// ) {
///     todo!()
/// }
///
/// // LOW_POWER_CLK
///
/// fn enable_low_power_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_low_power_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<LowPowerClkConfig>,
///     _new_config: LowPowerClkConfig,
/// ) {
///     todo!()
/// }
///
/// // UART_MEM_CLK
///
/// fn enable_uart_mem_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // TIMG_CALIBRATION_CLOCK
///
/// fn enable_timg_calibration_clock_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_timg_calibration_clock_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<TimgCalibrationClockConfig>,
///     _new_config: TimgCalibrationClockConfig,
/// ) {
///     todo!()
/// }
///
/// impl AdcInstance {
///     // ADC_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
/// }
/// impl I2cInstance {
///     // I2C_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<I2cFunctionClockConfig>,
///         _new_config: I2cFunctionClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl SpiInstance {
///     // SPI_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<SpiFunctionClockConfig>,
///         _new_config: SpiFunctionClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl TimgInstance {
///     // TIMG_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<TimgFunctionClockConfig>,
///         _new_config: TimgFunctionClockConfig,
///     ) {
///         todo!()
///     }
///
///     // TIMG_WDT_CLOCK
///
///     fn enable_wdt_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_wdt_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<TimgWdtClockConfig>,
///         _new_config: TimgWdtClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl UartInstance {
///     // UART_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<UartFunctionClockConfig>,
///         _new_config: UartFunctionClockConfig,
///     ) {
///         todo!()
///     }
///
///     // UART_MEM_CLOCK
///
///     fn enable_mem_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     // UART_BAUD_RATE_GENERATOR
///
///     fn enable_baud_rate_generator_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_baud_rate_generator_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<UartBaudRateGeneratorConfig>,
///         _new_config: UartBaudRateGeneratorConfig,
///     ) {
///         todo!()
///     }
/// }
/// ```
macro_rules! define_clock_tree_types {
    () => {
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum AdcInstance {
            ApbSaradc = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2cInstance {
            I2c0 = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SpiInstance {
            Spi2 = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgInstance {
            Timg0 = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum UartInstance {
            Uart0 = 0,
            Uart1 = 1,
        }
        /// Selects the output frequency of `XTAL_CLK`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum XtalClkConfig {
            /// 26 MHz
            _26,
            /// 40 MHz
            _40,
        }
        impl XtalClkConfig {
            pub fn value(&self) -> u32 {
                match self {
                    XtalClkConfig::_26 => 26000000,
                    XtalClkConfig::_40 => 40000000,
                }
            }
        }
        /// The list of clock signals that the `SYSTEM_PRE_DIV_IN` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SystemPreDivInConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
        }
        /// Configures the `SYSTEM_PRE_DIV` clock node.
        ///
        /// The output is calculated as `OUTPUT = SYSTEM_PRE_DIV_IN / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct SystemPreDivConfig {
            divisor: u32,
        }
        impl SystemPreDivConfig {
            /// Creates a new configuration for the SYSTEM_PRE_DIV clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 1023).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 1023,
                    "`SYSTEM_PRE_DIV` divisor must be between 0 and 1023 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CpuPllDivDivisor {
            /// Selects `divisor = 4`.
            _4 = 4,
            /// Selects `divisor = 6`.
            _6 = 6,
        }
        impl CpuPllDivDivisor {
            /// Creates a new parameter value from a raw number.
            pub const fn new(raw: u32) -> Self {
                match raw {
                    4 => Self::_4,
                    6 => Self::_6,
                    _ => ::core::panic!("Invalid CPU_PLL_DIV divisor value"),
                }
            }
        }
        /// Configures the `CPU_PLL_DIV` clock node.
        ///
        /// The output is calculated as `OUTPUT = PLL_CLK / divisor`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct CpuPllDivConfig {
            divisor: CpuPllDivDivisor,
        }
        impl CpuPllDivConfig {
            /// Creates a new configuration for the CPU_PLL_DIV clock node.
            pub const fn new(divisor: CpuPllDivDivisor) -> Self {
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// The list of clock signals that the `APB_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum ApbClkConfig {
            /// Selects `PLL_40M`.
            Pll40m,
            /// Selects `CPU_CLK`.
            Cpu,
        }
        /// The list of clock signals that the `CRYPTO_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CryptoClkConfig {
            /// Selects `PLL_80M`.
            Pll80m,
            /// Selects `CPU_CLK`.
            Cpu,
        }
        /// The list of clock signals that the `MSPI_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum MspiClkConfig {
            /// Selects `CPU_DIV2`.
            CpuDiv2,
            /// Selects `CPU_CLK`.
            Cpu,
        }
        /// The list of clock signals that the `CPU_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CpuClkConfig {
            /// Selects `SYSTEM_PRE_DIV`.
            Xtal,
            /// Selects `SYSTEM_PRE_DIV`.
            RcFast,
            /// Selects `CPU_PLL_DIV`.
            Pll,
        }
        /// Configures the `RC_FAST_CLK_DIV_N` clock node.
        ///
        /// The output is calculated as `OUTPUT = RC_FAST_CLK / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct RcFastClkDivNConfig {
            divisor: u32,
        }
        impl RcFastClkDivNConfig {
            /// Creates a new configuration for the RC_FAST_CLK_DIV_N clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 3).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 3,
                    "`RC_FAST_CLK_DIV_N` divisor must be between 0 and 3 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// The list of clock signals that the `RTC_SLOW_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RtcSlowClkConfig {
            /// Selects `OSC_SLOW_CLK`.
            OscSlow,
            /// Selects `RC_SLOW_CLK`.
            RcSlow,
            /// Selects `RC_FAST_DIV_CLK`.
            RcFast,
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum BleLpClkSclk {
            #[default]
            /// Selects `BLE_LP_XTAL_CLK`.
            Xtal,
            /// Selects `BLE_LP_RC_SLOW_CLK`.
            RcSlow,
        }
        /// Configures the `BLE_LP_CLK` clock node.
        ///
        /// The output is calculated as `OUTPUT = sclk / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct BleLpClkConfig {
            sclk: BleLpClkSclk,
            divisor: u32,
        }
        impl BleLpClkConfig {
            /// Creates a new configuration for the BLE_LP_CLK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(sclk: BleLpClkSclk, divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 255,
                    "`BLE_LP_CLK` divisor must be between 0 and 255 (inclusive)."
                );
                Self { sclk, divisor }
            }
            pub fn sclk(self) -> BleLpClkSclk {
                self.sclk
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// The list of clock signals that the `RTC_FAST_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum RtcFastClkConfig {
            /// Selects `XTAL_DIV_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK_DIV_N`.
            Rc,
        }
        /// The list of clock signals that the `LOW_POWER_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum LowPowerClkConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
            /// Selects `OSC_SLOW_CLK`.
            OscSlow,
            /// Selects `RTC_SLOW_CLK`.
            RtcSlow,
        }
        /// The list of clock signals that the `UART_MEM_CLK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum UartMemClkConfig {
            #[default]
            /// Selects `XTAL_CLK`.
            Xtal,
        }
        /// The list of clock signals that the `TIMG_CALIBRATION_CLOCK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgCalibrationClockConfig {
            /// Selects `RC_SLOW_CLK`.
            RcSlowClk,
            /// Selects `RC_FAST_DIV_CLK`.
            RcFastDivClk,
            /// Selects `OSC_SLOW_CLK`.
            Osc32kClk,
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2cFunctionClockSclk {
            #[default]
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
        }
        /// Configures the `I2C0_FUNCTION_CLOCK` clock node.
        ///
        /// The output is calculated as `OUTPUT = sclk / (div_num + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct I2cFunctionClockConfig {
            sclk: I2cFunctionClockSclk,
            div_num: u32,
        }
        impl I2cFunctionClockConfig {
            /// Creates a new configuration for the FUNCTION_CLOCK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(sclk: I2cFunctionClockSclk, div_num: u32) -> Self {
                ::core::assert!(
                    div_num <= 255,
                    "`I2C0_FUNCTION_CLOCK` div_num must be between 0 and 255 (inclusive)."
                );
                Self { sclk, div_num }
            }
            pub fn sclk(self) -> I2cFunctionClockSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
        }
        /// The list of clock signals that the `SPI2_FUNCTION_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SpiFunctionClockConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            #[default]
            /// Selects `PLL_40M`.
            Pll40m,
        }
        /// The list of clock signals that the `TIMG0_FUNCTION_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgFunctionClockConfig {
            #[default]
            /// Selects `XTAL_CLK`.
            XtalClk,
            /// Selects `PLL_40M`.
            Pll40m,
        }
        /// The list of clock signals that the `TIMG0_WDT_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgWdtClockConfig {
            #[default]
            /// Selects `PLL_40M`.
            Pll40m,
            /// Selects `XTAL_CLK`.
            XtalClk,
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum UartFunctionClockSclk {
            /// Selects `PLL_40M`.
            PllF40m,
            /// Selects `RC_FAST_CLK`.
            RcFast,
            #[default]
            /// Selects `XTAL_CLK`.
            Xtal,
        }
        /// Configures the `UART0_FUNCTION_CLOCK` clock node.
        ///
        /// The output is calculated as `OUTPUT = sclk / (div_num + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct UartFunctionClockConfig {
            sclk: UartFunctionClockSclk,
            div_num: u32,
        }
        impl UartFunctionClockConfig {
            /// Creates a new configuration for the FUNCTION_CLOCK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(sclk: UartFunctionClockSclk, div_num: u32) -> Self {
                ::core::assert!(
                    div_num <= 255,
                    "`UART0_FUNCTION_CLOCK` div_num must be between 0 and 255 (inclusive)."
                );
                Self { sclk, div_num }
            }
            pub fn sclk(self) -> UartFunctionClockSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
        }
        /// Configures the `UART0_BAUD_RATE_GENERATOR` clock node.
        ///
        /// The output is calculated as `OUTPUT = (FUNCTION_CLOCK * 16) / (integral * 16 +
        /// fractional)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct UartBaudRateGeneratorConfig {
            fractional: u32,
            integral: u32,
        }
        impl UartBaudRateGeneratorConfig {
            /// Creates a new configuration for the BAUD_RATE_GENERATOR clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the fractional value is outside the
            /// valid range (0 ..= 15).
            ///
            /// Panics if the integral value is outside the
            /// valid range (0 ..= 4095).
            pub const fn new(fractional: u32, integral: u32) -> Self {
                ::core::assert!(
                    fractional <= 15,
                    "`UART0_BAUD_RATE_GENERATOR` fractional must be between 0 and 15 (inclusive)."
                );
                ::core::assert!(
                    integral <= 4095,
                    "`UART0_BAUD_RATE_GENERATOR` integral must be between 0 and 4095 (inclusive)."
                );
                Self {
                    fractional,
                    integral,
                }
            }
            pub fn fractional(self) -> u32 {
                self.fractional as u32
            }
            pub fn integral(self) -> u32 {
                self.integral as u32
            }
        }
        /// Represents the device's clock tree.
        pub struct ClockTree {
            xtal_clk: Option<XtalClkConfig>,
            system_pre_div_in: Option<SystemPreDivInConfig>,
            system_pre_div: Option<SystemPreDivConfig>,
            cpu_pll_div: Option<CpuPllDivConfig>,
            apb_clk: Option<ApbClkConfig>,
            crypto_clk: Option<CryptoClkConfig>,
            mspi_clk: Option<MspiClkConfig>,
            cpu_clk: Option<CpuClkConfig>,
            rc_fast_clk_div_n: Option<RcFastClkDivNConfig>,
            rtc_slow_clk: Option<RtcSlowClkConfig>,
            ble_lp_clk: Option<BleLpClkConfig>,
            rtc_fast_clk: Option<RtcFastClkConfig>,
            low_power_clk: Option<LowPowerClkConfig>,
            timg_calibration_clock: Option<TimgCalibrationClockConfig>,
            i2c_function_clock: [Option<I2cFunctionClockConfig>; 1],
            spi_function_clock: [Option<SpiFunctionClockConfig>; 1],
            timg_function_clock: [Option<TimgFunctionClockConfig>; 1],
            timg_wdt_clock: [Option<TimgWdtClockConfig>; 1],
            uart_function_clock: [Option<UartFunctionClockConfig>; 2],
            uart_baud_rate_generator: [Option<UartBaudRateGeneratorConfig>; 2],
            rc_fast_clk_refcount: u32,
            osc_slow_clk_refcount: u32,
            rc_slow_clk_refcount: u32,
            rc_fast_div_clk_refcount: u32,
            crypto_clk_refcount: u32,
            mspi_clk_refcount: u32,
            pll_40m_refcount: u32,
            pll_60m_refcount: u32,
            ble_lp_clk_refcount: u32,
            rtc_fast_clk_refcount: u32,
            low_power_clk_refcount: u32,
            uart_mem_clk_refcount: u32,
            timg_calibration_clock_refcount: u32,
            adc_function_clock_refcount: [u32; 1],
            i2c_function_clock_refcount: [u32; 1],
            spi_function_clock_refcount: [u32; 1],
            timg_function_clock_refcount: [u32; 1],
            timg_wdt_clock_refcount: [u32; 1],
            uart_function_clock_refcount: [u32; 2],
            uart_mem_clock_refcount: [u32; 2],
            uart_baud_rate_generator_refcount: [u32; 2],
        }
        impl ClockTree {
            /// Locks the clock tree for exclusive access.
            pub fn with<R>(f: impl FnOnce(&mut ClockTree) -> R) -> R {
                CLOCK_TREE.with(f)
            }
            /// Returns the current configuration of the XTAL_CLK clock tree node
            pub fn xtal_clk(&self) -> Option<XtalClkConfig> {
                self.xtal_clk
            }
            /// Returns the current configuration of the SYSTEM_PRE_DIV_IN clock tree node
            pub fn system_pre_div_in(&self) -> Option<SystemPreDivInConfig> {
                self.system_pre_div_in
            }
            /// Returns the current configuration of the SYSTEM_PRE_DIV clock tree node
            pub fn system_pre_div(&self) -> Option<SystemPreDivConfig> {
                self.system_pre_div
            }
            /// Returns the current configuration of the CPU_PLL_DIV clock tree node
            pub fn cpu_pll_div(&self) -> Option<CpuPllDivConfig> {
                self.cpu_pll_div
            }
            /// Returns the current configuration of the APB_CLK clock tree node
            pub fn apb_clk(&self) -> Option<ApbClkConfig> {
                self.apb_clk
            }
            /// Returns the current configuration of the CRYPTO_CLK clock tree node
            pub fn crypto_clk(&self) -> Option<CryptoClkConfig> {
                self.crypto_clk
            }
            /// Returns the current configuration of the MSPI_CLK clock tree node
            pub fn mspi_clk(&self) -> Option<MspiClkConfig> {
                self.mspi_clk
            }
            /// Returns the current configuration of the CPU_CLK clock tree node
            pub fn cpu_clk(&self) -> Option<CpuClkConfig> {
                self.cpu_clk
            }
            /// Returns the current configuration of the RC_FAST_CLK_DIV_N clock tree node
            pub fn rc_fast_clk_div_n(&self) -> Option<RcFastClkDivNConfig> {
                self.rc_fast_clk_div_n
            }
            /// Returns the current configuration of the RTC_SLOW_CLK clock tree node
            pub fn rtc_slow_clk(&self) -> Option<RtcSlowClkConfig> {
                self.rtc_slow_clk
            }
            /// Returns the current configuration of the BLE_LP_CLK clock tree node
            pub fn ble_lp_clk(&self) -> Option<BleLpClkConfig> {
                self.ble_lp_clk
            }
            /// Returns the current configuration of the RTC_FAST_CLK clock tree node
            pub fn rtc_fast_clk(&self) -> Option<RtcFastClkConfig> {
                self.rtc_fast_clk
            }
            /// Returns the current configuration of the LOW_POWER_CLK clock tree node
            pub fn low_power_clk(&self) -> Option<LowPowerClkConfig> {
                self.low_power_clk
            }
            /// Returns the current configuration of the TIMG_CALIBRATION_CLOCK clock tree node
            pub fn timg_calibration_clock(&self) -> Option<TimgCalibrationClockConfig> {
                self.timg_calibration_clock
            }
            /// Returns the current configuration of the I2C0_FUNCTION_CLOCK clock tree node
            pub fn i2c0_function_clock(&self) -> Option<I2cFunctionClockConfig> {
                self.i2c_function_clock[I2cInstance::I2c0 as usize]
            }
            /// Returns the current configuration of the SPI2_FUNCTION_CLOCK clock tree node
            pub fn spi2_function_clock(&self) -> Option<SpiFunctionClockConfig> {
                self.spi_function_clock[SpiInstance::Spi2 as usize]
            }
            /// Returns the current configuration of the TIMG0_FUNCTION_CLOCK clock tree node
            pub fn timg0_function_clock(&self) -> Option<TimgFunctionClockConfig> {
                self.timg_function_clock[TimgInstance::Timg0 as usize]
            }
            /// Returns the current configuration of the TIMG0_WDT_CLOCK clock tree node
            pub fn timg0_wdt_clock(&self) -> Option<TimgWdtClockConfig> {
                self.timg_wdt_clock[TimgInstance::Timg0 as usize]
            }
            /// Returns the current configuration of the UART0_FUNCTION_CLOCK clock tree node
            pub fn uart0_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart0 as usize]
            }
            /// Returns the current configuration of the UART0_BAUD_RATE_GENERATOR clock tree node
            pub fn uart0_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart0 as usize]
            }
            /// Returns the current configuration of the UART1_FUNCTION_CLOCK clock tree node
            pub fn uart1_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart1 as usize]
            }
            /// Returns the current configuration of the UART1_BAUD_RATE_GENERATOR clock tree node
            pub fn uart1_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart1 as usize]
            }
        }
        static CLOCK_TREE: ::esp_sync::NonReentrantMutex<ClockTree> =
            ::esp_sync::NonReentrantMutex::new(ClockTree {
                xtal_clk: None,
                system_pre_div_in: None,
                system_pre_div: None,
                cpu_pll_div: None,
                apb_clk: None,
                crypto_clk: None,
                mspi_clk: None,
                cpu_clk: None,
                rc_fast_clk_div_n: None,
                rtc_slow_clk: None,
                ble_lp_clk: None,
                rtc_fast_clk: None,
                low_power_clk: None,
                timg_calibration_clock: None,
                i2c_function_clock: [None; 1],
                spi_function_clock: [None; 1],
                timg_function_clock: [None; 1],
                timg_wdt_clock: [None; 1],
                uart_function_clock: [None; 2],
                uart_baud_rate_generator: [None; 2],
                rc_fast_clk_refcount: 0,
                osc_slow_clk_refcount: 0,
                rc_slow_clk_refcount: 0,
                rc_fast_div_clk_refcount: 0,
                crypto_clk_refcount: 0,
                mspi_clk_refcount: 0,
                pll_40m_refcount: 0,
                pll_60m_refcount: 0,
                ble_lp_clk_refcount: 0,
                rtc_fast_clk_refcount: 0,
                low_power_clk_refcount: 0,
                uart_mem_clk_refcount: 0,
                timg_calibration_clock_refcount: 0,
                adc_function_clock_refcount: [0; 1],
                i2c_function_clock_refcount: [0; 1],
                spi_function_clock_refcount: [0; 1],
                timg_function_clock_refcount: [0; 1],
                timg_wdt_clock_refcount: [0; 1],
                uart_function_clock_refcount: [0; 2],
                uart_mem_clock_refcount: [0; 2],
                uart_baud_rate_generator_refcount: [0; 2],
            });
        static XTAL_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static SYSTEM_PRE_DIV_IN_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static SYSTEM_PRE_DIV_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static CPU_PLL_DIV_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static CPU_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static RC_FAST_CLK_DIV_N_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static RTC_SLOW_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static BLE_LP_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static RTC_FAST_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static LOW_POWER_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static TIMG_CALIBRATION_CLOCK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static I2C_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static SPI_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static TIMG_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static TIMG_WDT_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static UART_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 2];
        static UART_BAUD_RATE_GENERATOR_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 2];
        static APB_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static CRYPTO_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static MSPI_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        /// The clock sources of the device.
        ///
        /// A clock source is a node of the clock tree that other nodes derive their output
        /// from. Ask a node which source it runs on with its `..._root_source` function.
        #[derive(Debug, enumset::EnumSetType)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum ClockSource {
            /// `XTAL_CLK`.
            XtalClk,
            /// `RC_FAST_CLK`.
            RcFastClk,
            /// `OSC_SLOW_CLK`.
            OscSlowClk,
            /// `RC_SLOW_CLK`.
            RcSlowClk,
        }
        /// Returns the clock source that `XTAL_CLK` currently runs on.
        pub fn xtal_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::XtalClk)
        }
        /// Returns the clock source that `PLL_CLK` currently runs on.
        pub fn pll_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `RC_FAST_CLK` currently runs on.
        pub fn rc_fast_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::RcFastClk)
        }
        /// Returns the clock source that `OSC_SLOW_CLK` currently runs on.
        pub fn osc_slow_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::OscSlowClk)
        }
        /// Returns the clock source that `RC_SLOW_CLK` currently runs on.
        pub fn rc_slow_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::RcSlowClk)
        }
        /// Returns the clock source that `RC_FAST_DIV_CLK` currently runs on.
        pub fn rc_fast_div_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            rc_fast_clk_root_source(clocks)
        }
        /// Returns the clock source that `SYSTEM_PRE_DIV_IN` currently runs on.
        pub fn system_pre_div_in_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.system_pre_div_in?;
            match config {
                SystemPreDivInConfig::Xtal => xtal_clk_root_source(clocks),
                SystemPreDivInConfig::RcFast => rc_fast_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `SYSTEM_PRE_DIV` currently runs on.
        pub fn system_pre_div_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            system_pre_div_in_root_source(clocks)
        }
        /// Returns the clock source that `CPU_PLL_DIV` currently runs on.
        pub fn cpu_pll_div_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            pll_clk_root_source(clocks)
        }
        /// Returns the clock source that `CPU_CLK` currently runs on.
        pub fn cpu_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.cpu_clk?;
            match config {
                CpuClkConfig::Xtal => system_pre_div_root_source(clocks),
                CpuClkConfig::RcFast => system_pre_div_root_source(clocks),
                CpuClkConfig::Pll => cpu_pll_div_root_source(clocks),
            }
        }
        /// Returns the clock source that `PLL_40M` currently runs on.
        pub fn pll_40m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            cpu_clk_root_source(clocks)
        }
        /// Returns the clock source that `PLL_60M` currently runs on.
        pub fn pll_60m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            cpu_clk_root_source(clocks)
        }
        /// Returns the clock source that `PLL_80M` currently runs on.
        pub fn pll_80m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            cpu_clk_root_source(clocks)
        }
        /// Returns the clock source that `CPU_DIV2` currently runs on.
        pub fn cpu_div2_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            cpu_clk_root_source(clocks)
        }
        /// Returns the clock source that `RC_FAST_CLK_DIV_N` currently runs on.
        pub fn rc_fast_clk_div_n_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            rc_fast_clk_root_source(clocks)
        }
        /// Returns the clock source that `XTAL_DIV_CLK` currently runs on.
        pub fn xtal_div_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `RTC_SLOW_CLK` currently runs on.
        pub fn rtc_slow_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.rtc_slow_clk?;
            match config {
                RtcSlowClkConfig::OscSlow => osc_slow_clk_root_source(clocks),
                RtcSlowClkConfig::RcSlow => rc_slow_clk_root_source(clocks),
                RtcSlowClkConfig::RcFast => rc_fast_div_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `BLE_LP_XTAL_CLK` currently runs on.
        pub fn ble_lp_xtal_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `BLE_LP_RC_SLOW_CLK` currently runs on.
        pub fn ble_lp_rc_slow_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            rc_slow_clk_root_source(clocks)
        }
        /// Returns the clock source that `BLE_LP_CLK` currently runs on.
        pub fn ble_lp_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.ble_lp_clk?;
            match config.sclk() {
                BleLpClkSclk::Xtal => ble_lp_xtal_clk_root_source(clocks),
                BleLpClkSclk::RcSlow => ble_lp_rc_slow_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `RTC_FAST_CLK` currently runs on.
        pub fn rtc_fast_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.rtc_fast_clk?;
            match config {
                RtcFastClkConfig::Xtal => xtal_div_clk_root_source(clocks),
                RtcFastClkConfig::Rc => rc_fast_clk_div_n_root_source(clocks),
            }
        }
        /// Returns the clock source that `LOW_POWER_CLK` currently runs on.
        pub fn low_power_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.low_power_clk?;
            match config {
                LowPowerClkConfig::Xtal => xtal_clk_root_source(clocks),
                LowPowerClkConfig::RcFast => rc_fast_clk_root_source(clocks),
                LowPowerClkConfig::OscSlow => osc_slow_clk_root_source(clocks),
                LowPowerClkConfig::RtcSlow => rtc_slow_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `UART_MEM_CLK` currently runs on.
        pub fn uart_mem_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `TIMG_CALIBRATION_CLOCK` currently runs on.
        pub fn timg_calibration_clock_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.timg_calibration_clock?;
            match config {
                TimgCalibrationClockConfig::RcSlowClk => rc_slow_clk_root_source(clocks),
                TimgCalibrationClockConfig::RcFastDivClk => rc_fast_div_clk_root_source(clocks),
                TimgCalibrationClockConfig::Osc32kClk => osc_slow_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `APB_CLK` currently runs on.
        pub fn apb_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.apb_clk?;
            match config {
                ApbClkConfig::Pll40m => pll_40m_root_source(clocks),
                ApbClkConfig::Cpu => cpu_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `CRYPTO_CLK` currently runs on.
        pub fn crypto_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.crypto_clk?;
            match config {
                CryptoClkConfig::Pll80m => pll_80m_root_source(clocks),
                CryptoClkConfig::Cpu => cpu_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `MSPI_CLK` currently runs on.
        pub fn mspi_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.mspi_clk?;
            match config {
                MspiClkConfig::CpuDiv2 => cpu_div2_root_source(clocks),
                MspiClkConfig::Cpu => cpu_clk_root_source(clocks),
            }
        }
        pub fn configure_xtal_clk(clocks: &mut ClockTree, config: XtalClkConfig) {
            let old_config = clocks.xtal_clk.replace(config);
            refresh_xtal_clk_downstream(clocks);
            configure_xtal_clk_impl(clocks, old_config, config);
        }
        pub fn xtal_clk_config(clocks: &mut ClockTree) -> Option<XtalClkConfig> {
            clocks.xtal_clk
        }
        fn request_xtal_clk(_clocks: &mut ClockTree) {}
        fn release_xtal_clk(_clocks: &mut ClockTree) {}
        pub fn xtal_clk_config_frequency(config: XtalClkConfig) -> u32 {
            config.value()
        }
        pub fn xtal_clk_frequency() -> u32 {
            XTAL_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn request_pll_clk(clocks: &mut ClockTree) {
            trace!("Enabling PLL_CLK");
            request_xtal_clk(clocks);
            enable_pll_clk_impl(clocks, true);
        }
        pub fn release_pll_clk(clocks: &mut ClockTree) {
            trace!("Disabling PLL_CLK");
            enable_pll_clk_impl(clocks, false);
            release_xtal_clk(clocks);
        }
        pub fn pll_clk_frequency() -> u32 {
            480000000
        }
        pub fn pll_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn request_rc_fast_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC_FAST_CLK");
            if increment_reference_count(&mut clocks.rc_fast_clk_refcount) {
                trace!("Enabling RC_FAST_CLK");
                enable_rc_fast_clk_impl(clocks, true);
            }
        }
        pub fn release_rc_fast_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC_FAST_CLK");
            if decrement_reference_count(&mut clocks.rc_fast_clk_refcount) {
                trace!("Disabling RC_FAST_CLK");
                enable_rc_fast_clk_impl(clocks, false);
            }
        }
        static RC_FAST_CLK_FREQUENCY: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(rc_fast_clk_nominal_frequency());
        pub const fn rc_fast_clk_nominal_frequency() -> u32 {
            17500000
        }
        pub fn rc_fast_clk_frequency() -> u32 {
            RC_FAST_CLK_FREQUENCY.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn set_rc_fast_clk_frequency(clocks: &mut ClockTree, frequency: u32) {
            if !(8750000..=26250000).contains(&frequency) {
                warn!(
                    "Ignoring out-of-range RC_FAST_CLK frequency: {} Hz",
                    frequency
                );
                return;
            }
            debug!(
                "Updating RC_FAST_CLK frequency to {} Hz (nominal {} Hz)",
                frequency,
                rc_fast_clk_nominal_frequency()
            );
            RC_FAST_CLK_FREQUENCY.store(frequency, ::core::sync::atomic::Ordering::Release);
            refresh_rc_fast_clk_downstream(clocks);
        }
        pub fn request_osc_slow_clk(clocks: &mut ClockTree) {
            trace!("Requesting OSC_SLOW_CLK");
            if increment_reference_count(&mut clocks.osc_slow_clk_refcount) {
                trace!("Enabling OSC_SLOW_CLK");
                enable_osc_slow_clk_impl(clocks, true);
            }
        }
        pub fn release_osc_slow_clk(clocks: &mut ClockTree) {
            trace!("Releasing OSC_SLOW_CLK");
            if decrement_reference_count(&mut clocks.osc_slow_clk_refcount) {
                trace!("Disabling OSC_SLOW_CLK");
                enable_osc_slow_clk_impl(clocks, false);
            }
        }
        pub fn osc_slow_clk_frequency() -> u32 {
            32768
        }
        pub fn request_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC_SLOW_CLK");
            if increment_reference_count(&mut clocks.rc_slow_clk_refcount) {
                trace!("Enabling RC_SLOW_CLK");
                enable_rc_slow_clk_impl(clocks, true);
            }
        }
        pub fn release_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC_SLOW_CLK");
            if decrement_reference_count(&mut clocks.rc_slow_clk_refcount) {
                trace!("Disabling RC_SLOW_CLK");
                enable_rc_slow_clk_impl(clocks, false);
            }
        }
        static RC_SLOW_CLK_FREQUENCY: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(rc_slow_clk_nominal_frequency());
        pub const fn rc_slow_clk_nominal_frequency() -> u32 {
            136000
        }
        pub fn rc_slow_clk_frequency() -> u32 {
            RC_SLOW_CLK_FREQUENCY.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn set_rc_slow_clk_frequency(clocks: &mut ClockTree, frequency: u32) {
            if !(68000..=204000).contains(&frequency) {
                warn!(
                    "Ignoring out-of-range RC_SLOW_CLK frequency: {} Hz",
                    frequency
                );
                return;
            }
            debug!(
                "Updating RC_SLOW_CLK frequency to {} Hz (nominal {} Hz)",
                frequency,
                rc_slow_clk_nominal_frequency()
            );
            RC_SLOW_CLK_FREQUENCY.store(frequency, ::core::sync::atomic::Ordering::Release);
            refresh_rc_slow_clk_downstream(clocks);
        }
        pub fn request_rc_fast_div_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC_FAST_DIV_CLK");
            if increment_reference_count(&mut clocks.rc_fast_div_clk_refcount) {
                trace!("Enabling RC_FAST_DIV_CLK");
                request_rc_fast_clk(clocks);
                enable_rc_fast_div_clk_impl(clocks, true);
            }
        }
        pub fn release_rc_fast_div_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC_FAST_DIV_CLK");
            if decrement_reference_count(&mut clocks.rc_fast_div_clk_refcount) {
                trace!("Disabling RC_FAST_DIV_CLK");
                enable_rc_fast_div_clk_impl(clocks, false);
                release_rc_fast_clk(clocks);
            }
        }
        pub fn rc_fast_div_clk_frequency() -> u32 {
            (rc_fast_clk_frequency() / 256)
        }
        pub fn rc_fast_div_clk_source_frequency() -> u32 {
            rc_fast_clk_frequency()
        }
        pub fn configure_system_pre_div_in(
            clocks: &mut ClockTree,
            new_selector: SystemPreDivInConfig,
        ) {
            let old_selector = clocks.system_pre_div_in.replace(new_selector);
            refresh_system_pre_div_in_downstream(clocks);
            match new_selector {
                SystemPreDivInConfig::Xtal => request_xtal_clk(clocks),
                SystemPreDivInConfig::RcFast => request_rc_fast_clk(clocks),
            }
            configure_system_pre_div_in_impl(clocks, old_selector, new_selector);
            if let Some(old_selector) = old_selector {
                match old_selector {
                    SystemPreDivInConfig::Xtal => release_xtal_clk(clocks),
                    SystemPreDivInConfig::RcFast => release_rc_fast_clk(clocks),
                }
            }
        }
        pub fn system_pre_div_in_config(clocks: &mut ClockTree) -> Option<SystemPreDivInConfig> {
            clocks.system_pre_div_in
        }
        pub fn request_system_pre_div_in(clocks: &mut ClockTree) {
            trace!("Enabling SYSTEM_PRE_DIV_IN");
            match unwrap!(clocks.system_pre_div_in) {
                SystemPreDivInConfig::Xtal => request_xtal_clk(clocks),
                SystemPreDivInConfig::RcFast => request_rc_fast_clk(clocks),
            }
            enable_system_pre_div_in_impl(clocks, true);
        }
        pub fn release_system_pre_div_in(clocks: &mut ClockTree) {
            trace!("Disabling SYSTEM_PRE_DIV_IN");
            enable_system_pre_div_in_impl(clocks, false);
            match unwrap!(clocks.system_pre_div_in) {
                SystemPreDivInConfig::Xtal => release_xtal_clk(clocks),
                SystemPreDivInConfig::RcFast => release_rc_fast_clk(clocks),
            }
        }
        pub fn system_pre_div_in_config_frequency(config: SystemPreDivInConfig) -> u32 {
            match config {
                SystemPreDivInConfig::Xtal => xtal_clk_frequency(),
                SystemPreDivInConfig::RcFast => rc_fast_clk_frequency(),
            }
        }
        pub fn system_pre_div_in_frequency() -> u32 {
            SYSTEM_PRE_DIV_IN_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn system_pre_div_in_source_frequency(source: SystemPreDivInConfig) -> u32 {
            system_pre_div_in_config_frequency(source)
        }
        pub fn configure_system_pre_div(clocks: &mut ClockTree, config: SystemPreDivConfig) {
            let old_config = clocks.system_pre_div.replace(config);
            refresh_system_pre_div_downstream(clocks);
            configure_system_pre_div_impl(clocks, old_config, config);
        }
        pub fn system_pre_div_config(clocks: &mut ClockTree) -> Option<SystemPreDivConfig> {
            clocks.system_pre_div
        }
        pub fn request_system_pre_div(clocks: &mut ClockTree) {
            trace!("Enabling SYSTEM_PRE_DIV");
            request_system_pre_div_in(clocks);
            enable_system_pre_div_impl(clocks, true);
        }
        pub fn release_system_pre_div(clocks: &mut ClockTree) {
            trace!("Disabling SYSTEM_PRE_DIV");
            enable_system_pre_div_impl(clocks, false);
            release_system_pre_div_in(clocks);
        }
        pub fn system_pre_div_config_frequency(config: SystemPreDivConfig) -> u32 {
            (system_pre_div_in_frequency() / (config.divisor() + 1))
        }
        pub fn system_pre_div_frequency() -> u32 {
            SYSTEM_PRE_DIV_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn system_pre_div_source_frequency() -> u32 {
            system_pre_div_in_frequency()
        }
        pub fn configure_cpu_pll_div(clocks: &mut ClockTree, config: CpuPllDivConfig) {
            let old_config = clocks.cpu_pll_div.replace(config);
            refresh_cpu_pll_div_downstream(clocks);
            configure_cpu_pll_div_impl(clocks, old_config, config);
        }
        pub fn cpu_pll_div_config(clocks: &mut ClockTree) -> Option<CpuPllDivConfig> {
            clocks.cpu_pll_div
        }
        pub fn request_cpu_pll_div(clocks: &mut ClockTree) {
            trace!("Enabling CPU_PLL_DIV");
            request_pll_clk(clocks);
            enable_cpu_pll_div_impl(clocks, true);
        }
        pub fn release_cpu_pll_div(clocks: &mut ClockTree) {
            trace!("Disabling CPU_PLL_DIV");
            enable_cpu_pll_div_impl(clocks, false);
            release_pll_clk(clocks);
        }
        pub fn cpu_pll_div_config_frequency(config: CpuPllDivConfig) -> u32 {
            (pll_clk_frequency() / config.divisor())
        }
        pub fn cpu_pll_div_frequency() -> u32 {
            CPU_PLL_DIV_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn cpu_pll_div_source_frequency() -> u32 {
            pll_clk_frequency()
        }
        pub fn configure_apb_clk(clocks: &mut ClockTree, new_selector: ApbClkConfig) {
            let old_selector = clocks.apb_clk.replace(new_selector);
            refresh_apb_clk_downstream(clocks);
            match new_selector {
                ApbClkConfig::Pll40m => request_pll_40m(clocks),
                ApbClkConfig::Cpu => request_cpu_clk(clocks),
            }
            configure_apb_clk_impl(clocks, old_selector, new_selector);
            if let Some(old_selector) = old_selector {
                match old_selector {
                    ApbClkConfig::Pll40m => release_pll_40m(clocks),
                    ApbClkConfig::Cpu => release_cpu_clk(clocks),
                }
            }
        }
        pub fn apb_clk_config(clocks: &mut ClockTree) -> Option<ApbClkConfig> {
            clocks.apb_clk
        }
        pub fn request_apb_clk(clocks: &mut ClockTree) {
            trace!("Enabling APB_CLK");
            match unwrap!(clocks.apb_clk) {
                ApbClkConfig::Pll40m => request_pll_40m(clocks),
                ApbClkConfig::Cpu => request_cpu_clk(clocks),
            }
            enable_apb_clk_impl(clocks, true);
        }
        pub fn release_apb_clk(clocks: &mut ClockTree) {
            trace!("Disabling APB_CLK");
            enable_apb_clk_impl(clocks, false);
            match unwrap!(clocks.apb_clk) {
                ApbClkConfig::Pll40m => release_pll_40m(clocks),
                ApbClkConfig::Cpu => release_cpu_clk(clocks),
            }
        }
        pub fn apb_clk_config_frequency(config: ApbClkConfig) -> u32 {
            match config {
                ApbClkConfig::Pll40m => pll_40m_frequency(),
                ApbClkConfig::Cpu => cpu_clk_frequency(),
            }
        }
        pub fn apb_clk_frequency() -> u32 {
            APB_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn apb_clk_source_frequency(source: ApbClkConfig) -> u32 {
            apb_clk_config_frequency(source)
        }
        pub fn configure_crypto_clk(clocks: &mut ClockTree, new_selector: CryptoClkConfig) {
            let old_selector = clocks.crypto_clk.replace(new_selector);
            refresh_crypto_clk_downstream(clocks);
            let active = clocks.crypto_clk_refcount > 0;
            if active {
                match new_selector {
                    CryptoClkConfig::Pll80m => request_pll_80m(clocks),
                    CryptoClkConfig::Cpu => request_cpu_clk(clocks),
                }
            }
            configure_crypto_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    CryptoClkConfig::Pll80m => release_pll_80m(clocks),
                    CryptoClkConfig::Cpu => release_cpu_clk(clocks),
                }
            }
        }
        pub fn crypto_clk_config(clocks: &mut ClockTree) -> Option<CryptoClkConfig> {
            clocks.crypto_clk
        }
        pub fn request_crypto_clk(clocks: &mut ClockTree) {
            trace!("Requesting CRYPTO_CLK");
            if increment_reference_count(&mut clocks.crypto_clk_refcount) {
                trace!("Enabling CRYPTO_CLK");
                match unwrap!(clocks.crypto_clk) {
                    CryptoClkConfig::Pll80m => request_pll_80m(clocks),
                    CryptoClkConfig::Cpu => request_cpu_clk(clocks),
                }
                enable_crypto_clk_impl(clocks, true);
            }
        }
        pub fn release_crypto_clk(clocks: &mut ClockTree) {
            trace!("Releasing CRYPTO_CLK");
            if decrement_reference_count(&mut clocks.crypto_clk_refcount) {
                trace!("Disabling CRYPTO_CLK");
                enable_crypto_clk_impl(clocks, false);
                match unwrap!(clocks.crypto_clk) {
                    CryptoClkConfig::Pll80m => release_pll_80m(clocks),
                    CryptoClkConfig::Cpu => release_cpu_clk(clocks),
                }
            }
        }
        pub fn crypto_clk_config_frequency(config: CryptoClkConfig) -> u32 {
            match config {
                CryptoClkConfig::Pll80m => pll_80m_frequency(),
                CryptoClkConfig::Cpu => cpu_clk_frequency(),
            }
        }
        pub fn crypto_clk_frequency() -> u32 {
            CRYPTO_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn crypto_clk_source_frequency(source: CryptoClkConfig) -> u32 {
            crypto_clk_config_frequency(source)
        }
        pub fn configure_mspi_clk(clocks: &mut ClockTree, new_selector: MspiClkConfig) {
            let old_selector = clocks.mspi_clk.replace(new_selector);
            refresh_mspi_clk_downstream(clocks);
            let active = clocks.mspi_clk_refcount > 0;
            if active {
                match new_selector {
                    MspiClkConfig::CpuDiv2 => request_cpu_div2(clocks),
                    MspiClkConfig::Cpu => request_cpu_clk(clocks),
                }
            }
            configure_mspi_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    MspiClkConfig::CpuDiv2 => release_cpu_div2(clocks),
                    MspiClkConfig::Cpu => release_cpu_clk(clocks),
                }
            }
        }
        pub fn mspi_clk_config(clocks: &mut ClockTree) -> Option<MspiClkConfig> {
            clocks.mspi_clk
        }
        pub fn request_mspi_clk(clocks: &mut ClockTree) {
            trace!("Requesting MSPI_CLK");
            if increment_reference_count(&mut clocks.mspi_clk_refcount) {
                trace!("Enabling MSPI_CLK");
                match unwrap!(clocks.mspi_clk) {
                    MspiClkConfig::CpuDiv2 => request_cpu_div2(clocks),
                    MspiClkConfig::Cpu => request_cpu_clk(clocks),
                }
                enable_mspi_clk_impl(clocks, true);
            }
        }
        pub fn release_mspi_clk(clocks: &mut ClockTree) {
            trace!("Releasing MSPI_CLK");
            if decrement_reference_count(&mut clocks.mspi_clk_refcount) {
                trace!("Disabling MSPI_CLK");
                enable_mspi_clk_impl(clocks, false);
                match unwrap!(clocks.mspi_clk) {
                    MspiClkConfig::CpuDiv2 => release_cpu_div2(clocks),
                    MspiClkConfig::Cpu => release_cpu_clk(clocks),
                }
            }
        }
        pub fn mspi_clk_config_frequency(config: MspiClkConfig) -> u32 {
            match config {
                MspiClkConfig::CpuDiv2 => cpu_div2_frequency(),
                MspiClkConfig::Cpu => cpu_clk_frequency(),
            }
        }
        pub fn mspi_clk_frequency() -> u32 {
            MSPI_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn mspi_clk_source_frequency(source: MspiClkConfig) -> u32 {
            mspi_clk_config_frequency(source)
        }
        pub fn configure_cpu_clk(clocks: &mut ClockTree, new_selector: CpuClkConfig) {
            let old_selector = clocks.cpu_clk.replace(new_selector);
            refresh_cpu_clk_downstream(clocks);
            match new_selector {
                CpuClkConfig::Xtal => {
                    configure_apb_clk(clocks, ApbClkConfig::Cpu);
                    configure_crypto_clk(clocks, CryptoClkConfig::Cpu);
                    configure_mspi_clk(clocks, MspiClkConfig::Cpu);
                    configure_system_pre_div_in(clocks, SystemPreDivInConfig::Xtal);
                }
                CpuClkConfig::RcFast => {
                    configure_apb_clk(clocks, ApbClkConfig::Cpu);
                    configure_crypto_clk(clocks, CryptoClkConfig::Cpu);
                    configure_mspi_clk(clocks, MspiClkConfig::Cpu);
                    configure_system_pre_div_in(clocks, SystemPreDivInConfig::RcFast);
                }
                CpuClkConfig::Pll => {
                    configure_apb_clk(clocks, ApbClkConfig::Pll40m);
                    configure_crypto_clk(clocks, CryptoClkConfig::Pll80m);
                    configure_mspi_clk(clocks, MspiClkConfig::CpuDiv2);
                }
            }
            match new_selector {
                CpuClkConfig::Xtal => request_system_pre_div(clocks),
                CpuClkConfig::RcFast => request_system_pre_div(clocks),
                CpuClkConfig::Pll => request_cpu_pll_div(clocks),
            }
            configure_cpu_clk_impl(clocks, old_selector, new_selector);
            if let Some(old_selector) = old_selector {
                match old_selector {
                    CpuClkConfig::Xtal => release_system_pre_div(clocks),
                    CpuClkConfig::RcFast => release_system_pre_div(clocks),
                    CpuClkConfig::Pll => release_cpu_pll_div(clocks),
                }
            }
        }
        pub fn cpu_clk_config(clocks: &mut ClockTree) -> Option<CpuClkConfig> {
            clocks.cpu_clk
        }
        fn request_cpu_clk(_clocks: &mut ClockTree) {}
        fn release_cpu_clk(_clocks: &mut ClockTree) {}
        pub fn cpu_clk_config_frequency(config: CpuClkConfig) -> u32 {
            match config {
                CpuClkConfig::Xtal => system_pre_div_frequency(),
                CpuClkConfig::RcFast => system_pre_div_frequency(),
                CpuClkConfig::Pll => cpu_pll_div_frequency(),
            }
        }
        pub fn cpu_clk_frequency() -> u32 {
            CPU_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn request_pll_40m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_40M");
            if increment_reference_count(&mut clocks.pll_40m_refcount) {
                trace!("Enabling PLL_40M");
                request_cpu_clk(clocks);
                enable_pll_40m_impl(clocks, true);
            }
        }
        pub fn release_pll_40m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_40M");
            if decrement_reference_count(&mut clocks.pll_40m_refcount) {
                trace!("Disabling PLL_40M");
                enable_pll_40m_impl(clocks, false);
                release_cpu_clk(clocks);
            }
        }
        pub fn pll_40m_frequency() -> u32 {
            40000000
        }
        pub fn pll_40m_source_frequency() -> u32 {
            cpu_clk_frequency()
        }
        pub fn request_pll_60m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_60M");
            if increment_reference_count(&mut clocks.pll_60m_refcount) {
                trace!("Enabling PLL_60M");
                request_cpu_clk(clocks);
                enable_pll_60m_impl(clocks, true);
            }
        }
        pub fn release_pll_60m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_60M");
            if decrement_reference_count(&mut clocks.pll_60m_refcount) {
                trace!("Disabling PLL_60M");
                enable_pll_60m_impl(clocks, false);
                release_cpu_clk(clocks);
            }
        }
        pub fn pll_60m_frequency() -> u32 {
            60000000
        }
        pub fn pll_60m_source_frequency() -> u32 {
            cpu_clk_frequency()
        }
        pub fn request_pll_80m(clocks: &mut ClockTree) {
            trace!("Enabling PLL_80M");
            request_cpu_clk(clocks);
            enable_pll_80m_impl(clocks, true);
        }
        pub fn release_pll_80m(clocks: &mut ClockTree) {
            trace!("Disabling PLL_80M");
            enable_pll_80m_impl(clocks, false);
            release_cpu_clk(clocks);
        }
        pub fn pll_80m_frequency() -> u32 {
            80000000
        }
        pub fn pll_80m_source_frequency() -> u32 {
            cpu_clk_frequency()
        }
        pub fn request_cpu_div2(clocks: &mut ClockTree) {
            trace!("Enabling CPU_DIV2");
            request_cpu_clk(clocks);
            enable_cpu_div2_impl(clocks, true);
        }
        pub fn release_cpu_div2(clocks: &mut ClockTree) {
            trace!("Disabling CPU_DIV2");
            enable_cpu_div2_impl(clocks, false);
            release_cpu_clk(clocks);
        }
        pub fn cpu_div2_frequency() -> u32 {
            (cpu_clk_frequency() / 2)
        }
        pub fn cpu_div2_source_frequency() -> u32 {
            cpu_clk_frequency()
        }
        pub fn configure_rc_fast_clk_div_n(clocks: &mut ClockTree, config: RcFastClkDivNConfig) {
            let old_config = clocks.rc_fast_clk_div_n.replace(config);
            refresh_rc_fast_clk_div_n_downstream(clocks);
            configure_rc_fast_clk_div_n_impl(clocks, old_config, config);
        }
        pub fn rc_fast_clk_div_n_config(clocks: &mut ClockTree) -> Option<RcFastClkDivNConfig> {
            clocks.rc_fast_clk_div_n
        }
        pub fn request_rc_fast_clk_div_n(clocks: &mut ClockTree) {
            trace!("Enabling RC_FAST_CLK_DIV_N");
            request_rc_fast_clk(clocks);
            enable_rc_fast_clk_div_n_impl(clocks, true);
        }
        pub fn release_rc_fast_clk_div_n(clocks: &mut ClockTree) {
            trace!("Disabling RC_FAST_CLK_DIV_N");
            enable_rc_fast_clk_div_n_impl(clocks, false);
            release_rc_fast_clk(clocks);
        }
        pub fn rc_fast_clk_div_n_config_frequency(config: RcFastClkDivNConfig) -> u32 {
            (rc_fast_clk_frequency() / (config.divisor() + 1))
        }
        pub fn rc_fast_clk_div_n_frequency() -> u32 {
            RC_FAST_CLK_DIV_N_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn rc_fast_clk_div_n_source_frequency() -> u32 {
            rc_fast_clk_frequency()
        }
        pub fn request_xtal_div_clk(clocks: &mut ClockTree) {
            trace!("Enabling XTAL_DIV_CLK");
            request_xtal_clk(clocks);
            enable_xtal_div_clk_impl(clocks, true);
        }
        pub fn release_xtal_div_clk(clocks: &mut ClockTree) {
            trace!("Disabling XTAL_DIV_CLK");
            enable_xtal_div_clk_impl(clocks, false);
            release_xtal_clk(clocks);
        }
        pub fn xtal_div_clk_frequency() -> u32 {
            (xtal_clk_frequency() / 2)
        }
        pub fn xtal_div_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn configure_rtc_slow_clk(clocks: &mut ClockTree, new_selector: RtcSlowClkConfig) {
            let old_selector = clocks.rtc_slow_clk.replace(new_selector);
            refresh_rtc_slow_clk_downstream(clocks);
            match new_selector {
                RtcSlowClkConfig::OscSlow => request_osc_slow_clk(clocks),
                RtcSlowClkConfig::RcSlow => request_rc_slow_clk(clocks),
                RtcSlowClkConfig::RcFast => request_rc_fast_div_clk(clocks),
            }
            configure_rtc_slow_clk_impl(clocks, old_selector, new_selector);
            if let Some(old_selector) = old_selector {
                match old_selector {
                    RtcSlowClkConfig::OscSlow => release_osc_slow_clk(clocks),
                    RtcSlowClkConfig::RcSlow => release_rc_slow_clk(clocks),
                    RtcSlowClkConfig::RcFast => release_rc_fast_div_clk(clocks),
                }
            }
        }
        pub fn rtc_slow_clk_config(clocks: &mut ClockTree) -> Option<RtcSlowClkConfig> {
            clocks.rtc_slow_clk
        }
        pub fn request_rtc_slow_clk(clocks: &mut ClockTree) {
            trace!("Enabling RTC_SLOW_CLK");
            match unwrap!(clocks.rtc_slow_clk) {
                RtcSlowClkConfig::OscSlow => request_osc_slow_clk(clocks),
                RtcSlowClkConfig::RcSlow => request_rc_slow_clk(clocks),
                RtcSlowClkConfig::RcFast => request_rc_fast_div_clk(clocks),
            }
            enable_rtc_slow_clk_impl(clocks, true);
        }
        pub fn release_rtc_slow_clk(clocks: &mut ClockTree) {
            trace!("Disabling RTC_SLOW_CLK");
            enable_rtc_slow_clk_impl(clocks, false);
            match unwrap!(clocks.rtc_slow_clk) {
                RtcSlowClkConfig::OscSlow => release_osc_slow_clk(clocks),
                RtcSlowClkConfig::RcSlow => release_rc_slow_clk(clocks),
                RtcSlowClkConfig::RcFast => release_rc_fast_div_clk(clocks),
            }
        }
        pub fn rtc_slow_clk_config_frequency(config: RtcSlowClkConfig) -> u32 {
            match config {
                RtcSlowClkConfig::OscSlow => osc_slow_clk_frequency(),
                RtcSlowClkConfig::RcSlow => rc_slow_clk_frequency(),
                RtcSlowClkConfig::RcFast => rc_fast_div_clk_frequency(),
            }
        }
        pub fn rtc_slow_clk_frequency() -> u32 {
            RTC_SLOW_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn rtc_slow_clk_source_frequency(source: RtcSlowClkConfig) -> u32 {
            rtc_slow_clk_config_frequency(source)
        }
        pub fn request_ble_lp_xtal_clk(clocks: &mut ClockTree) {
            trace!("Enabling BLE_LP_XTAL_CLK");
            request_xtal_clk(clocks);
            enable_ble_lp_xtal_clk_impl(clocks, true);
        }
        pub fn release_ble_lp_xtal_clk(clocks: &mut ClockTree) {
            trace!("Disabling BLE_LP_XTAL_CLK");
            enable_ble_lp_xtal_clk_impl(clocks, false);
            release_xtal_clk(clocks);
        }
        pub fn ble_lp_xtal_clk_frequency() -> u32 {
            (xtal_clk_frequency() / 5)
        }
        pub fn ble_lp_xtal_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn request_ble_lp_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Enabling BLE_LP_RC_SLOW_CLK");
            request_rc_slow_clk(clocks);
            enable_ble_lp_rc_slow_clk_impl(clocks, true);
        }
        pub fn release_ble_lp_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Disabling BLE_LP_RC_SLOW_CLK");
            enable_ble_lp_rc_slow_clk_impl(clocks, false);
            release_rc_slow_clk(clocks);
        }
        pub fn ble_lp_rc_slow_clk_frequency() -> u32 {
            (rc_slow_clk_frequency() / 5)
        }
        pub fn ble_lp_rc_slow_clk_source_frequency() -> u32 {
            rc_slow_clk_frequency()
        }
        pub fn configure_ble_lp_clk(clocks: &mut ClockTree, config: BleLpClkConfig) {
            let old_config = clocks.ble_lp_clk.replace(config);
            refresh_ble_lp_clk_downstream(clocks);
            let active = clocks.ble_lp_clk_refcount > 0;
            if active {
                match config.sclk {
                    BleLpClkSclk::Xtal => request_ble_lp_xtal_clk(clocks),
                    BleLpClkSclk::RcSlow => request_ble_lp_rc_slow_clk(clocks),
                }
            }
            configure_ble_lp_clk_impl(clocks, old_config, config);
            if active && let Some(old_config) = old_config {
                match old_config.sclk {
                    BleLpClkSclk::Xtal => release_ble_lp_xtal_clk(clocks),
                    BleLpClkSclk::RcSlow => release_ble_lp_rc_slow_clk(clocks),
                }
            }
        }
        pub fn ble_lp_clk_config(clocks: &mut ClockTree) -> Option<BleLpClkConfig> {
            clocks.ble_lp_clk
        }
        pub fn request_ble_lp_clk(clocks: &mut ClockTree) {
            trace!("Requesting BLE_LP_CLK");
            if increment_reference_count(&mut clocks.ble_lp_clk_refcount) {
                trace!("Enabling BLE_LP_CLK");
                match unwrap!(clocks.ble_lp_clk).sclk {
                    BleLpClkSclk::Xtal => request_ble_lp_xtal_clk(clocks),
                    BleLpClkSclk::RcSlow => request_ble_lp_rc_slow_clk(clocks),
                }
                enable_ble_lp_clk_impl(clocks, true);
            }
        }
        pub fn release_ble_lp_clk(clocks: &mut ClockTree) {
            trace!("Releasing BLE_LP_CLK");
            if decrement_reference_count(&mut clocks.ble_lp_clk_refcount) {
                trace!("Disabling BLE_LP_CLK");
                enable_ble_lp_clk_impl(clocks, false);
                match unwrap!(clocks.ble_lp_clk).sclk {
                    BleLpClkSclk::Xtal => release_ble_lp_xtal_clk(clocks),
                    BleLpClkSclk::RcSlow => release_ble_lp_rc_slow_clk(clocks),
                }
            }
        }
        pub fn ble_lp_clk_config_frequency(config: BleLpClkConfig) -> u32 {
            (match config.sclk {
                BleLpClkSclk::Xtal => ble_lp_xtal_clk_frequency(),
                BleLpClkSclk::RcSlow => ble_lp_rc_slow_clk_frequency(),
            } / (config.divisor() + 1))
        }
        pub fn ble_lp_clk_frequency() -> u32 {
            BLE_LP_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn ble_lp_clk_source_frequency(sclk: BleLpClkSclk) -> u32 {
            match sclk {
                BleLpClkSclk::Xtal => ble_lp_xtal_clk_frequency(),
                BleLpClkSclk::RcSlow => ble_lp_rc_slow_clk_frequency(),
            }
        }
        pub fn configure_rtc_fast_clk(clocks: &mut ClockTree, new_selector: RtcFastClkConfig) {
            let old_selector = clocks.rtc_fast_clk.replace(new_selector);
            refresh_rtc_fast_clk_downstream(clocks);
            let active = clocks.rtc_fast_clk_refcount > 0;
            if active {
                match new_selector {
                    RtcFastClkConfig::Xtal => request_xtal_div_clk(clocks),
                    RtcFastClkConfig::Rc => request_rc_fast_clk_div_n(clocks),
                }
            }
            configure_rtc_fast_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    RtcFastClkConfig::Xtal => release_xtal_div_clk(clocks),
                    RtcFastClkConfig::Rc => release_rc_fast_clk_div_n(clocks),
                }
            }
        }
        pub fn rtc_fast_clk_config(clocks: &mut ClockTree) -> Option<RtcFastClkConfig> {
            clocks.rtc_fast_clk
        }
        pub fn request_rtc_fast_clk(clocks: &mut ClockTree) {
            trace!("Requesting RTC_FAST_CLK");
            if increment_reference_count(&mut clocks.rtc_fast_clk_refcount) {
                trace!("Enabling RTC_FAST_CLK");
                match unwrap!(clocks.rtc_fast_clk) {
                    RtcFastClkConfig::Xtal => request_xtal_div_clk(clocks),
                    RtcFastClkConfig::Rc => request_rc_fast_clk_div_n(clocks),
                }
                enable_rtc_fast_clk_impl(clocks, true);
            }
        }
        pub fn release_rtc_fast_clk(clocks: &mut ClockTree) {
            trace!("Releasing RTC_FAST_CLK");
            if decrement_reference_count(&mut clocks.rtc_fast_clk_refcount) {
                trace!("Disabling RTC_FAST_CLK");
                enable_rtc_fast_clk_impl(clocks, false);
                match unwrap!(clocks.rtc_fast_clk) {
                    RtcFastClkConfig::Xtal => release_xtal_div_clk(clocks),
                    RtcFastClkConfig::Rc => release_rc_fast_clk_div_n(clocks),
                }
            }
        }
        pub fn rtc_fast_clk_config_frequency(config: RtcFastClkConfig) -> u32 {
            match config {
                RtcFastClkConfig::Xtal => xtal_div_clk_frequency(),
                RtcFastClkConfig::Rc => rc_fast_clk_div_n_frequency(),
            }
        }
        pub fn rtc_fast_clk_frequency() -> u32 {
            RTC_FAST_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn rtc_fast_clk_source_frequency(source: RtcFastClkConfig) -> u32 {
            rtc_fast_clk_config_frequency(source)
        }
        pub fn configure_low_power_clk(clocks: &mut ClockTree, new_selector: LowPowerClkConfig) {
            let old_selector = clocks.low_power_clk.replace(new_selector);
            refresh_low_power_clk_downstream(clocks);
            let active = clocks.low_power_clk_refcount > 0;
            if active {
                match new_selector {
                    LowPowerClkConfig::Xtal => request_xtal_clk(clocks),
                    LowPowerClkConfig::RcFast => request_rc_fast_clk(clocks),
                    LowPowerClkConfig::OscSlow => request_osc_slow_clk(clocks),
                    LowPowerClkConfig::RtcSlow => request_rtc_slow_clk(clocks),
                }
            }
            configure_low_power_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    LowPowerClkConfig::Xtal => release_xtal_clk(clocks),
                    LowPowerClkConfig::RcFast => release_rc_fast_clk(clocks),
                    LowPowerClkConfig::OscSlow => release_osc_slow_clk(clocks),
                    LowPowerClkConfig::RtcSlow => release_rtc_slow_clk(clocks),
                }
            }
        }
        pub fn low_power_clk_config(clocks: &mut ClockTree) -> Option<LowPowerClkConfig> {
            clocks.low_power_clk
        }
        pub fn request_low_power_clk(clocks: &mut ClockTree) {
            trace!("Requesting LOW_POWER_CLK");
            if increment_reference_count(&mut clocks.low_power_clk_refcount) {
                trace!("Enabling LOW_POWER_CLK");
                match unwrap!(clocks.low_power_clk) {
                    LowPowerClkConfig::Xtal => request_xtal_clk(clocks),
                    LowPowerClkConfig::RcFast => request_rc_fast_clk(clocks),
                    LowPowerClkConfig::OscSlow => request_osc_slow_clk(clocks),
                    LowPowerClkConfig::RtcSlow => request_rtc_slow_clk(clocks),
                }
                enable_low_power_clk_impl(clocks, true);
            }
        }
        pub fn release_low_power_clk(clocks: &mut ClockTree) {
            trace!("Releasing LOW_POWER_CLK");
            if decrement_reference_count(&mut clocks.low_power_clk_refcount) {
                trace!("Disabling LOW_POWER_CLK");
                enable_low_power_clk_impl(clocks, false);
                match unwrap!(clocks.low_power_clk) {
                    LowPowerClkConfig::Xtal => release_xtal_clk(clocks),
                    LowPowerClkConfig::RcFast => release_rc_fast_clk(clocks),
                    LowPowerClkConfig::OscSlow => release_osc_slow_clk(clocks),
                    LowPowerClkConfig::RtcSlow => release_rtc_slow_clk(clocks),
                }
            }
        }
        pub fn low_power_clk_config_frequency(config: LowPowerClkConfig) -> u32 {
            match config {
                LowPowerClkConfig::Xtal => xtal_clk_frequency(),
                LowPowerClkConfig::RcFast => rc_fast_clk_frequency(),
                LowPowerClkConfig::OscSlow => osc_slow_clk_frequency(),
                LowPowerClkConfig::RtcSlow => rtc_slow_clk_frequency(),
            }
        }
        pub fn low_power_clk_frequency() -> u32 {
            LOW_POWER_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn low_power_clk_source_frequency(source: LowPowerClkConfig) -> u32 {
            low_power_clk_config_frequency(source)
        }
        pub fn request_uart_mem_clk(clocks: &mut ClockTree) {
            trace!("Requesting UART_MEM_CLK");
            if increment_reference_count(&mut clocks.uart_mem_clk_refcount) {
                trace!("Enabling UART_MEM_CLK");
                request_xtal_clk(clocks);
                enable_uart_mem_clk_impl(clocks, true);
            }
        }
        pub fn release_uart_mem_clk(clocks: &mut ClockTree) {
            trace!("Releasing UART_MEM_CLK");
            if decrement_reference_count(&mut clocks.uart_mem_clk_refcount) {
                trace!("Disabling UART_MEM_CLK");
                enable_uart_mem_clk_impl(clocks, false);
                release_xtal_clk(clocks);
            }
        }
        pub fn uart_mem_clk_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn uart_mem_clk_source_frequency(source: UartMemClkConfig) -> u32 {
            match source {
                UartMemClkConfig::Xtal => xtal_clk_frequency(),
            }
        }
        pub fn configure_timg_calibration_clock(
            clocks: &mut ClockTree,
            new_selector: TimgCalibrationClockConfig,
        ) {
            let old_selector = clocks.timg_calibration_clock.replace(new_selector);
            refresh_timg_calibration_clock_downstream(clocks);
            let active = clocks.timg_calibration_clock_refcount > 0;
            if active {
                match new_selector {
                    TimgCalibrationClockConfig::RcSlowClk => request_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => request_rc_fast_div_clk(clocks),
                    TimgCalibrationClockConfig::Osc32kClk => request_osc_slow_clk(clocks),
                }
            }
            configure_timg_calibration_clock_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    TimgCalibrationClockConfig::RcSlowClk => release_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => release_rc_fast_div_clk(clocks),
                    TimgCalibrationClockConfig::Osc32kClk => release_osc_slow_clk(clocks),
                }
            }
        }
        pub fn timg_calibration_clock_config(
            clocks: &mut ClockTree,
        ) -> Option<TimgCalibrationClockConfig> {
            clocks.timg_calibration_clock
        }
        pub fn request_timg_calibration_clock(clocks: &mut ClockTree) {
            trace!("Requesting TIMG_CALIBRATION_CLOCK");
            if increment_reference_count(&mut clocks.timg_calibration_clock_refcount) {
                trace!("Enabling TIMG_CALIBRATION_CLOCK");
                crate::rtc_cntl::WakeLock::acquire();
                match unwrap!(clocks.timg_calibration_clock) {
                    TimgCalibrationClockConfig::RcSlowClk => request_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => request_rc_fast_div_clk(clocks),
                    TimgCalibrationClockConfig::Osc32kClk => request_osc_slow_clk(clocks),
                }
                enable_timg_calibration_clock_impl(clocks, true);
            }
        }
        pub fn release_timg_calibration_clock(clocks: &mut ClockTree) {
            trace!("Releasing TIMG_CALIBRATION_CLOCK");
            if decrement_reference_count(&mut clocks.timg_calibration_clock_refcount) {
                trace!("Disabling TIMG_CALIBRATION_CLOCK");
                crate::rtc_cntl::WakeLock::release();
                enable_timg_calibration_clock_impl(clocks, false);
                match unwrap!(clocks.timg_calibration_clock) {
                    TimgCalibrationClockConfig::RcSlowClk => release_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => release_rc_fast_div_clk(clocks),
                    TimgCalibrationClockConfig::Osc32kClk => release_osc_slow_clk(clocks),
                }
            }
        }
        pub fn timg_calibration_clock_config_frequency(config: TimgCalibrationClockConfig) -> u32 {
            match config {
                TimgCalibrationClockConfig::RcSlowClk => rc_slow_clk_frequency(),
                TimgCalibrationClockConfig::RcFastDivClk => rc_fast_div_clk_frequency(),
                TimgCalibrationClockConfig::Osc32kClk => osc_slow_clk_frequency(),
            }
        }
        pub fn timg_calibration_clock_frequency() -> u32 {
            TIMG_CALIBRATION_CLOCK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn timg_calibration_clock_source_frequency(source: TimgCalibrationClockConfig) -> u32 {
            timg_calibration_clock_config_frequency(source)
        }
        impl AdcInstance {
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(&mut clocks.adc_function_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    request_apb_clk(clocks);
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(&mut clocks.adc_function_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    release_apb_clk(clocks);
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                apb_clk_frequency()
            }
            pub fn function_clock_source_frequency() -> u32 {
                apb_clk_frequency()
            }
        }
        impl I2cInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                config: I2cFunctionClockConfig,
            ) {
                let old_config = clocks.i2c_function_clock[self as usize].replace(config);
                refresh_i2c_function_clock_downstream(clocks, self);
                let active = clocks.i2c_function_clock_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        I2cFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        I2cFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<I2cFunctionClockConfig> {
                clocks.i2c_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(&mut clocks.i2c_function_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.i2c_function_clock[self as usize]).sclk {
                        I2cFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(&mut clocks.i2c_function_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.i2c_function_clock[self as usize]).sclk {
                        I2cFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: I2cFunctionClockConfig) -> u32 {
                (match config.sclk {
                    I2cFunctionClockSclk::Xtal => xtal_clk_frequency(),
                    I2cFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                } / (config.div_num() + 1))
            }
            pub fn function_clock_frequency(self) -> u32 {
                I2C_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(sclk: I2cFunctionClockSclk) -> u32 {
                match sclk {
                    I2cFunctionClockSclk::Xtal => xtal_clk_frequency(),
                    I2cFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                }
            }
        }
        impl SpiInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                new_selector: SpiFunctionClockConfig,
            ) {
                let old_selector = clocks.spi_function_clock[self as usize].replace(new_selector);
                refresh_spi_function_clock_downstream(clocks, self);
                let active = clocks.spi_function_clock_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        SpiFunctionClockConfig::Xtal => request_xtal_clk(clocks),
                        SpiFunctionClockConfig::Pll40m => request_pll_40m(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        SpiFunctionClockConfig::Xtal => release_xtal_clk(clocks),
                        SpiFunctionClockConfig::Pll40m => release_pll_40m(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<SpiFunctionClockConfig> {
                clocks.spi_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(&mut clocks.spi_function_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.spi_function_clock[self as usize]) {
                        SpiFunctionClockConfig::Xtal => request_xtal_clk(clocks),
                        SpiFunctionClockConfig::Pll40m => request_pll_40m(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(&mut clocks.spi_function_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.spi_function_clock[self as usize]) {
                        SpiFunctionClockConfig::Xtal => release_xtal_clk(clocks),
                        SpiFunctionClockConfig::Pll40m => release_pll_40m(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: SpiFunctionClockConfig) -> u32 {
                match config {
                    SpiFunctionClockConfig::Xtal => xtal_clk_frequency(),
                    SpiFunctionClockConfig::Pll40m => pll_40m_frequency(),
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                SPI_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(source: SpiFunctionClockConfig) -> u32 {
                Self::function_clock_config_frequency(source)
            }
        }
        impl TimgInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                new_selector: TimgFunctionClockConfig,
            ) {
                let old_selector = clocks.timg_function_clock[self as usize].replace(new_selector);
                refresh_timg_function_clock_downstream(clocks, self);
                let active = clocks.timg_function_clock_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        TimgFunctionClockConfig::XtalClk => request_xtal_clk(clocks),
                        TimgFunctionClockConfig::Pll40m => request_pll_40m(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        TimgFunctionClockConfig::XtalClk => release_xtal_clk(clocks),
                        TimgFunctionClockConfig::Pll40m => release_pll_40m(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<TimgFunctionClockConfig> {
                clocks.timg_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(
                    &mut clocks.timg_function_clock_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.timg_function_clock[self as usize]) {
                        TimgFunctionClockConfig::XtalClk => request_xtal_clk(clocks),
                        TimgFunctionClockConfig::Pll40m => request_pll_40m(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(
                    &mut clocks.timg_function_clock_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.timg_function_clock[self as usize]) {
                        TimgFunctionClockConfig::XtalClk => release_xtal_clk(clocks),
                        TimgFunctionClockConfig::Pll40m => release_pll_40m(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: TimgFunctionClockConfig) -> u32 {
                match config {
                    TimgFunctionClockConfig::XtalClk => xtal_clk_frequency(),
                    TimgFunctionClockConfig::Pll40m => pll_40m_frequency(),
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                TIMG_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(source: TimgFunctionClockConfig) -> u32 {
                Self::function_clock_config_frequency(source)
            }
            pub fn configure_wdt_clock(
                self,
                clocks: &mut ClockTree,
                new_selector: TimgWdtClockConfig,
            ) {
                let old_selector = clocks.timg_wdt_clock[self as usize].replace(new_selector);
                refresh_timg_wdt_clock_downstream(clocks, self);
                let active = clocks.timg_wdt_clock_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        TimgWdtClockConfig::Pll40m => request_pll_40m(clocks),
                        TimgWdtClockConfig::XtalClk => request_xtal_clk(clocks),
                    }
                }
                self.configure_wdt_clock_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        TimgWdtClockConfig::Pll40m => release_pll_40m(clocks),
                        TimgWdtClockConfig::XtalClk => release_xtal_clk(clocks),
                    }
                }
            }
            pub fn wdt_clock_config(self, clocks: &mut ClockTree) -> Option<TimgWdtClockConfig> {
                clocks.timg_wdt_clock[self as usize]
            }
            pub fn request_wdt_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::WDT_CLOCK", self);
                if increment_reference_count(&mut clocks.timg_wdt_clock_refcount[self as usize]) {
                    trace!("Enabling {:?}::WDT_CLOCK", self);
                    match unwrap!(clocks.timg_wdt_clock[self as usize]) {
                        TimgWdtClockConfig::Pll40m => request_pll_40m(clocks),
                        TimgWdtClockConfig::XtalClk => request_xtal_clk(clocks),
                    }
                    self.enable_wdt_clock_impl(clocks, true);
                }
            }
            pub fn release_wdt_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::WDT_CLOCK", self);
                if decrement_reference_count(&mut clocks.timg_wdt_clock_refcount[self as usize]) {
                    trace!("Disabling {:?}::WDT_CLOCK", self);
                    self.enable_wdt_clock_impl(clocks, false);
                    match unwrap!(clocks.timg_wdt_clock[self as usize]) {
                        TimgWdtClockConfig::Pll40m => release_pll_40m(clocks),
                        TimgWdtClockConfig::XtalClk => release_xtal_clk(clocks),
                    }
                }
            }
            pub fn wdt_clock_config_frequency(config: TimgWdtClockConfig) -> u32 {
                match config {
                    TimgWdtClockConfig::Pll40m => pll_40m_frequency(),
                    TimgWdtClockConfig::XtalClk => xtal_clk_frequency(),
                }
            }
            pub fn wdt_clock_frequency(self) -> u32 {
                TIMG_WDT_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn wdt_clock_source_frequency(source: TimgWdtClockConfig) -> u32 {
                Self::wdt_clock_config_frequency(source)
            }
        }
        impl UartInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                config: UartFunctionClockConfig,
            ) {
                let old_config = clocks.uart_function_clock[self as usize].replace(config);
                refresh_uart_function_clock_downstream(clocks, self);
                let active = clocks.uart_function_clock_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        UartFunctionClockSclk::PllF40m => request_pll_40m(clocks),
                        UartFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                        UartFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        UartFunctionClockSclk::PllF40m => release_pll_40m(clocks),
                        UartFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                        UartFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<UartFunctionClockConfig> {
                clocks.uart_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(
                    &mut clocks.uart_function_clock_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.uart_function_clock[self as usize]).sclk {
                        UartFunctionClockSclk::PllF40m => request_pll_40m(clocks),
                        UartFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                        UartFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(
                    &mut clocks.uart_function_clock_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.uart_function_clock[self as usize]).sclk {
                        UartFunctionClockSclk::PllF40m => release_pll_40m(clocks),
                        UartFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                        UartFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: UartFunctionClockConfig) -> u32 {
                (match config.sclk {
                    UartFunctionClockSclk::PllF40m => pll_40m_frequency(),
                    UartFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                    UartFunctionClockSclk::Xtal => xtal_clk_frequency(),
                } / (config.div_num() + 1))
            }
            pub fn function_clock_frequency(self) -> u32 {
                UART_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(sclk: UartFunctionClockSclk) -> u32 {
                match sclk {
                    UartFunctionClockSclk::PllF40m => pll_40m_frequency(),
                    UartFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                    UartFunctionClockSclk::Xtal => xtal_clk_frequency(),
                }
            }
            pub fn request_mem_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::MEM_CLOCK", self);
                if increment_reference_count(&mut clocks.uart_mem_clock_refcount[self as usize]) {
                    trace!("Enabling {:?}::MEM_CLOCK", self);
                    request_uart_mem_clk(clocks);
                    self.enable_mem_clock_impl(clocks, true);
                }
            }
            pub fn release_mem_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::MEM_CLOCK", self);
                if decrement_reference_count(&mut clocks.uart_mem_clock_refcount[self as usize]) {
                    trace!("Disabling {:?}::MEM_CLOCK", self);
                    self.enable_mem_clock_impl(clocks, false);
                    release_uart_mem_clk(clocks);
                }
            }
            pub fn mem_clock_frequency(self) -> u32 {
                uart_mem_clk_frequency()
            }
            pub fn mem_clock_source_frequency() -> u32 {
                uart_mem_clk_frequency()
            }
            pub fn configure_baud_rate_generator(
                self,
                clocks: &mut ClockTree,
                config: UartBaudRateGeneratorConfig,
            ) {
                let old_config = clocks.uart_baud_rate_generator[self as usize].replace(config);
                refresh_uart_baud_rate_generator_downstream(clocks, self);
                self.configure_baud_rate_generator_impl(clocks, old_config, config);
            }
            pub fn baud_rate_generator_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<UartBaudRateGeneratorConfig> {
                clocks.uart_baud_rate_generator[self as usize]
            }
            pub fn request_baud_rate_generator(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::BAUD_RATE_GENERATOR", self);
                if increment_reference_count(
                    &mut clocks.uart_baud_rate_generator_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::BAUD_RATE_GENERATOR", self);
                    self.request_function_clock(clocks);
                    self.enable_baud_rate_generator_impl(clocks, true);
                }
            }
            pub fn release_baud_rate_generator(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::BAUD_RATE_GENERATOR", self);
                if decrement_reference_count(
                    &mut clocks.uart_baud_rate_generator_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::BAUD_RATE_GENERATOR", self);
                    self.enable_baud_rate_generator_impl(clocks, false);
                    self.release_function_clock(clocks);
                }
            }
            pub fn baud_rate_generator_config_frequency(
                self,
                config: UartBaudRateGeneratorConfig,
            ) -> u32 {
                ((self.function_clock_frequency() * 16)
                    / ((config.integral() * 16) + config.fractional()))
            }
            pub fn baud_rate_generator_frequency(self) -> u32 {
                UART_BAUD_RATE_GENERATOR_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
        }
        /// Clock tree configuration.
        ///
        /// The fields of this struct are optional, with the following caveats:
        /// - If `XTAL_CLK` is not specified, the crystal frequency will be automatically detected
        ///   if possible.
        /// - The CPU and its upstream clock nodes will be set to a default configuration.
        /// - Other unspecified clock sources will not be useable by peripherals.
        #[derive(Debug, Clone, Copy, PartialEq, Eq)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[instability::unstable]
        pub struct ClockConfig {
            /// `XTAL_CLK` configuration.
            pub xtal_clk: Option<XtalClkConfig>,
            /// `SYSTEM_PRE_DIV` configuration.
            pub system_pre_div: Option<SystemPreDivConfig>,
            /// `CPU_PLL_DIV` configuration.
            pub cpu_pll_div: Option<CpuPllDivConfig>,
            /// `CPU_CLK` configuration.
            pub cpu_clk: Option<CpuClkConfig>,
            /// `RC_FAST_CLK_DIV_N` configuration.
            pub rc_fast_clk_div_n: Option<RcFastClkDivNConfig>,
            /// `RTC_SLOW_CLK` configuration.
            pub rtc_slow_clk: Option<RtcSlowClkConfig>,
            /// `BLE_LP_CLK` configuration.
            pub ble_lp_clk: Option<BleLpClkConfig>,
            /// `RTC_FAST_CLK` configuration.
            pub rtc_fast_clk: Option<RtcFastClkConfig>,
            /// `LOW_POWER_CLK` configuration.
            pub low_power_clk: Option<LowPowerClkConfig>,
            /// `TIMG_CALIBRATION_CLOCK` configuration.
            pub timg_calibration_clock: Option<TimgCalibrationClockConfig>,
        }
        impl ClockConfig {
            fn apply(&self, clocks: &mut ClockTree) {
                if let Some(config) = self.xtal_clk {
                    configure_xtal_clk(clocks, config);
                }
                if let Some(config) = self.system_pre_div {
                    configure_system_pre_div(clocks, config);
                }
                if let Some(config) = self.cpu_pll_div {
                    configure_cpu_pll_div(clocks, config);
                }
                if let Some(config) = self.cpu_clk {
                    configure_cpu_clk(clocks, config);
                }
                if let Some(config) = self.rc_fast_clk_div_n {
                    configure_rc_fast_clk_div_n(clocks, config);
                }
                if let Some(config) = self.rtc_slow_clk {
                    configure_rtc_slow_clk(clocks, config);
                }
                if let Some(config) = self.ble_lp_clk {
                    configure_ble_lp_clk(clocks, config);
                }
                if let Some(config) = self.rtc_fast_clk {
                    configure_rtc_fast_clk(clocks, config);
                }
                if let Some(config) = self.low_power_clk {
                    configure_low_power_clk(clocks, config);
                }
                if let Some(config) = self.timg_calibration_clock {
                    configure_timg_calibration_clock(clocks, config);
                }
            }
        }
        fn increment_reference_count(refcount: &mut u32) -> bool {
            let first = *refcount == 0;
            *refcount = unwrap!(refcount.checked_add(1), "Reference count overflow");
            first
        }
        fn decrement_reference_count(refcount: &mut u32) -> bool {
            *refcount = refcount.saturating_sub(1);
            let last = *refcount == 0;
            last
        }
        fn refresh_xtal_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.xtal_clk {
                XTAL_CLK_FREQ_CACHE.store(
                    xtal_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_system_pre_div_in_downstream(clocks);
            refresh_cpu_pll_div_downstream(clocks);
            refresh_ble_lp_clk_downstream(clocks);
            refresh_rtc_fast_clk_downstream(clocks);
            refresh_low_power_clk_downstream(clocks);
            for child_instance in [I2cInstance::I2c0] {
                refresh_i2c_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [SpiInstance::Spi2] {
                refresh_spi_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [TimgInstance::Timg0] {
                refresh_timg_function_clock_downstream(clocks, child_instance);
                refresh_timg_wdt_clock_downstream(clocks, child_instance);
            }
            for child_instance in [UartInstance::Uart0, UartInstance::Uart1] {
                refresh_uart_function_clock_downstream(clocks, child_instance);
            }
        }
        fn refresh_rc_fast_clk_downstream(clocks: &mut ClockTree) {
            refresh_system_pre_div_in_downstream(clocks);
            refresh_rc_fast_clk_div_n_downstream(clocks);
            refresh_rtc_slow_clk_downstream(clocks);
            refresh_low_power_clk_downstream(clocks);
            refresh_timg_calibration_clock_downstream(clocks);
            for child_instance in [I2cInstance::I2c0] {
                refresh_i2c_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [UartInstance::Uart0, UartInstance::Uart1] {
                refresh_uart_function_clock_downstream(clocks, child_instance);
            }
        }
        fn refresh_rc_slow_clk_downstream(clocks: &mut ClockTree) {
            refresh_rtc_slow_clk_downstream(clocks);
            refresh_ble_lp_clk_downstream(clocks);
            refresh_timg_calibration_clock_downstream(clocks);
        }
        fn refresh_system_pre_div_in_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.system_pre_div_in {
                SYSTEM_PRE_DIV_IN_FREQ_CACHE.store(
                    system_pre_div_in_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_system_pre_div_downstream(clocks);
        }
        fn refresh_system_pre_div_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.system_pre_div {
                SYSTEM_PRE_DIV_FREQ_CACHE.store(
                    system_pre_div_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_cpu_clk_downstream(clocks);
        }
        fn refresh_cpu_pll_div_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.cpu_pll_div {
                CPU_PLL_DIV_FREQ_CACHE.store(
                    cpu_pll_div_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_cpu_clk_downstream(clocks);
        }
        fn refresh_cpu_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.cpu_clk {
                CPU_CLK_FREQ_CACHE.store(
                    cpu_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_apb_clk_downstream(clocks);
            refresh_crypto_clk_downstream(clocks);
            refresh_mspi_clk_downstream(clocks);
            for child_instance in [SpiInstance::Spi2] {
                refresh_spi_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [TimgInstance::Timg0] {
                refresh_timg_function_clock_downstream(clocks, child_instance);
                refresh_timg_wdt_clock_downstream(clocks, child_instance);
            }
            for child_instance in [UartInstance::Uart0, UartInstance::Uart1] {
                refresh_uart_function_clock_downstream(clocks, child_instance);
            }
        }
        fn refresh_rc_fast_clk_div_n_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.rc_fast_clk_div_n {
                RC_FAST_CLK_DIV_N_FREQ_CACHE.store(
                    rc_fast_clk_div_n_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_rtc_fast_clk_downstream(clocks);
        }
        fn refresh_rtc_slow_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.rtc_slow_clk {
                RTC_SLOW_CLK_FREQ_CACHE.store(
                    rtc_slow_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_low_power_clk_downstream(clocks);
        }
        fn refresh_ble_lp_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.ble_lp_clk {
                BLE_LP_CLK_FREQ_CACHE.store(
                    ble_lp_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_rtc_fast_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.rtc_fast_clk {
                RTC_FAST_CLK_FREQ_CACHE.store(
                    rtc_fast_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_low_power_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.low_power_clk {
                LOW_POWER_CLK_FREQ_CACHE.store(
                    low_power_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_timg_calibration_clock_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.timg_calibration_clock {
                TIMG_CALIBRATION_CLOCK_FREQ_CACHE.store(
                    timg_calibration_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_i2c_function_clock_downstream(clocks: &mut ClockTree, instance: I2cInstance) {
            if let Some(config) = clocks.i2c_function_clock[instance as usize] {
                I2C_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    I2cInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_spi_function_clock_downstream(clocks: &mut ClockTree, instance: SpiInstance) {
            if let Some(config) = clocks.spi_function_clock[instance as usize] {
                SPI_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    SpiInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_timg_function_clock_downstream(clocks: &mut ClockTree, instance: TimgInstance) {
            if let Some(config) = clocks.timg_function_clock[instance as usize] {
                TIMG_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    TimgInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_timg_wdt_clock_downstream(clocks: &mut ClockTree, instance: TimgInstance) {
            if let Some(config) = clocks.timg_wdt_clock[instance as usize] {
                TIMG_WDT_CLOCK_FREQ_CACHE[instance as usize].store(
                    TimgInstance::wdt_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_uart_function_clock_downstream(clocks: &mut ClockTree, instance: UartInstance) {
            if let Some(config) = clocks.uart_function_clock[instance as usize] {
                UART_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    UartInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_uart_baud_rate_generator_downstream(clocks, instance);
        }
        fn refresh_uart_baud_rate_generator_downstream(
            clocks: &mut ClockTree,
            instance: UartInstance,
        ) {
            if let Some(config) = clocks.uart_baud_rate_generator[instance as usize] {
                UART_BAUD_RATE_GENERATOR_FREQ_CACHE[instance as usize].store(
                    instance.baud_rate_generator_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_apb_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.apb_clk {
                APB_CLK_FREQ_CACHE.store(
                    apb_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_crypto_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.crypto_clk {
                CRYPTO_CLK_FREQ_CACHE.store(
                    crypto_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_mspi_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.mspi_clk {
                MSPI_CLK_FREQ_CACHE.store(
                    mspi_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
    };
}
/// Implement the `Peripheral` enum and enable/disable/reset functions.
///
/// This macro is intended to be placed in `esp_hal::system`.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! implement_peripheral_clocks {
    () => {
        #[doc(hidden)]
        #[derive(Debug, Clone, Copy, PartialEq, Eq)]
        #[repr(u8)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum Peripheral {
            /// AHB_GDMA peripheral clock signal
            AhbGdma,
            /// APB_SAR_ADC peripheral clock signal
            ApbSarAdc,
            /// ECC peripheral clock signal
            Ecc,
            /// I2C_EXT0 peripheral clock signal
            I2cExt0,
            /// LEDC peripheral clock signal
            Ledc,
            /// SHA peripheral clock signal
            Sha,
            /// SPI2 peripheral clock signal
            Spi2,
            /// SYSTIMER peripheral clock signal
            Systimer,
            /// TIMG0 peripheral clock signal
            Timg0,
            /// TSENS peripheral clock signal
            Tsens,
            /// UART0 peripheral clock signal
            Uart0,
            /// UART1 peripheral clock signal
            Uart1,
            /// UART_MEM peripheral clock signal
            UartMem,
        }
        impl Peripheral {
            const KEEP_ENABLED: &[Peripheral] =
                &[Self::Systimer, Self::Timg0, Self::Uart0, Self::UartMem];
            const COUNT: usize = Self::ALL.len();
            const ALL: &[Self] = &[
                Self::AhbGdma,
                Self::ApbSarAdc,
                Self::Ecc,
                Self::I2cExt0,
                Self::Ledc,
                Self::Sha,
                Self::Spi2,
                Self::Systimer,
                Self::Timg0,
                Self::Tsens,
                Self::Uart0,
                Self::Uart1,
                Self::UartMem,
            ];
        }
        unsafe fn enable_internal_racey(peripheral: Peripheral, enable: bool) {
            match peripheral {
                Peripheral::AhbGdma => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.dma_clk_en().bit(enable));
                }
                Peripheral::ApbSarAdc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.apb_saradc_clk_en().bit(enable));
                }
                Peripheral::Ecc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.crypto_ecc_clk_en().bit(enable));
                }
                Peripheral::I2cExt0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.i2c_ext0_clk_en().bit(enable));
                }
                Peripheral::Ledc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.ledc_clk_en().bit(enable));
                }
                Peripheral::Sha => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.crypto_sha_clk_en().bit(enable));
                }
                Peripheral::Spi2 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.spi2_clk_en().bit(enable));
                }
                Peripheral::Systimer => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.systimer_clk_en().bit(enable));
                }
                Peripheral::Timg0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.timergroup_clk_en().bit(enable));
                }
                Peripheral::Tsens => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en1()
                        .modify(|_, w| w.tsens_clk_en().bit(enable));
                }
                Peripheral::Uart0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.uart_clk_en().bit(enable));
                }
                Peripheral::Uart1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.uart1_clk_en().bit(enable));
                }
                Peripheral::UartMem => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_clk_en0()
                        .modify(|_, w| w.uart_mem_clk_en().bit(enable));
                }
            }
        }
        unsafe fn assert_peri_reset_racey(peripheral: Peripheral, reset: bool) {
            match peripheral {
                Peripheral::AhbGdma => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.dma_rst().bit(reset));
                }
                Peripheral::ApbSarAdc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.apb_saradc_rst().bit(reset));
                }
                Peripheral::Ecc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.crypto_ecc_rst().bit(reset));
                }
                Peripheral::I2cExt0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.i2c_ext0_rst().bit(reset));
                }
                Peripheral::Ledc => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.ledc_rst().bit(reset));
                }
                Peripheral::Sha => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.crypto_sha_rst().bit(reset));
                }
                Peripheral::Spi2 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.spi2_rst().bit(reset));
                }
                Peripheral::Systimer => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.systimer_rst().bit(reset));
                }
                Peripheral::Timg0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.timergroup_rst().bit(reset));
                }
                Peripheral::Tsens => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en1()
                        .modify(|_, w| w.tsens_rst().bit(reset));
                }
                Peripheral::Uart0 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.uart_rst().bit(reset));
                }
                Peripheral::Uart1 => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.uart1_rst().bit(reset));
                }
                Peripheral::UartMem => {
                    crate::peripherals::SYSTEM::regs()
                        .perip_rst_en0()
                        .modify(|_, w| w.uart_mem_rst().bit(reset));
                }
            }
        }
    };
}
/// Macro to get the address range of the given memory region.
///
/// This macro provides two syntax options for each memory region:
///
/// - `memory_range!("region_name")` returns the address range as a range expression (`start..end`).
/// - `memory_range!(size as str, "region_name")` returns the size of the region as a string
///   literal.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! memory_range {
    ("DRAM") => {
        0x3FCA0000..0x3FCE0000
    };
    (size as str, "DRAM") => {
        "262144"
    };
    ("DRAM2_UNINIT") => {
        0x3FCCE800..0x3FCDEB70
    };
    (size as str, "DRAM2_UNINIT") => {
        "66416"
    };
    ("IROM") => {
        0x42000000..0x42400000
    };
    (size as str, "IROM") => {
        "4194304"
    };
    ("DROM") => {
        0x3C000000..0x3C400000
    };
    (size as str, "DROM") => {
        "4194304"
    };
}
/// This macro can be used to generate code for each peripheral instance of the I2C master driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($id:literal, $instance:ident, $sys:ident, $scl:ident, $sda:ident)`
///
/// Macro fragments:
/// - `$id`: the index of the I2C instance
/// - `$instance`: the name of the I2C instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$scl`, `$sda`: peripheral signal names.
///
/// Example data: `(0, I2C0, I2cExt0, I2CEXT0_SCL, I2CEXT0_SDA)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_i2c_master {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_i2c_master { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_i2c_master!((0, I2C0, I2cExt0, I2CEXT0_SCL,
        I2CEXT0_SDA)); _for_each_inner_i2c_master!((all(0, I2C0, I2cExt0, I2CEXT0_SCL,
        I2CEXT0_SDA)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the UART driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($id:literal, $instance:ident, $sys:ident, $rx:ident, $tx:ident, $cts:ident,
/// $rts:ident)`
///
/// Macro fragments:
///
/// - `$id`: the index of the UART instance
/// - `$instance`: the name of the UART instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$rx`, `$tx`, `$cts`, `$rts`: signal names.
///
/// Example data: `(0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_uart {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_uart { $(($pattern) => $code;)* ($other : tt) => {}
        } _for_each_inner_uart!((0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS,
        wakeup_source = true)); _for_each_inner_uart!((1, UART1, Uart1, U1RXD, U1TXD,
        U1CTS, U1RTS, wakeup_source = true)); _for_each_inner_uart!((all(0, UART0, Uart0,
        U0RXD, U0TXD, U0CTS, U0RTS, wakeup_source = true), (1, UART1, Uart1, U1RXD,
        U1TXD, U1CTS, U1RTS, wakeup_source = true)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the SPI master driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $sclk:ident [$($cs:ident),*] [$($sio:ident),*]
/// $($is_qspi:literal)?)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the SPI instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$cs`, `$sio`: chip select and SIO signal names.
/// - `$is_qspi`: a `true` literal present if the SPI instance supports QSPI.
///
/// Example data:
/// - `(SPI2, Spi2, FSPICLK [FSPICS0, FSPICS1, FSPICS2, FSPICS3, FSPICS4, FSPICS5] [FSPID, FSPIQ,
///   FSPIWP, FSPIHD, FSPIIO4, FSPIIO5, FSPIIO6, FSPIIO7], true)`
/// - `(SPI3, Spi3, SPI3_CLK [SPI3_CS0, SPI3_CS1, SPI3_CS2] [SPI3_D, SPI3_Q])`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_spi_master {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_spi_master { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_spi_master!((SPI2)); _for_each_inner_spi_master!((SPI2,
        Spi2, FSPICLK[FSPICS0, FSPICS1, FSPICS2, FSPICS3, FSPICS4, FSPICS5] [FSPID,
        FSPIQ, FSPIWP, FSPIHD], true)); _for_each_inner_spi_master!((names(SPI2)));
        _for_each_inner_spi_master!((all(SPI2, Spi2, FSPICLK[FSPICS0, FSPICS1, FSPICS2,
        FSPICS3, FSPICS4, FSPICS5] [FSPID, FSPIQ, FSPIWP, FSPIHD], true)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the SPI slave driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $sclk:ident, $mosi:ident, $miso:ident, $cs:ident)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the SPI instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$sclk`, `$mosi`, `$miso`, `$cs`: signal names.
///
/// Example data: `(SPI2, Spi2, FSPICLK, FSPID, FSPIQ, FSPICS0)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_spi_slave {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_spi_slave { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_spi_slave!((SPI2)); _for_each_inner_spi_slave!((SPI2,
        Spi2, FSPICLK, FSPID, FSPIQ, FSPICS0));
        _for_each_inner_spi_slave!((names(SPI2))); _for_each_inner_spi_slave!((all(SPI2,
        Spi2, FSPICLK, FSPID, FSPIQ, FSPICS0)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_peripheral {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_peripheral { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO0 peripheral singleton"] GPIO0 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO1 peripheral singleton"]
        GPIO1 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO2 peripheral singleton"] GPIO2 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO3 peripheral singleton"]
        GPIO3 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO4 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO4 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO5 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO5 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO6 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO6 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO7 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO7 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO8 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO8 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO9 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO9 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO10 peripheral singleton"]
        GPIO10 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO11 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO11 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO12 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO12 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO13 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO13 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO14 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO14 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO15 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO15 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO16 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO16 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO17 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO17 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO18 peripheral singleton"]
        GPIO18 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO19 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO19 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO20 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO20 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA_CH0 peripheral singleton"]
        DMA_CH0 <= virtual(DMA_CH0 : { bind_dma_interrupt, enable_dma_interrupt,
        disable_dma_interrupt }) (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "APB_CTRL peripheral singleton"] APB_CTRL <= APB_CTRL() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "APB_SARADC peripheral singleton"] APB_SARADC <= APB_SARADC() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "BB peripheral singleton"] BB <=
        BB() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "ASSIST_DEBUG peripheral singleton"] ASSIST_DEBUG <= ASSIST_DEBUG() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA peripheral singleton"] DMA
        <= DMA() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "ECC peripheral singleton"] ECC <= ECC() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "EFUSE peripheral singleton"]
        EFUSE <= EFUSE() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "EXTMEM peripheral singleton"] EXTMEM <= EXTMEM() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "MMU_TABLE peripheral singleton"] MMU_TABLE <= MMU_TABLE() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO peripheral singleton"]
        GPIO <= GPIO() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "I2C_ANA_MST peripheral singleton"] I2C_ANA_MST <= I2C_ANA_MST() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "I2C0 peripheral singleton"]
        I2C0 <= I2C0(I2C_EXT0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "INTERRUPT_CORE0 peripheral singleton"] INTERRUPT_CORE0 <= INTERRUPT_CORE0()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "IO_MUX peripheral singleton"] IO_MUX <= IO_MUX() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LEDC peripheral singleton"]
        LEDC <= LEDC() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "RNG peripheral singleton"] RNG <= RNG() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LPWR peripheral singleton"]
        LPWR <= RTC_CNTL() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "RTC_TIMER peripheral singleton"] RTC_TIMER <= RTC_CNTL() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "MODEM_CLKRST peripheral singleton"] MODEM_CLKRST <= MODEM_CLKRST() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "SENSITIVE peripheral singleton"] SENSITIVE <= SENSITIVE() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SHA peripheral singleton"] SHA
        <= SHA(SHA : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt
        }) (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SPI0 peripheral singleton"] SPI0 <= SPI0() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SPI1 peripheral singleton"]
        SPI1 <= SPI1() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SPI2 peripheral singleton"] SPI2 <= SPI2(SPI2 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SYSTEM peripheral singleton"]
        SYSTEM <= SYSTEM() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SYSTIMER peripheral singleton"] SYSTIMER <= SYSTIMER() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "TIMG0 peripheral singleton"]
        TIMG0 <= TIMG0() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "UART0 peripheral singleton"] UART0 <= UART0(UART0 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "UART1 peripheral singleton"]
        UART1 <= UART1(UART1 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "XTS_AES peripheral singleton"] XTS_AES <= XTS_AES() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "ADC1 peripheral singleton"]
        ADC1 <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "BT peripheral singleton"] BT <= virtual(LP_TIMER : { bind_lp_timer_interrupt,
        enable_lp_timer_interrupt, disable_lp_timer_interrupt }, BT_MAC : {
        bind_mac_interrupt, enable_mac_interrupt, disable_mac_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "FLASH peripheral singleton"]
        FLASH <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO_DEDICATED peripheral singleton"] GPIO_DEDICATED <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "WIFI peripheral singleton"]
        WIFI <= virtual(WIFI_MAC : { bind_mac_interrupt, enable_mac_interrupt,
        disable_mac_interrupt }, WIFI_PWR : { bind_pwr_interrupt, enable_pwr_interrupt,
        disable_pwr_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR0 peripheral singleton"] FROM_CPU_INTR0 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR1 peripheral singleton"] FROM_CPU_INTR1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR2 peripheral singleton"] FROM_CPU_INTR2 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR3 peripheral singleton"] FROM_CPU_INTR3 <= virtual() (unstable)));
        _for_each_inner_peripheral!((GPIO0)); _for_each_inner_peripheral!((GPIO1));
        _for_each_inner_peripheral!((GPIO2)); _for_each_inner_peripheral!((GPIO3));
        _for_each_inner_peripheral!((GPIO4)); _for_each_inner_peripheral!((GPIO5));
        _for_each_inner_peripheral!((GPIO6)); _for_each_inner_peripheral!((GPIO7));
        _for_each_inner_peripheral!((GPIO8)); _for_each_inner_peripheral!((GPIO9));
        _for_each_inner_peripheral!((GPIO10)); _for_each_inner_peripheral!((GPIO11));
        _for_each_inner_peripheral!((GPIO12)); _for_each_inner_peripheral!((GPIO13));
        _for_each_inner_peripheral!((GPIO14)); _for_each_inner_peripheral!((GPIO15));
        _for_each_inner_peripheral!((GPIO16)); _for_each_inner_peripheral!((GPIO17));
        _for_each_inner_peripheral!((GPIO18)); _for_each_inner_peripheral!((GPIO19));
        _for_each_inner_peripheral!((GPIO20));
        _for_each_inner_peripheral!((DMA_CH0(unstable)));
        _for_each_inner_peripheral!((APB_CTRL(unstable)));
        _for_each_inner_peripheral!((APB_SARADC(unstable)));
        _for_each_inner_peripheral!((BB(unstable)));
        _for_each_inner_peripheral!((ASSIST_DEBUG(unstable)));
        _for_each_inner_peripheral!((DMA(unstable)));
        _for_each_inner_peripheral!((ECC(unstable)));
        _for_each_inner_peripheral!((EXTMEM(unstable)));
        _for_each_inner_peripheral!((GPIO(unstable)));
        _for_each_inner_peripheral!((I2C_ANA_MST(unstable)));
        _for_each_inner_peripheral!((I2C0));
        _for_each_inner_peripheral!((INTERRUPT_CORE0(unstable)));
        _for_each_inner_peripheral!((IO_MUX(unstable)));
        _for_each_inner_peripheral!((LEDC(unstable)));
        _for_each_inner_peripheral!((RNG(unstable)));
        _for_each_inner_peripheral!((LPWR(unstable)));
        _for_each_inner_peripheral!((RTC_TIMER(unstable)));
        _for_each_inner_peripheral!((MODEM_CLKRST(unstable)));
        _for_each_inner_peripheral!((SENSITIVE(unstable)));
        _for_each_inner_peripheral!((SHA(unstable)));
        _for_each_inner_peripheral!((SPI0(unstable)));
        _for_each_inner_peripheral!((SPI1(unstable)));
        _for_each_inner_peripheral!((SPI2));
        _for_each_inner_peripheral!((SYSTEM(unstable)));
        _for_each_inner_peripheral!((SYSTIMER(unstable)));
        _for_each_inner_peripheral!((TIMG0(unstable)));
        _for_each_inner_peripheral!((UART0)); _for_each_inner_peripheral!((UART1));
        _for_each_inner_peripheral!((XTS_AES(unstable)));
        _for_each_inner_peripheral!((ADC1(unstable)));
        _for_each_inner_peripheral!((BT(unstable)));
        _for_each_inner_peripheral!((FLASH(unstable)));
        _for_each_inner_peripheral!((GPIO_DEDICATED(unstable)));
        _for_each_inner_peripheral!((WIFI));
        _for_each_inner_peripheral!((FROM_CPU_INTR1(unstable)));
        _for_each_inner_peripheral!((FROM_CPU_INTR2(unstable)));
        _for_each_inner_peripheral!((FROM_CPU_INTR3(unstable)));
        _for_each_inner_peripheral!((SPI2, Spi2, 0, AhbGdmaChannel));
        _for_each_inner_peripheral!((SHA, Sha, 7, AhbGdmaChannel));
        _for_each_inner_peripheral!((all(@ peri_type #[doc =
        "GPIO0 peripheral singleton"] GPIO0 <= virtual()), (@ peri_type #[doc =
        "GPIO1 peripheral singleton"] GPIO1 <= virtual()), (@ peri_type #[doc =
        "GPIO2 peripheral singleton"] GPIO2 <= virtual()), (@ peri_type #[doc =
        "GPIO3 peripheral singleton"] GPIO3 <= virtual()), (@ peri_type #[doc =
        "GPIO4 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO4 <= virtual()), (@ peri_type #[doc =
        "GPIO5 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO5 <= virtual()), (@ peri_type #[doc =
        "GPIO6 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO6 <= virtual()), (@ peri_type #[doc =
        "GPIO7 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO7 <= virtual()), (@ peri_type #[doc =
        "GPIO8 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO8 <= virtual()), (@ peri_type #[doc =
        "GPIO9 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO9 <= virtual()), (@ peri_type #[doc =
        "GPIO10 peripheral singleton"] GPIO10 <= virtual()), (@ peri_type #[doc =
        "GPIO11 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO11 <= virtual()), (@ peri_type #[doc =
        "GPIO12 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO12 <= virtual()), (@ peri_type #[doc =
        "GPIO13 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO13 <= virtual()), (@ peri_type #[doc =
        "GPIO14 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO14 <= virtual()), (@ peri_type #[doc =
        "GPIO15 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO15 <= virtual()), (@ peri_type #[doc =
        "GPIO16 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO16 <= virtual()), (@ peri_type #[doc =
        "GPIO17 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO17 <= virtual()), (@ peri_type #[doc =
        "GPIO18 peripheral singleton"] GPIO18 <= virtual()), (@ peri_type #[doc =
        "GPIO19 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO19 <= virtual()), (@ peri_type #[doc =
        "GPIO20 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO20 <= virtual()), (@ peri_type #[doc =
        "DMA_CH0 peripheral singleton"] DMA_CH0 <= virtual(DMA_CH0 : {
        bind_dma_interrupt, enable_dma_interrupt, disable_dma_interrupt }) (unstable)),
        (@ peri_type #[doc = "APB_CTRL peripheral singleton"] APB_CTRL <= APB_CTRL()
        (unstable)), (@ peri_type #[doc = "APB_SARADC peripheral singleton"] APB_SARADC
        <= APB_SARADC() (unstable)), (@ peri_type #[doc = "BB peripheral singleton"] BB
        <= BB() (unstable)), (@ peri_type #[doc = "ASSIST_DEBUG peripheral singleton"]
        ASSIST_DEBUG <= ASSIST_DEBUG() (unstable)), (@ peri_type #[doc =
        "DMA peripheral singleton"] DMA <= DMA() (unstable)), (@ peri_type #[doc =
        "ECC peripheral singleton"] ECC <= ECC() (unstable)), (@ peri_type #[doc =
        "EFUSE peripheral singleton"] EFUSE <= EFUSE() (unstable)), (@ peri_type #[doc =
        "EXTMEM peripheral singleton"] EXTMEM <= EXTMEM() (unstable)), (@ peri_type #[doc
        = "MMU_TABLE peripheral singleton"] MMU_TABLE <= MMU_TABLE() (unstable)), (@
        peri_type #[doc = "GPIO peripheral singleton"] GPIO <= GPIO() (unstable)), (@
        peri_type #[doc = "I2C_ANA_MST peripheral singleton"] I2C_ANA_MST <=
        I2C_ANA_MST() (unstable)), (@ peri_type #[doc = "I2C0 peripheral singleton"] I2C0
        <= I2C0(I2C_EXT0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc =
        "INTERRUPT_CORE0 peripheral singleton"] INTERRUPT_CORE0 <= INTERRUPT_CORE0()
        (unstable)), (@ peri_type #[doc = "IO_MUX peripheral singleton"] IO_MUX <=
        IO_MUX() (unstable)), (@ peri_type #[doc = "LEDC peripheral singleton"] LEDC <=
        LEDC() (unstable)), (@ peri_type #[doc = "RNG peripheral singleton"] RNG <= RNG()
        (unstable)), (@ peri_type #[doc = "LPWR peripheral singleton"] LPWR <= RTC_CNTL()
        (unstable)), (@ peri_type #[doc = "RTC_TIMER peripheral singleton"] RTC_TIMER <=
        RTC_CNTL() (unstable)), (@ peri_type #[doc = "MODEM_CLKRST peripheral singleton"]
        MODEM_CLKRST <= MODEM_CLKRST() (unstable)), (@ peri_type #[doc =
        "SENSITIVE peripheral singleton"] SENSITIVE <= SENSITIVE() (unstable)), (@
        peri_type #[doc = "SHA peripheral singleton"] SHA <= SHA(SHA : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "SPI0 peripheral singleton"] SPI0 <= SPI0()
        (unstable)), (@ peri_type #[doc = "SPI1 peripheral singleton"] SPI1 <= SPI1()
        (unstable)), (@ peri_type #[doc = "SPI2 peripheral singleton"] SPI2 <= SPI2(SPI2
        : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (@
        peri_type #[doc = "SYSTEM peripheral singleton"] SYSTEM <= SYSTEM() (unstable)),
        (@ peri_type #[doc = "SYSTIMER peripheral singleton"] SYSTIMER <= SYSTIMER()
        (unstable)), (@ peri_type #[doc = "TIMG0 peripheral singleton"] TIMG0 <= TIMG0()
        (unstable)), (@ peri_type #[doc = "UART0 peripheral singleton"] UART0 <=
        UART0(UART0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "UART1 peripheral singleton"]
        UART1 <= UART1(UART1 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "XTS_AES peripheral singleton"]
        XTS_AES <= XTS_AES() (unstable)), (@ peri_type #[doc =
        "ADC1 peripheral singleton"] ADC1 <= virtual() (unstable)), (@ peri_type #[doc =
        "BT peripheral singleton"] BT <= virtual(LP_TIMER : { bind_lp_timer_interrupt,
        enable_lp_timer_interrupt, disable_lp_timer_interrupt }, BT_MAC : {
        bind_mac_interrupt, enable_mac_interrupt, disable_mac_interrupt }) (unstable)),
        (@ peri_type #[doc = "FLASH peripheral singleton"] FLASH <= virtual()
        (unstable)), (@ peri_type #[doc = "GPIO_DEDICATED peripheral singleton"]
        GPIO_DEDICATED <= virtual() (unstable)), (@ peri_type #[doc =
        "WIFI peripheral singleton"] WIFI <= virtual(WIFI_MAC : { bind_mac_interrupt,
        enable_mac_interrupt, disable_mac_interrupt }, WIFI_PWR : { bind_pwr_interrupt,
        enable_pwr_interrupt, disable_pwr_interrupt })), (@ peri_type #[doc =
        "FROM_CPU_INTR0 peripheral singleton"] FROM_CPU_INTR0 <= virtual() (unstable)),
        (@ peri_type #[doc = "FROM_CPU_INTR1 peripheral singleton"] FROM_CPU_INTR1 <=
        virtual() (unstable)), (@ peri_type #[doc =
        "FROM_CPU_INTR2 peripheral singleton"] FROM_CPU_INTR2 <= virtual() (unstable)),
        (@ peri_type #[doc = "FROM_CPU_INTR3 peripheral singleton"] FROM_CPU_INTR3 <=
        virtual() (unstable)))); _for_each_inner_peripheral!((singletons(GPIO0), (GPIO1),
        (GPIO2), (GPIO3), (GPIO4), (GPIO5), (GPIO6), (GPIO7), (GPIO8), (GPIO9), (GPIO10),
        (GPIO11), (GPIO12), (GPIO13), (GPIO14), (GPIO15), (GPIO16), (GPIO17), (GPIO18),
        (GPIO19), (GPIO20), (DMA_CH0(unstable)), (APB_CTRL(unstable)),
        (APB_SARADC(unstable)), (BB(unstable)), (ASSIST_DEBUG(unstable)),
        (DMA(unstable)), (ECC(unstable)), (EXTMEM(unstable)), (GPIO(unstable)),
        (I2C_ANA_MST(unstable)), (I2C0), (INTERRUPT_CORE0(unstable)), (IO_MUX(unstable)),
        (LEDC(unstable)), (RNG(unstable)), (LPWR(unstable)), (RTC_TIMER(unstable)),
        (MODEM_CLKRST(unstable)), (SENSITIVE(unstable)), (SHA(unstable)),
        (SPI0(unstable)), (SPI1(unstable)), (SPI2), (SYSTEM(unstable)),
        (SYSTIMER(unstable)), (TIMG0(unstable)), (UART0), (UART1), (XTS_AES(unstable)),
        (ADC1(unstable)), (BT(unstable)), (FLASH(unstable)), (GPIO_DEDICATED(unstable)),
        (WIFI), (FROM_CPU_INTR1(unstable)), (FROM_CPU_INTR2(unstable)),
        (FROM_CPU_INTR3(unstable)))); _for_each_inner_peripheral!((dma_eligible(SPI2,
        Spi2, 0, AhbGdmaChannel), (SHA, Sha, 7, AhbGdmaChannel)));
    };
}
/// This macro can be used to generate code for each `GPIOn` instance.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($n:literal, $gpio:ident ($($digital_input_function:ident =>
/// $digital_input_signal:ident)*) ($($digital_output_function:ident =>
/// $digital_output_signal:ident)*) ($([$pin_attribute:ident])*))`
///
/// Macro fragments:
///
/// - `$n`: the number of the GPIO. For `GPIO0`, `$n` is 0.
/// - `$gpio`: the name of the GPIO.
/// - `$digital_input_function`: the number of the digital function, as an identifier (i.e. for
///   function 0 this is `_0`).
/// - `$digital_input_function`: the name of the digital function, as an identifier.
/// - `$digital_output_function`: the number of the digital function, as an identifier (i.e. for
///   function 0 this is `_0`).
/// - `$digital_output_function`: the name of the digital function, as an identifier.
/// - `$pin_attribute`: `Input` and/or `Output`, marks the possible directions of the GPIO.
///   Bracketed so that they can also be matched as optional fragments. Order is always Input first.
///
/// Example data: `(0, GPIO0 (_5 => EMAC_TX_CLK) (_1 => CLK_OUT1 _5 => EMAC_TX_CLK) ([Input]
/// [Output]))`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_gpio {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_gpio { $(($pattern) => $code;)* ($other : tt) => {}
        } _for_each_inner_gpio!((0, GPIO0() () ([Input] [Output])));
        _for_each_inner_gpio!((1, GPIO1() () ([Input] [Output])));
        _for_each_inner_gpio!((2, GPIO2(_2 => FSPIQ) (_2 => FSPIQ) ([Input] [Output])));
        _for_each_inner_gpio!((3, GPIO3() () ([Input] [Output])));
        _for_each_inner_gpio!((4, GPIO4(_0 => MTMS _2 => FSPIHD) (_2 => FSPIHD) ([Input]
        [Output]))); _for_each_inner_gpio!((5, GPIO5(_0 => MTDI _2 => FSPIWP) (_2 =>
        FSPIWP) ([Input] [Output]))); _for_each_inner_gpio!((6, GPIO6(_0 => MTCK _2 =>
        FSPICLK) (_2 => FSPICLK) ([Input] [Output]))); _for_each_inner_gpio!((7, GPIO7(_2
        => FSPID) (_0 => MTDO _2 => FSPID) ([Input] [Output])));
        _for_each_inner_gpio!((8, GPIO8() () ([Input] [Output])));
        _for_each_inner_gpio!((9, GPIO9() () ([Input] [Output])));
        _for_each_inner_gpio!((10, GPIO10(_2 => FSPICS0) (_2 => FSPICS0) ([Input]
        [Output]))); _for_each_inner_gpio!((11, GPIO11(_0 => SPIHD) (_0 => SPIHD)
        ([Input] [Output]))); _for_each_inner_gpio!((12, GPIO12(_0 => SPIHD) (_0 =>
        SPIHD) ([Input] [Output]))); _for_each_inner_gpio!((13, GPIO13(_0 => SPIWP) (_0
        => SPIWP) ([Input] [Output]))); _for_each_inner_gpio!((14, GPIO14() (_0 =>
        SPICS0) ([Input] [Output]))); _for_each_inner_gpio!((15, GPIO15() (_0 => SPICLK)
        ([Input] [Output]))); _for_each_inner_gpio!((16, GPIO16(_0 => SPID) (_0 => SPID)
        ([Input] [Output]))); _for_each_inner_gpio!((17, GPIO17(_0 => SPIQ) (_0 => SPIQ)
        ([Input] [Output]))); _for_each_inner_gpio!((18, GPIO18() () ([Input]
        [Output]))); _for_each_inner_gpio!((19, GPIO19(_0 => U0RXD) () ([Input]
        [Output]))); _for_each_inner_gpio!((20, GPIO20() (_0 => U0TXD) ([Input]
        [Output]))); _for_each_inner_gpio!((all(0, GPIO0() () ([Input] [Output])), (1,
        GPIO1() () ([Input] [Output])), (2, GPIO2(_2 => FSPIQ) (_2 => FSPIQ) ([Input]
        [Output])), (3, GPIO3() () ([Input] [Output])), (4, GPIO4(_0 => MTMS _2 =>
        FSPIHD) (_2 => FSPIHD) ([Input] [Output])), (5, GPIO5(_0 => MTDI _2 => FSPIWP)
        (_2 => FSPIWP) ([Input] [Output])), (6, GPIO6(_0 => MTCK _2 => FSPICLK) (_2 =>
        FSPICLK) ([Input] [Output])), (7, GPIO7(_2 => FSPID) (_0 => MTDO _2 => FSPID)
        ([Input] [Output])), (8, GPIO8() () ([Input] [Output])), (9, GPIO9() () ([Input]
        [Output])), (10, GPIO10(_2 => FSPICS0) (_2 => FSPICS0) ([Input] [Output])), (11,
        GPIO11(_0 => SPIHD) (_0 => SPIHD) ([Input] [Output])), (12, GPIO12(_0 => SPIHD)
        (_0 => SPIHD) ([Input] [Output])), (13, GPIO13(_0 => SPIWP) (_0 => SPIWP)
        ([Input] [Output])), (14, GPIO14() (_0 => SPICS0) ([Input] [Output])), (15,
        GPIO15() (_0 => SPICLK) ([Input] [Output])), (16, GPIO16(_0 => SPID) (_0 => SPID)
        ([Input] [Output])), (17, GPIO17(_0 => SPIQ) (_0 => SPIQ) ([Input] [Output])),
        (18, GPIO18() () ([Input] [Output])), (19, GPIO19(_0 => U0RXD) () ([Input]
        [Output])), (20, GPIO20() (_0 => U0TXD) ([Input] [Output]))));
    };
}
/// This macro can be used to generate code for each analog function of each GPIO.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident)` - simple case where you only need identifiers
/// - group: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident)` - expanded signal
///   case, where you need the number(s) of a signal, or the general group to which the signal
///   belongs. For example, in case of `ADC2_CH3` the expanded form looks like `(ADC2_CH3, ADCn_CHm,
///   2, 3)`.
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders. For `ADC2_CH3` this
///   is `ADCn_CHm`.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
///
/// Example data:
/// - `(ADC2_CH5, GPIO12)`
/// - `((ADC2_CH5, ADCn_CHm, 2, 5), GPIO12)`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_analog_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_analog_function { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_analog_function!((ADC1_CH0, GPIO0));
        _for_each_inner_analog_function!((ADC1_CH1, GPIO1));
        _for_each_inner_analog_function!((ADC1_CH2, GPIO2));
        _for_each_inner_analog_function!((ADC1_CH3, GPIO3));
        _for_each_inner_analog_function!((ADC1_CH4, GPIO4));
        _for_each_inner_analog_function!(((ADC1_CH0, ADCn_CHm, 1, 0), GPIO0));
        _for_each_inner_analog_function!(((ADC1_CH1, ADCn_CHm, 1, 1), GPIO1));
        _for_each_inner_analog_function!(((ADC1_CH2, ADCn_CHm, 1, 2), GPIO2));
        _for_each_inner_analog_function!(((ADC1_CH3, ADCn_CHm, 1, 3), GPIO3));
        _for_each_inner_analog_function!(((ADC1_CH4, ADCn_CHm, 1, 4), GPIO4));
        _for_each_inner_analog_function!((all(ADC1_CH0, GPIO0), (ADC1_CH1, GPIO1),
        (ADC1_CH2, GPIO2), (ADC1_CH3, GPIO3), (ADC1_CH4, GPIO4)));
        _for_each_inner_analog_function!((ADCn_CHm((ADC1_CH0, ADCn_CHm, 1, 0), GPIO0),
        ((ADC1_CH1, ADCn_CHm, 1, 1), GPIO1), ((ADC1_CH2, ADCn_CHm, 1, 2), GPIO2),
        ((ADC1_CH3, ADCn_CHm, 1, 3), GPIO3), ((ADC1_CH4, ADCn_CHm, 1, 4), GPIO4)));
    };
}
/// This macro can be used to generate code for each LP function of each GPIO.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident, $af:ident)` - simple case where you only need
///   identifiers, and maybe the function.
/// - group: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident, $af:ident, ($(
///   $lp_input_af:ident => $lp_input_signal:ident )*) ($( $lp_output_af:ident =>
///   $lp_output_signal:ident )*))` - expanded signal case, where you need the number(s) of a
///   signal, or the general group to which the signal belongs. Every expanded branch ends with the
///   pad's LP input and output function groups (empty on chips without an LP GPIO matrix).
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders. For `ADC2_CH3` this
///   is `ADCn_CHm`.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
/// - `$af`: the LP IO MUX function, as an identifier (i.e. for function 0 this is `_0`). This is
///   the name of an `LpFunction` variant, and its number is the value to write to the pad's
///   function select field.
/// - `$lp_input_af`: the LP IO MUX function for an LP peripheral input on this pad.
/// - `$lp_input_signal`: the LP peripheral input signal name.
/// - `$lp_output_af`: the LP IO MUX function for an LP peripheral output on this pad.
/// - `$lp_output_signal`: the LP peripheral output signal name.
///
/// Example data:
/// - `(LP_GPIO15, GPIO12, _0)`
/// - `((LP_GPIO15, LP_GPIOn, 15), GPIO12, _0, () ())`
/// - `((LP_GPIO14, LP_GPIOn, 14), GPIO14, _1, () (_0 => LP_UART_TXD))`
/// - `((SAR_I2C_SCL_1, SAR_I2C_SCL_n, 1), GPIO2, _3, () ())`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_lp_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_lp_function { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_lp_function!((LP_GPIO0, GPIO0, _0));
        _for_each_inner_lp_function!((LP_GPIO1, GPIO1, _0));
        _for_each_inner_lp_function!((LP_GPIO2, GPIO2, _0));
        _for_each_inner_lp_function!((LP_GPIO3, GPIO3, _0));
        _for_each_inner_lp_function!((LP_GPIO4, GPIO4, _0));
        _for_each_inner_lp_function!((LP_GPIO5, GPIO5, _0));
        _for_each_inner_lp_function!(((LP_GPIO0, LP_GPIOn, 0), GPIO0, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO1, LP_GPIOn, 1), GPIO1, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO2, LP_GPIOn, 2), GPIO2, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO3, LP_GPIOn, 3), GPIO3, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO4, LP_GPIOn, 4), GPIO4, _0, () ()));
        _for_each_inner_lp_function!(((LP_GPIO5, LP_GPIOn, 5), GPIO5, _0, () ()));
        _for_each_inner_lp_function!((all(LP_GPIO0, GPIO0, _0), (LP_GPIO1, GPIO1, _0),
        (LP_GPIO2, GPIO2, _0), (LP_GPIO3, GPIO3, _0), (LP_GPIO4, GPIO4, _0), (LP_GPIO5,
        GPIO5, _0))); _for_each_inner_lp_function!((LP_GPIOn((LP_GPIO0, LP_GPIOn, 0),
        GPIO0, _0, () ()), ((LP_GPIO1, LP_GPIOn, 1), GPIO1, _0, () ()), ((LP_GPIO2,
        LP_GPIOn, 2), GPIO2, _0, () ()), ((LP_GPIO3, LP_GPIOn, 3), GPIO3, _0, () ()),
        ((LP_GPIO4, LP_GPIOn, 4), GPIO4, _0, () ()), ((LP_GPIO5, LP_GPIOn, 5), GPIO5, _0,
        () ())));
    };
}
/// This macro can be used to generate code for each IOMUX digital function of each GPIO.
///
/// IOMUX functions are the alternate digital functions configured via the IO_MUX registers.
/// Use this to implement signal-specific traits for peripherals whose pins must bypass the
/// GPIO matrix (e.g., EMAC, USB).
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident, $af:ident)` - simple case where you only need
///   identifiers, and maybe the alternate function.
/// - group: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident, $af:ident)` -
///   expanded signal case, where you need the number(s) of a signal, or the general group to which
///   the signal belongs.
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
/// - `$af`: the alternate function number, as an identifier (e.g. `_5`).
///
/// Example data:
/// - `(EMAC_RXD0, GPIO25, _5)`
/// - `((EMAC_RXDn, EMAC_RXDn, 0), GPIO25, _5)`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_iomux_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_iomux_function { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_iomux_function!((FSPIQ, GPIO2, _2));
        _for_each_inner_iomux_function!((MTMS, GPIO4, _0));
        _for_each_inner_iomux_function!((FSPIHD, GPIO4, _2));
        _for_each_inner_iomux_function!((MTDI, GPIO5, _0));
        _for_each_inner_iomux_function!((FSPIWP, GPIO5, _2));
        _for_each_inner_iomux_function!((MTCK, GPIO6, _0));
        _for_each_inner_iomux_function!((FSPICLK, GPIO6, _2));
        _for_each_inner_iomux_function!((MTDO, GPIO7, _0));
        _for_each_inner_iomux_function!((FSPID, GPIO7, _2));
        _for_each_inner_iomux_function!((FSPICS0, GPIO10, _2));
        _for_each_inner_iomux_function!((SPIHD, GPIO11, _0));
        _for_each_inner_iomux_function!((SPIHD, GPIO12, _0));
        _for_each_inner_iomux_function!((SPIWP, GPIO13, _0));
        _for_each_inner_iomux_function!((SPICS0, GPIO14, _0));
        _for_each_inner_iomux_function!((SPICLK, GPIO15, _0));
        _for_each_inner_iomux_function!((SPID, GPIO16, _0));
        _for_each_inner_iomux_function!((SPIQ, GPIO17, _0));
        _for_each_inner_iomux_function!((U0RXD, GPIO19, _0));
        _for_each_inner_iomux_function!((U0TXD, GPIO20, _0));
        _for_each_inner_iomux_function!(((FSPICS0, FSPICSn, 0), GPIO10, _2));
        _for_each_inner_iomux_function!(((SPICS0, SPICSn, 0), GPIO14, _0));
        _for_each_inner_iomux_function!((all(FSPIQ, GPIO2, _2), (MTMS, GPIO4, _0),
        (FSPIHD, GPIO4, _2), (MTDI, GPIO5, _0), (FSPIWP, GPIO5, _2), (MTCK, GPIO6, _0),
        (FSPICLK, GPIO6, _2), (MTDO, GPIO7, _0), (FSPID, GPIO7, _2), (FSPICS0, GPIO10,
        _2), (SPIHD, GPIO11, _0), (SPIHD, GPIO12, _0), (SPIWP, GPIO13, _0), (SPICS0,
        GPIO14, _0), (SPICLK, GPIO15, _0), (SPID, GPIO16, _0), (SPIQ, GPIO17, _0),
        (U0RXD, GPIO19, _0), (U0TXD, GPIO20, _0)));
        _for_each_inner_iomux_function!((FSPICSn((FSPICS0, FSPICSn, 0), GPIO10, _2)));
        _for_each_inner_iomux_function!((SPICSn((SPICS0, SPICSn, 0), GPIO14, _0)));
    };
}
/// Returns the name of the GPIO that provides the given signal, as a string.
///
/// The macro takes the name of a direct function - a digital IO MUX function, an analog
/// function, or an LP IO MUX function - and expands to a string literal like `"GPIO4"`. It
/// is meant to keep documentation free of per-chip pin lists.
///
/// Signals that are not wired to a pad on this chip have to be routed through the GPIO
/// matrix, which can reach any pad. The macro has no pad to return for those, so it accepts
/// an optional fallback to expand to instead. The fallback is not validated.
///
/// If multiple pads provide the signal, the macro returns one that is not reserved for some
/// other purpose, such as booting or interfacing with flash.
///
/// Example usage:
/// - `gpio_for_signal!(ADC1_CH0)`
/// - `gpio_for_signal!(LP_I2C_SDA, "GPIO6")`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! gpio_for_signal {
    (ADC1_CH0 $(, $_fallback:literal)?) => {
        "GPIO0"
    };
    (LP_GPIO0 $(, $_fallback:literal)?) => {
        "GPIO0"
    };
    (ADC1_CH1 $(, $_fallback:literal)?) => {
        "GPIO1"
    };
    (LP_GPIO1 $(, $_fallback:literal)?) => {
        "GPIO1"
    };
    (FSPIQ $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (ADC1_CH2 $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (LP_GPIO2 $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (ADC1_CH3 $(, $_fallback:literal)?) => {
        "GPIO3"
    };
    (LP_GPIO3 $(, $_fallback:literal)?) => {
        "GPIO3"
    };
    (MTMS $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (FSPIHD $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (ADC1_CH4 $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (LP_GPIO4 $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (MTDI $(, $_fallback:literal)?) => {
        "GPIO5"
    };
    (FSPIWP $(, $_fallback:literal)?) => {
        "GPIO5"
    };
    (LP_GPIO5 $(, $_fallback:literal)?) => {
        "GPIO5"
    };
    (MTCK $(, $_fallback:literal)?) => {
        "GPIO6"
    };
    (FSPICLK $(, $_fallback:literal)?) => {
        "GPIO6"
    };
    (MTDO $(, $_fallback:literal)?) => {
        "GPIO7"
    };
    (FSPID $(, $_fallback:literal)?) => {
        "GPIO7"
    };
    (FSPICS0 $(, $_fallback:literal)?) => {
        "GPIO10"
    };
    (SPIHD $(, $_fallback:literal)?) => {
        "GPIO11"
    };
    (SPIWP $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (SPICS0 $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (SPICLK $(, $_fallback:literal)?) => {
        "GPIO15"
    };
    (SPID $(, $_fallback:literal)?) => {
        "GPIO16"
    };
    (SPIQ $(, $_fallback:literal)?) => {
        "GPIO17"
    };
    (U0RXD $(, $_fallback:literal)?) => {
        "GPIO19"
    };
    (U0TXD $(, $_fallback:literal)?) => {
        "GPIO20"
    };
    ($_signal:ident, $fallback:literal) => {
        $fallback
    };
}
/// Defines the `InputSignal` and `OutputSignal` enums.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_io_mux_signals {
    () => {
        #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
        #[derive(Debug, PartialEq, Copy, Clone)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum InputSignal {
            SPIQ          = 0,
            SPID          = 1,
            SPIHD         = 2,
            SPIWP         = 3,
            U0RXD         = 6,
            U0CTS         = 7,
            U0DSR         = 8,
            U1RXD         = 9,
            U1CTS         = 10,
            U1DSR         = 11,
            CPU_GPIO_0    = 28,
            CPU_GPIO_1    = 29,
            CPU_GPIO_2    = 30,
            CPU_GPIO_3    = 31,
            CPU_GPIO_4    = 32,
            CPU_GPIO_5    = 33,
            CPU_GPIO_6    = 34,
            CPU_GPIO_7    = 35,
            EXT_ADC_START = 45,
            RMT_SIG_0     = 51,
            RMT_SIG_1     = 52,
            I2CEXT0_SCL   = 53,
            I2CEXT0_SDA   = 54,
            FSPICLK       = 63,
            FSPIQ         = 64,
            FSPID         = 65,
            FSPIHD        = 66,
            FSPIWP        = 67,
            FSPICS0       = 68,
            SIG_FUNC_97   = 97,
            SIG_FUNC_98   = 98,
            SIG_FUNC_99   = 99,
            SIG_FUNC_100  = 100,
            MTCK,
            MTMS,
            MTDI,
        }
        #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
        #[derive(Debug, PartialEq, Copy, Clone)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum OutputSignal {
            SPIQ          = 0,
            SPID          = 1,
            SPIHD         = 2,
            SPIWP         = 3,
            SPICLK        = 4,
            SPICS0        = 5,
            U0TXD         = 6,
            U0RTS         = 7,
            U0DTR         = 8,
            U1TXD         = 9,
            U1RTS         = 10,
            U1DTR         = 11,
            SPIQ_MONITOR  = 15,
            SPID_MONITOR  = 16,
            SPIHD_MONITOR = 17,
            SPIWP_MONITOR = 18,
            SPICS1        = 19,
            CPU_GPIO_0    = 28,
            CPU_GPIO_1    = 29,
            CPU_GPIO_2    = 30,
            CPU_GPIO_3    = 31,
            CPU_GPIO_4    = 32,
            CPU_GPIO_5    = 33,
            CPU_GPIO_6    = 34,
            CPU_GPIO_7    = 35,
            LEDC_LS_SIG0  = 45,
            LEDC_LS_SIG1  = 46,
            LEDC_LS_SIG2  = 47,
            LEDC_LS_SIG3  = 48,
            LEDC_LS_SIG4  = 49,
            LEDC_LS_SIG5  = 50,
            RMT_SIG_0     = 51,
            RMT_SIG_1     = 52,
            I2CEXT0_SCL   = 53,
            I2CEXT0_SDA   = 54,
            FSPICLK       = 63,
            FSPIQ         = 64,
            FSPID         = 65,
            FSPIHD        = 66,
            FSPIWP        = 67,
            FSPICS0       = 68,
            FSPICS1       = 69,
            FSPICS3       = 70,
            FSPICS2       = 71,
            FSPICS4       = 72,
            FSPICS5       = 73,
            ANT_SEL0      = 89,
            ANT_SEL1      = 90,
            ANT_SEL2      = 91,
            ANT_SEL3      = 92,
            ANT_SEL4      = 93,
            ANT_SEL5      = 94,
            ANT_SEL6      = 95,
            ANT_SEL7      = 96,
            SIG_FUNC_97   = 97,
            SIG_FUNC_98   = 98,
            SIG_FUNC_99   = 99,
            SIG_FUNC_100  = 100,
            CLK_OUT1      = 123,
            CLK_OUT2      = 124,
            CLK_OUT3      = 125,
            GPIO          = 128,
            MTDO,
        }
    };
}
/// Defines the `LpFunction` enum.
///
/// The enum only contains the LP IO MUX functions that the chip implements. It is
/// empty on chips without an LP IO peripheral.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_lp_functions {
    () => {
        /// LP IO MUX function of a pad.
        ///
        /// This is the low-power counterpart of `AlternateFunction`: it selects which function
        /// drives a pad while the pad belongs to the low-power domain.
        #[derive(Debug, Eq, PartialEq, Copy, Clone, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum LpFunction {
            /// LP IO MUX function 0.
            _0 = 0,
        }
        impl LpFunction {
            /// The function that connects the pad to the LP GPIO peripheral.
            pub const LP_GPIO: Self = Self::_0;
        }
    };
}
/// Defines and implements the `io_mux_reg` function.
///
/// The generated function has the following signature:
///
/// ```rust,ignore
/// pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO0 {
///     // ...
/// # unimplemented!()
/// }
/// ```
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[expect(clippy::crate_in_macro_def)]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_io_mux_reg {
    () => {
        pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO {
            crate::peripherals::IO_MUX::regs().gpio(gpio_num as usize)
        }
    };
}