esp_metadata_generated/

_generated_esp32c61.rs

// Do NOT edit this file directly. Make your changes to esp-metadata,
// then run `cargo update-metadata`.

/// The name of the chip as `&str`
///
/// # Example
///
/// ```rust, no_run
/// use esp_hal::chip;
/// let chip_name = chip!();
#[doc = concat!("assert_eq!(chip_name, ", chip!(), ")")]
/// ```
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! chip {
    () => {
        "esp32c61"
    };
}
/// The pretty name of the chip as `&str`
///
/// # Example
///
/// ```rust, no_run
/// use esp_hal::chip;
/// let chip_name = chip_pretty!();
#[doc = concat!("assert_eq!(chip_name, ", chip_pretty!(), ")")]
/// ```
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! chip_pretty {
    () => {
        "ESP32-C61"
    };
}
/// The properties of this chip and its drivers.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! property {
    ("chip") => {
        "esp32c61"
    };
    ("arch") => {
        "riscv"
    };
    ("cores") => {
        1
    };
    ("cores", str) => {
        stringify!(1)
    };
    ("trm") => {
        "https://www.espressif.com/sites/default/files/documentation/esp32-c61_technical_reference_manual_en.pdf"
    };
    ("gpio.version") => {
        2
    };
    ("gpio.version", str) => {
        stringify!(2)
    };
    ("gpio.has_input_sync") => {
        true
    };
    ("gpio.gpio_function") => {
        1
    };
    ("gpio.gpio_function", str) => {
        stringify!(1)
    };
    ("gpio.constant_0_input") => {
        96
    };
    ("gpio.constant_0_input", str) => {
        stringify!(96)
    };
    ("gpio.constant_1_input") => {
        64
    };
    ("gpio.constant_1_input", str) => {
        stringify!(64)
    };
    ("gpio.remap_iomux_pin_registers") => {
        false
    };
    ("gpio.func_in_sel_offset") => {
        0
    };
    ("gpio.func_in_sel_offset", str) => {
        stringify!(0)
    };
    ("gpio.need_soft_isolate_during_pd") => {
        false
    };
    ("gpio.has_bank_1") => {
        false
    };
    ("gpio.input_signal_max") => {
        100
    };
    ("gpio.input_signal_max", str) => {
        stringify!(100)
    };
    ("gpio.output_signal_max") => {
        256
    };
    ("gpio.output_signal_max", str) => {
        stringify!(256)
    };
    ("dedicated_gpio.version") => {
        "riscv_v1"
    };
    ("dedicated_gpio.needs_initialization") => {
        false
    };
    ("dedicated_gpio.channel_count") => {
        8
    };
    ("dedicated_gpio.channel_count", str) => {
        stringify!(8)
    };
    ("lp_io.version") => {
        "v4"
    };
    ("lp_io.has_gpio_matrix") => {
        false
    };
    ("uart.ram_size") => {
        128
    };
    ("uart.ram_size", str) => {
        stringify!(128)
    };
    ("uart.version") => {
        2
    };
    ("uart.version", str) => {
        stringify!(2)
    };
    ("uart.peripheral_controls_mem_clk") => {
        true
    };
    ("uart.has_sclk_divider") => {
        false
    };
    ("uart.has_sclk_enable") => {
        true
    };
    ("i2c_master.version") => {
        4
    };
    ("i2c_master.version", str) => {
        stringify!(4)
    };
    ("i2c_master.has_fsm_timeouts") => {
        true
    };
    ("i2c_master.has_hw_bus_clear") => {
        true
    };
    ("i2c_master.has_bus_timeout_enable") => {
        true
    };
    ("i2c_master.separate_filter_config_registers") => {
        false
    };
    ("i2c_master.can_estimate_nack_reason") => {
        true
    };
    ("i2c_master.has_conf_update") => {
        true
    };
    ("i2c_master.has_reliable_fsm_reset") => {
        true
    };
    ("i2c_master.has_arbitration_en") => {
        true
    };
    ("i2c_master.has_tx_fifo_watermark") => {
        true
    };
    ("i2c_master.bus_timeout_is_exponential") => {
        true
    };
    ("i2c_master.has_pd_en") => {
        true
    };
    ("i2c_master.max_bus_timeout") => {
        31
    };
    ("i2c_master.max_bus_timeout", str) => {
        stringify!(31)
    };
    ("i2c_master.ll_intr_mask") => {
        262143
    };
    ("i2c_master.ll_intr_mask", str) => {
        stringify!(262143)
    };
    ("i2c_master.fifo_size") => {
        32
    };
    ("i2c_master.fifo_size", str) => {
        stringify!(32)
    };
    ("spi_master.version") => {
        3
    };
    ("spi_master.version", str) => {
        stringify!(3)
    };
    ("spi_master.fifo_size") => {
        64
    };
    ("spi_master.fifo_size", str) => {
        stringify!(64)
    };
    ("spi_master.bit_order_is_bool") => {
        false
    };
    ("spi_master.has_octal") => {
        false
    };
    ("spi_master.has_app_interrupts") => {
        true
    };
    ("spi_master.has_dma_segmented_transfer") => {
        true
    };
    ("spi_master.has_clk_pre_div") => {
        true
    };
    ("spi_master.dma_can_access_flash") => {
        true
    };
    ("i2s.version") => {
        3
    };
    ("i2s.version", str) => {
        stringify!(3)
    };
    ("i2s.mclk_divider_bit_width") => {
        9
    };
    ("i2s.mclk_divider_bit_width", str) => {
        stringify!(9)
    };
    ("i2s.max_ws_width") => {
        512
    };
    ("i2s.max_ws_width", str) => {
        stringify!(512)
    };
    ("i2s.clock_configured_by_pcr") => {
        true
    };
    ("i2s.clock_configured_by_hp_sys_clkrst") => {
        false
    };
    ("i2s.supports_pdm_rx_hp_filter") => {
        false
    };
    ("i2s.supports_pdm_tx") => {
        true
    };
    ("i2s.supports_pdm_rx") => {
        true
    };
    ("i2s.supports_pcm2pdm") => {
        true
    };
    ("i2s.supports_pdm2pcm") => {
        false
    };
    ("bt.controller") => {
        "npl"
    };
    ("wifi.has_wifi6") => {
        true
    };
    ("wifi.mac_version") => {
        3
    };
    ("wifi.mac_version", str) => {
        stringify!(3)
    };
    ("wifi.has_5g") => {
        false
    };
    ("wifi.csi_supported") => {
        true
    };
    ("wifi.has_nan") => {
        true
    };
    ("wifi.has_ftm") => {
        true
    };
    ("phy.combo_module") => {
        true
    };
    ("adc.controller") => {
        "digital"
    };
    ("adc.channel_count") => {
        4
    };
    ("adc.channel_count", str) => {
        stringify!(4)
    };
    ("adc.line_calibration") => {
        true
    };
    ("adc.curve_calibration") => {
        true
    };
    ("adc.basic_calibration") => {
        true
    };
    ("adc.calibration_v1_scheme_supported") => {
        true
    };
    ("adc.channel_compensation") => {
        true
    };
    ("adc.pcr_clock") => {
        true
    };
    ("adc.pcr_sar_clk_div") => {
        true
    };
    ("adc.sar_power_override") => {
        true
    };
    ("timergroup.timg_has_timer1") => {
        false
    };
    ("timergroup.timg_has_divcnt_rst") => {
        true
    };
    ("timergroup.wdt_has_conf_update") => {
        true
    };
    ("timergroup.rc_fast_calibration_divider_min_rev") => {
        0
    };
    ("timergroup.rc_fast_calibration_divider") => {
        32
    };
    ("timergroup.rc_fast_calibration_tick_enable") => {
        false
    };
    ("ecc.zero_extend_writes") => {
        true
    };
    ("ecc.separate_jacobian_point_memory") => {
        true
    };
    ("ecc.has_memory_clock_gate") => {
        true
    };
    ("ecc.supports_enhanced_security") => {
        true
    };
    ("ecc.mem_block_size") => {
        32
    };
    ("rng.apb_cycle_wait_num") => {
        16
    };
    ("rng.apb_cycle_wait_num", str) => {
        stringify!(16)
    };
    ("rng.trng_supported") => {
        true
    };
    ("rng.is_lp_sys") => {
        true
    };
    ("sleep.light_sleep") => {
        true
    };
    ("sleep.deep_sleep") => {
        true
    };
    ("sleep.rejectable_mask") => {
        4094
    };
    ("sleep.ext1_version") => {
        2
    };
    ("sleep.ext1_version", str) => {
        stringify!(2)
    };
    ("sleep.pin_wakeup_version") => {
        3
    };
    ("sleep.pin_wakeup_version", str) => {
        stringify!(3)
    };
    ("sleep.deep_sleep_needs_gpio_isolation") => {
        false
    };
    ("assist_debug.has_sp_monitor") => {
        true
    };
    ("assist_debug.has_region_monitor") => {
        true
    };
    ("dma.mem2mem_requires_peripheral") => {
        false
    };
    ("dma.ext_mem_configurable_block_size") => {
        false
    };
    ("dma.separate_in_out_interrupts") => {
        true
    };
    ("dma.gdma_version") => {
        2
    };
    ("dma.gdma_version", str) => {
        stringify!(2)
    };
    ("interrupts.status_registers") => {
        3
    };
    ("interrupts.status_registers", str) => {
        stringify!(3)
    };
    ("interrupts.disabled_interrupt") => {
        0
    };
    ("mmu.page_size") => {
        65536
    };
    ("mmu.page_size", str) => {
        stringify!(65536)
    };
    ("mmu.entry_num") => {
        512
    };
    ("mmu.entry_num", str) => {
        stringify!(512)
    };
    ("psram.octal_spi") => {
        false
    };
    ("psram.hex_spi") => {
        false
    };
    ("psram.extmem_origin") => {
        1107296256
    };
    ("psram.extmem_origin", str) => {
        stringify!(1107296256)
    };
    ("rom.has_crc_le") => {
        true
    };
    ("rom.has_crc_be") => {
        true
    };
    ("rom.has_md5_bsd") => {
        true
    };
    ("rom.has_md5_mbedtls") => {
        false
    };
    ("soc.cpu_has_branch_predictor") => {
        true
    };
    ("soc.cpu_has_csr_pc") => {
        false
    };
    ("soc.cpu_has_zcmp_workaround") => {
        false
    };
    ("soc.multi_core_enabled") => {
        false
    };
    ("soc.cpu_csr_prv_mode") => {
        2064
    };
    ("soc.cpu_csr_prv_mode", str) => {
        stringify!(2064)
    };
    ("soc.internal_memory_cached") => {
        false
    };
    ("soc.has_swd_watchdog") => {
        true
    };
    ("soc.cpu_mcause_mask") => {
        31
    };
    ("soc.cpu_mcause_mask", str) => {
        stringify!(31)
    };
    ("soc.cpu_pmp_granularity") => {
        128
    };
    ("soc.cpu_pmp_granularity", str) => {
        stringify!(128)
    };
    ("clock_tree.hp_root_clk") => {
        [crate ::soc::clocks::HpRootClkConfig::Xtal, crate
        ::soc::clocks::HpRootClkConfig::RcFast, crate
        ::soc::clocks::HpRootClkConfig::PllF160m]
    };
    ("clock_tree.cpu_clk.divisor") => {
        (0, 255)
    };
    ("clock_tree.ahb_clk.divisor") => {
        (0, 255)
    };
    ("clock_tree.apb_clk.divisor") => {
        (0, 255)
    };
    ("clock_tree.lp_fast_clk") => {
        [crate ::soc::clocks::LpFastClkConfig::RcFast, crate
        ::soc::clocks::LpFastClkConfig::XtalD2, crate
        ::soc::clocks::LpFastClkConfig::Xtal]
    };
    ("clock_tree.lp_slow_clk") => {
        [crate ::soc::clocks::LpSlowClkConfig::RcSlow, #[cfg(use_xtal32k)] crate
        ::soc::clocks::LpSlowClkConfig::Xtal32k, crate
        ::soc::clocks::LpSlowClkConfig::OscSlow]
    };
    ("clock_tree.ble_lp_clk") => {
        [crate ::soc::clocks::BleLpClkConfig::Xtal, crate
        ::soc::clocks::BleLpClkConfig::RcSlow, #[cfg(use_xtal32k)] crate
        ::soc::clocks::BleLpClkConfig::Xtal32k]
    };
    ("clock_tree.crypto_clk") => {
        [crate ::soc::clocks::CryptoClkConfig::Xtal, crate
        ::soc::clocks::CryptoClkConfig::RcFast, crate
        ::soc::clocks::CryptoClkConfig::PllF480m]
    };
    ("clock_tree.timg_calibration_clock") => {
        [crate ::soc::clocks::TimgCalibrationClockConfig::OscSlowClk, crate
        ::soc::clocks::TimgCalibrationClockConfig::RcSlowClk, crate
        ::soc::clocks::TimgCalibrationClockConfig::RcFastDivClk, #[cfg(use_xtal32k)]
        crate ::soc::clocks::TimgCalibrationClockConfig::Xtal32kClk]
    };
    ("clock_tree.uart.function_clock.sclk") => {
        [crate ::soc::clocks::UartFunctionClockSclk::Xtal, crate
        ::soc::clocks::UartFunctionClockSclk::PllF80m, crate
        ::soc::clocks::UartFunctionClockSclk::RcFast]
    };
    ("clock_tree.uart.function_clock.div_num") => {
        (0, 255)
    };
    ("clock_tree.uart.baud_rate_generator.fractional") => {
        (0, 15)
    };
    ("clock_tree.uart.baud_rate_generator.integral") => {
        (0, 4095)
    };
    ("clock_tree.timg.function_clock") => {
        [crate ::soc::clocks::TimgFunctionClockConfig::XtalClk, crate
        ::soc::clocks::TimgFunctionClockConfig::RcFastClk, crate
        ::soc::clocks::TimgFunctionClockConfig::PllF80m]
    };
    ("clock_tree.timg.wdt_clock") => {
        [crate ::soc::clocks::TimgWdtClockConfig::XtalClk, crate
        ::soc::clocks::TimgWdtClockConfig::RcFastClk, crate
        ::soc::clocks::TimgWdtClockConfig::PllF80m]
    };
    ("clock_tree.i2c.function_clock.sclk") => {
        [crate ::soc::clocks::I2cFunctionClockSclk::Xtal, crate
        ::soc::clocks::I2cFunctionClockSclk::RcFast]
    };
    ("clock_tree.i2c.function_clock.div_num") => {
        (0, 255)
    };
    ("clock_tree.spi.function_clock") => {
        [crate ::soc::clocks::SpiFunctionClockConfig::Xtal, crate
        ::soc::clocks::SpiFunctionClockConfig::PllF160m, crate
        ::soc::clocks::SpiFunctionClockConfig::RcFast]
    };
    ("clock_tree.adc.function_clock") => {
        [crate ::soc::clocks::AdcFunctionClockConfig::Xtal, crate
        ::soc::clocks::AdcFunctionClockConfig::RcFast, crate
        ::soc::clocks::AdcFunctionClockConfig::PllF80m]
    };
    ("clock_tree.i2s.tx_clk.sclk") => {
        [crate ::soc::clocks::I2sClkSclk::Xtal, crate
        ::soc::clocks::I2sClkSclk::PllF120m, crate ::soc::clocks::I2sClkSclk::PllF160m]
    };
    ("clock_tree.i2s.tx_clk.div_num") => {
        (1, 255)
    };
    ("clock_tree.i2s.tx_clk.div_a") => {
        (1, 511)
    };
    ("clock_tree.i2s.tx_clk.div_b") => {
        (0, 511)
    };
    ("clock_tree.i2s.rx_clk.sclk") => {
        [crate ::soc::clocks::I2sClkSclk::Xtal, crate
        ::soc::clocks::I2sClkSclk::PllF120m, crate ::soc::clocks::I2sClkSclk::PllF160m]
    };
    ("clock_tree.i2s.rx_clk.div_num") => {
        (1, 255)
    };
    ("clock_tree.i2s.rx_clk.div_a") => {
        (1, 511)
    };
    ("clock_tree.i2s.rx_clk.div_b") => {
        (0, 511)
    };
    ("clock_tree.i2s.mclk_out") => {
        [crate ::soc::clocks::I2sMclkOutConfig::Tx, crate
        ::soc::clocks::I2sMclkOutConfig::Rx]
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dedicated_gpio {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dedicated_gpio { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_dedicated_gpio!((0));
        _for_each_inner_dedicated_gpio!((1)); _for_each_inner_dedicated_gpio!((2));
        _for_each_inner_dedicated_gpio!((3)); _for_each_inner_dedicated_gpio!((4));
        _for_each_inner_dedicated_gpio!((5)); _for_each_inner_dedicated_gpio!((6));
        _for_each_inner_dedicated_gpio!((7)); _for_each_inner_dedicated_gpio!((0, 0,
        CPU_GPIO_0)); _for_each_inner_dedicated_gpio!((0, 1, CPU_GPIO_1));
        _for_each_inner_dedicated_gpio!((0, 2, CPU_GPIO_2));
        _for_each_inner_dedicated_gpio!((0, 3, CPU_GPIO_3));
        _for_each_inner_dedicated_gpio!((0, 4, CPU_GPIO_4));
        _for_each_inner_dedicated_gpio!((0, 5, CPU_GPIO_5));
        _for_each_inner_dedicated_gpio!((0, 6, CPU_GPIO_6));
        _for_each_inner_dedicated_gpio!((0, 7, CPU_GPIO_7));
        _for_each_inner_dedicated_gpio!((channels(0), (1), (2), (3), (4), (5), (6),
        (7))); _for_each_inner_dedicated_gpio!((signals(0, 0, CPU_GPIO_0), (0, 1,
        CPU_GPIO_1), (0, 2, CPU_GPIO_2), (0, 3, CPU_GPIO_3), (0, 4, CPU_GPIO_4), (0, 5,
        CPU_GPIO_5), (0, 6, CPU_GPIO_6), (0, 7, CPU_GPIO_7)));
    };
}
/// Defines the `LpInputSignal` and `LpOutputSignal` enums.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_lp_io_signals {
    () => {};
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_ecc_working_mode {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_ecc_working_mode { $(($pattern) => $code;)* ($other
        : tt) => {} } _for_each_inner_ecc_working_mode!((0, AffinePointMultiplication));
        _for_each_inner_ecc_working_mode!((2, AffinePointVerification));
        _for_each_inner_ecc_working_mode!((3, AffinePointVerificationAndMultiplication));
        _for_each_inner_ecc_working_mode!((4, JacobianPointMultiplication));
        _for_each_inner_ecc_working_mode!((5, AffinePointAddition));
        _for_each_inner_ecc_working_mode!((6, JacobianPointVerification));
        _for_each_inner_ecc_working_mode!((7,
        AffinePointVerificationAndJacobianPointMultiplication));
        _for_each_inner_ecc_working_mode!((8, ModularAddition));
        _for_each_inner_ecc_working_mode!((9, ModularSubtraction));
        _for_each_inner_ecc_working_mode!((10, ModularMultiplication));
        _for_each_inner_ecc_working_mode!((11, ModularDivision));
        _for_each_inner_ecc_working_mode!((all(0, AffinePointMultiplication), (2,
        AffinePointVerification), (3, AffinePointVerificationAndMultiplication), (4,
        JacobianPointMultiplication), (5, AffinePointAddition), (6,
        JacobianPointVerification), (7,
        AffinePointVerificationAndJacobianPointMultiplication), (8, ModularAddition), (9,
        ModularSubtraction), (10, ModularMultiplication), (11, ModularDivision)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_ecc_curve {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_ecc_curve { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_ecc_curve!((0, P192, 192));
        _for_each_inner_ecc_curve!((1, P256, 256)); _for_each_inner_ecc_curve!((all(0,
        P192, 192), (1, P256, 256)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sha_algorithm {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sha_algorithm { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_sha_algorithm!((Sha1, "SHA-1"(sizes : 64, 20, 8)
        (insecure_against : "collision", "length extension"), 0));
        _for_each_inner_sha_algorithm!((Sha224, "SHA-224"(sizes : 64, 28, 8)
        (insecure_against : "length extension"), 1));
        _for_each_inner_sha_algorithm!((Sha256, "SHA-256"(sizes : 64, 32, 8)
        (insecure_against : "length extension"), 2));
        _for_each_inner_sha_algorithm!((algos(Sha1, "SHA-1"(sizes : 64, 20, 8)
        (insecure_against : "collision", "length extension"), 0), (Sha224,
        "SHA-224"(sizes : 64, 28, 8) (insecure_against : "length extension"), 1),
        (Sha256, "SHA-256"(sizes : 64, 32, 8) (insecure_against : "length extension"),
        2)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_wakeup_source {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_wakeup_source { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_wakeup_source!((Ext1, 1));
        _for_each_inner_wakeup_source!((Gpio, 2));
        _for_each_inner_wakeup_source!((WifiBeacon, 3));
        _for_each_inner_wakeup_source!((Timer, 4)); _for_each_inner_wakeup_source!((Wifi,
        5)); _for_each_inner_wakeup_source!((Uart0, 6));
        _for_each_inner_wakeup_source!((Uart1, 7)); _for_each_inner_wakeup_source!((Sdio,
        8)); _for_each_inner_wakeup_source!((Uart2, 9));
        _for_each_inner_wakeup_source!((Bt, 10)); _for_each_inner_wakeup_source!((LpCore,
        11)); _for_each_inner_wakeup_source!((all(Ext1, 1), (Gpio, 2), (WifiBeacon, 3),
        (Timer, 4), (Wifi, 5), (Uart0, 6), (Uart1, 7), (Sdio, 8), (Uart2, 9), (Bt, 10),
        (LpCore, 11)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_dma_engine!(("AHB_GDMA"));
        _for_each_inner_dma_engine!((all("AHB_GDMA")));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dma_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dma_channel { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH0));
        _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH1));
        _for_each_inner_dma_channel!(("AHB_GDMA", any_channel = AhbGdmaChannel));
        _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH0, 0, interrupt_in = DMA_IN_CH0,
        interrupt_out = DMA_OUT_CH0, compatible = [SPI2, I2S0, SHA]));
        _for_each_inner_dma_channel!(("AHB_GDMA", DMA_CH1, 1, interrupt_in = DMA_IN_CH1,
        interrupt_out = DMA_OUT_CH1, compatible = [SPI2, I2S0, SHA]));
        _for_each_inner_dma_channel!((names("AHB_GDMA", DMA_CH0), ("AHB_GDMA",
        DMA_CH1))); _for_each_inner_dma_channel!((separate_any_type("AHB_GDMA",
        any_channel = AhbGdmaChannel))); _for_each_inner_dma_channel!((shared));
        _for_each_inner_dma_channel!((split("AHB_GDMA", DMA_CH0, 0, interrupt_in =
        DMA_IN_CH0, interrupt_out = DMA_OUT_CH0, compatible = [SPI2, I2S0, SHA]),
        ("AHB_GDMA", DMA_CH1, 1, interrupt_in = DMA_IN_CH1, interrupt_out = DMA_OUT_CH1,
        compatible = [SPI2, I2S0, SHA])));
        _for_each_inner_dma_channel!((no_own_interrupt));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_dma_channel_peri_pair {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_dma_channel_peri_pair { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA",
        DMA_CH0, SPI2)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH0,
        I2S0)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH0, SHA));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, SPI2));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, I2S0));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", DMA_CH1, SHA));
        _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", any_channel = AhbGdmaChannel,
        SPI2)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA", any_channel =
        AhbGdmaChannel, I2S0)); _for_each_inner_dma_channel_peri_pair!(("AHB_GDMA",
        any_channel = AhbGdmaChannel, SHA));
        _for_each_inner_dma_channel_peri_pair!((channels("AHB_GDMA", DMA_CH0, SPI2),
        ("AHB_GDMA", DMA_CH0, I2S0), ("AHB_GDMA", DMA_CH0, SHA), ("AHB_GDMA", DMA_CH1,
        SPI2), ("AHB_GDMA", DMA_CH1, I2S0), ("AHB_GDMA", DMA_CH1, SHA)));
        _for_each_inner_dma_channel_peri_pair!((any_channels("AHB_GDMA", any_channel =
        AhbGdmaChannel, SPI2), ("AHB_GDMA", any_channel = AhbGdmaChannel, I2S0),
        ("AHB_GDMA", any_channel = AhbGdmaChannel, SHA)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_mem2mem_channel {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_mem2mem_channel { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_mem2mem_channel!(("AHB_GDMA", AhbGdma,
        AhbGdmaChannel, DMA_CH0, 4)); _for_each_inner_mem2mem_channel!(("AHB_GDMA",
        AhbGdma, AhbGdmaChannel, DMA_CH1, 5));
        _for_each_inner_mem2mem_channel!(("AHB_GDMA", AhbGdma, AhbGdmaChannel, 0, 4, 1,
        5)); _for_each_inner_mem2mem_channel!(("AHB_GDMA", AhbGdma, AhbGdmaChannel));
        _for_each_inner_mem2mem_channel!((channels("AHB_GDMA", AhbGdma, AhbGdmaChannel,
        DMA_CH0, 4), ("AHB_GDMA", AhbGdma, AhbGdmaChannel, DMA_CH1, 5)));
        _for_each_inner_mem2mem_channel!((erased("AHB_GDMA", AhbGdma, AhbGdmaChannel, 0,
        4, 1, 5))); _for_each_inner_mem2mem_channel!((engines("AHB_GDMA", AhbGdma,
        AhbGdmaChannel)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_i2s_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_i2s_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _with_inner_i2s_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_sha_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_sha_dma_engine { $(($pattern) => $code;)* ($other : tt)
        => {} } _with_inner_sha_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_spi_master_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_spi_master_dma_engine { $(($pattern) => $code;)* ($other
        : tt) => {} } _with_inner_spi_master_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! with_spi_slave_dma_engine {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _with_inner_spi_slave_dma_engine { $(($pattern) => $code;)* ($other
        : tt) => {} } _with_inner_spi_slave_dma_engine!(("AHB_GDMA", AhbGdmaChannel));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_interrupt {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_interrupt { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_interrupt!(([disabled 0] 0));
        _for_each_inner_interrupt!(([reserved 0] 1));
        _for_each_inner_interrupt!(([reserved 1] 2));
        _for_each_inner_interrupt!(([reserved 2] 3));
        _for_each_inner_interrupt!(([reserved 3] 4));
        _for_each_inner_interrupt!(([reserved 4] 5));
        _for_each_inner_interrupt!(([reserved 5] 6));
        _for_each_inner_interrupt!(([reserved 6] 7));
        _for_each_inner_interrupt!(([reserved 7] 8));
        _for_each_inner_interrupt!(([reserved 8] 9));
        _for_each_inner_interrupt!(([reserved 9] 10));
        _for_each_inner_interrupt!(([reserved 10] 11));
        _for_each_inner_interrupt!(([reserved 11] 12));
        _for_each_inner_interrupt!(([reserved 12] 13));
        _for_each_inner_interrupt!(([reserved 13] 14));
        _for_each_inner_interrupt!(([reserved 14] 15));
        _for_each_inner_interrupt!(([vector 0] 16)); _for_each_inner_interrupt!(([vector
        1] 17)); _for_each_inner_interrupt!(([vector 2] 18));
        _for_each_inner_interrupt!(([vector 3] 19)); _for_each_inner_interrupt!(([vector
        4] 20)); _for_each_inner_interrupt!(([vector 5] 21));
        _for_each_inner_interrupt!(([vector 6] 22)); _for_each_inner_interrupt!(([vector
        7] 23)); _for_each_inner_interrupt!(([direct_bindable 0] 24));
        _for_each_inner_interrupt!(([direct_bindable 1] 25));
        _for_each_inner_interrupt!(([direct_bindable 2] 26));
        _for_each_inner_interrupt!(([direct_bindable 3] 27));
        _for_each_inner_interrupt!(([direct_bindable 4] 28));
        _for_each_inner_interrupt!(([direct_bindable 5] 29));
        _for_each_inner_interrupt!(([direct_bindable 6] 30));
        _for_each_inner_interrupt!(([direct_bindable 7] 31));
        _for_each_inner_interrupt!((all([disabled 0] 0), ([reserved 0] 1), ([reserved 1]
        2), ([reserved 2] 3), ([reserved 3] 4), ([reserved 4] 5), ([reserved 5] 6),
        ([reserved 6] 7), ([reserved 7] 8), ([reserved 8] 9), ([reserved 9] 10),
        ([reserved 10] 11), ([reserved 11] 12), ([reserved 12] 13), ([reserved 13] 14),
        ([reserved 14] 15), ([vector 0] 16), ([vector 1] 17), ([vector 2] 18), ([vector
        3] 19), ([vector 4] 20), ([vector 5] 21), ([vector 6] 22), ([vector 7] 23),
        ([direct_bindable 0] 24), ([direct_bindable 1] 25), ([direct_bindable 2] 26),
        ([direct_bindable 3] 27), ([direct_bindable 4] 28), ([direct_bindable 5] 29),
        ([direct_bindable 6] 30), ([direct_bindable 7] 31)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_classified_interrupt {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_classified_interrupt { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_classified_interrupt!(([direct_bindable 0]
        24)); _for_each_inner_classified_interrupt!(([direct_bindable 1] 25));
        _for_each_inner_classified_interrupt!(([direct_bindable 2] 26));
        _for_each_inner_classified_interrupt!(([direct_bindable 3] 27));
        _for_each_inner_classified_interrupt!(([direct_bindable 4] 28));
        _for_each_inner_classified_interrupt!(([direct_bindable 5] 29));
        _for_each_inner_classified_interrupt!(([direct_bindable 6] 30));
        _for_each_inner_classified_interrupt!(([direct_bindable 7] 31));
        _for_each_inner_classified_interrupt!(([vector 0] 16));
        _for_each_inner_classified_interrupt!(([vector 1] 17));
        _for_each_inner_classified_interrupt!(([vector 2] 18));
        _for_each_inner_classified_interrupt!(([vector 3] 19));
        _for_each_inner_classified_interrupt!(([vector 4] 20));
        _for_each_inner_classified_interrupt!(([vector 5] 21));
        _for_each_inner_classified_interrupt!(([vector 6] 22));
        _for_each_inner_classified_interrupt!(([vector 7] 23));
        _for_each_inner_classified_interrupt!(([reserved 0] 1));
        _for_each_inner_classified_interrupt!(([reserved 1] 2));
        _for_each_inner_classified_interrupt!(([reserved 2] 3));
        _for_each_inner_classified_interrupt!(([reserved 3] 4));
        _for_each_inner_classified_interrupt!(([reserved 4] 5));
        _for_each_inner_classified_interrupt!(([reserved 5] 6));
        _for_each_inner_classified_interrupt!(([reserved 6] 7));
        _for_each_inner_classified_interrupt!(([reserved 7] 8));
        _for_each_inner_classified_interrupt!(([reserved 8] 9));
        _for_each_inner_classified_interrupt!(([reserved 9] 10));
        _for_each_inner_classified_interrupt!(([reserved 10] 11));
        _for_each_inner_classified_interrupt!(([reserved 11] 12));
        _for_each_inner_classified_interrupt!(([reserved 12] 13));
        _for_each_inner_classified_interrupt!(([reserved 13] 14));
        _for_each_inner_classified_interrupt!(([reserved 14] 15));
        _for_each_inner_classified_interrupt!((direct_bindable([direct_bindable 0] 24),
        ([direct_bindable 1] 25), ([direct_bindable 2] 26), ([direct_bindable 3] 27),
        ([direct_bindable 4] 28), ([direct_bindable 5] 29), ([direct_bindable 6] 30),
        ([direct_bindable 7] 31))); _for_each_inner_classified_interrupt!((vector([vector
        0] 16), ([vector 1] 17), ([vector 2] 18), ([vector 3] 19), ([vector 4] 20),
        ([vector 5] 21), ([vector 6] 22), ([vector 7] 23)));
        _for_each_inner_classified_interrupt!((reserved([reserved 0] 1), ([reserved 1]
        2), ([reserved 2] 3), ([reserved 3] 4), ([reserved 4] 5), ([reserved 5] 6),
        ([reserved 6] 7), ([reserved 7] 8), ([reserved 8] 9), ([reserved 9] 10),
        ([reserved 10] 11), ([reserved 11] 12), ([reserved 12] 13), ([reserved 13] 14),
        ([reserved 14] 15))); _for_each_inner_classified_interrupt!((context_switch));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_interrupt_priority {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_interrupt_priority { $(($pattern) => $code;)*
        ($other : tt) => {} } _for_each_inner_interrupt_priority!((0, 1, Priority1,
        Level1)); _for_each_inner_interrupt_priority!((1, 2, Priority2, Level2));
        _for_each_inner_interrupt_priority!((2, 3, Priority3, Level3));
        _for_each_inner_interrupt_priority!((3, 4, Priority4, Level4));
        _for_each_inner_interrupt_priority!((4, 5, Priority5, Level5));
        _for_each_inner_interrupt_priority!((5, 6, Priority6, Level6));
        _for_each_inner_interrupt_priority!((6, 7, Priority7, Level7));
        _for_each_inner_interrupt_priority!((7, 8, Priority8, Level8));
        _for_each_inner_interrupt_priority!((all(0, 1, Priority1, Level1), (1, 2,
        Priority2, Level2), (2, 3, Priority3, Level3), (3, 4, Priority4, Level4), (4, 5,
        Priority5, Level5), (5, 6, Priority6, Level6), (6, 7, Priority7, Level7), (7, 8,
        Priority8, Level8)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_sw_interrupt {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_sw_interrupt { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_sw_interrupt!((0, FROM_CPU_INTR0,
        software_interrupt0)); _for_each_inner_sw_interrupt!((1, FROM_CPU_INTR1,
        software_interrupt1)); _for_each_inner_sw_interrupt!((2, FROM_CPU_INTR2,
        software_interrupt2)); _for_each_inner_sw_interrupt!((3, FROM_CPU_INTR3,
        software_interrupt3)); _for_each_inner_sw_interrupt!((all(0, FROM_CPU_INTR0,
        software_interrupt0), (1, FROM_CPU_INTR1, software_interrupt1), (2,
        FROM_CPU_INTR2, software_interrupt2), (3, FROM_CPU_INTR3, software_interrupt3)));
    };
}
#[macro_export]
/// ESP-HAL must provide implementation for the following functions:
/// ```rust, no_run
/// // XTAL_CLK
///
/// fn configure_xtal_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<XtalClkConfig>,
///     _new_config: XtalClkConfig,
/// ) {
///     todo!()
/// }
///
/// // RC_FAST_CLK
///
/// fn enable_rc_fast_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_CLK
///
/// fn enable_pll_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // XTAL32K_CLK
///
/// #[cfg(use_xtal32k)]
/// fn enable_xtal32k_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // OSC_SLOW_CLK
///
/// fn enable_osc_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // RC_SLOW_CLK
///
/// fn enable_rc_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_F20M
///
/// fn enable_pll_f20m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_F40M
///
/// fn enable_pll_f40m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_F48M
///
/// fn enable_pll_f48m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_F60M
///
/// fn enable_pll_f60m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_F80M
///
/// fn enable_pll_f80m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_F120M
///
/// fn enable_pll_f120m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // PLL_F160M
///
/// fn enable_pll_f160m_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // HP_ROOT_CLK
///
/// fn enable_hp_root_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_hp_root_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<HpRootClkConfig>,
///     _new_config: HpRootClkConfig,
/// ) {
///     todo!()
/// }
///
/// // CPU_CLK
///
/// fn enable_cpu_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_cpu_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CpuClkConfig>,
///     _new_config: CpuClkConfig,
/// ) {
///     todo!()
/// }
///
/// // AHB_CLK
///
/// fn enable_ahb_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_ahb_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<AhbClkConfig>,
///     _new_config: AhbClkConfig,
/// ) {
///     todo!()
/// }
///
/// // APB_CLK
///
/// fn enable_apb_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_apb_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<ApbClkConfig>,
///     _new_config: ApbClkConfig,
/// ) {
///     todo!()
/// }
///
/// // XTAL_D2_CLK
///
/// fn enable_xtal_d2_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // LP_FAST_CLK
///
/// fn enable_lp_fast_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_lp_fast_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<LpFastClkConfig>,
///     _new_config: LpFastClkConfig,
/// ) {
///     todo!()
/// }
///
/// // LP_SLOW_CLK
///
/// fn enable_lp_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_lp_slow_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<LpSlowClkConfig>,
///     _new_config: LpSlowClkConfig,
/// ) {
///     todo!()
/// }
///
/// // BLE_LP_XTAL_CLK
///
/// fn enable_ble_lp_xtal_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // BLE_LP_RC_SLOW_CLK
///
/// fn enable_ble_lp_rc_slow_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // BLE_LP_CLK
///
/// fn enable_ble_lp_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_ble_lp_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<BleLpClkConfig>,
///     _new_config: BleLpClkConfig,
/// ) {
///     todo!()
/// }
///
/// // CRYPTO_PLL_DIV
///
/// fn enable_crypto_pll_div_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// // CRYPTO_CLK
///
/// fn enable_crypto_clk_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_crypto_clk_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<CryptoClkConfig>,
///     _new_config: CryptoClkConfig,
/// ) {
///     todo!()
/// }
///
/// // TIMG_CALIBRATION_CLOCK
///
/// fn enable_timg_calibration_clock_impl(_clocks: &mut ClockTree, _en: bool) {
///     todo!()
/// }
///
/// fn configure_timg_calibration_clock_impl(
///     _clocks: &mut ClockTree,
///     _old_config: Option<TimgCalibrationClockConfig>,
///     _new_config: TimgCalibrationClockConfig,
/// ) {
///     todo!()
/// }
///
/// impl AdcInstance {
///     // ADC_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<AdcFunctionClockConfig>,
///         _new_config: AdcFunctionClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl I2cInstance {
///     // I2C_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<I2cFunctionClockConfig>,
///         _new_config: I2cFunctionClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl I2sInstance {
///     // I2S_TX_CLK
///
///     fn enable_tx_clk_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_tx_clk_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<I2sClkConfig>,
///         _new_config: I2sClkConfig,
///     ) {
///         todo!()
///     }
///
///     // I2S_RX_CLK
///
///     fn enable_rx_clk_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_rx_clk_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<I2sClkConfig>,
///         _new_config: I2sClkConfig,
///     ) {
///         todo!()
///     }
///
///     // I2S_MCLK_OUT
///
///     fn enable_mclk_out_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_mclk_out_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<I2sMclkOutConfig>,
///         _new_config: I2sMclkOutConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl SpiInstance {
///     // SPI_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<SpiFunctionClockConfig>,
///         _new_config: SpiFunctionClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl TimgInstance {
///     // TIMG_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<TimgFunctionClockConfig>,
///         _new_config: TimgFunctionClockConfig,
///     ) {
///         todo!()
///     }
///
///     // TIMG_WDT_CLOCK
///
///     fn enable_wdt_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_wdt_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<TimgWdtClockConfig>,
///         _new_config: TimgWdtClockConfig,
///     ) {
///         todo!()
///     }
/// }
/// impl UartInstance {
///     // UART_FUNCTION_CLOCK
///
///     fn enable_function_clock_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_function_clock_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<UartFunctionClockConfig>,
///         _new_config: UartFunctionClockConfig,
///     ) {
///         todo!()
///     }
///
///     // UART_BAUD_RATE_GENERATOR
///
///     fn enable_baud_rate_generator_impl(self, _clocks: &mut ClockTree, _en: bool) {
///         todo!()
///     }
///
///     fn configure_baud_rate_generator_impl(
///         self,
///         _clocks: &mut ClockTree,
///         _old_config: Option<UartBaudRateGeneratorConfig>,
///         _new_config: UartBaudRateGeneratorConfig,
///     ) {
///         todo!()
///     }
/// }
/// ```
macro_rules! define_clock_tree_types {
    () => {
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum AdcInstance {
            ApbSaradc = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2cInstance {
            I2c0 = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2sInstance {
            I2s0 = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SpiInstance {
            Spi2 = 0,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgInstance {
            Timg0 = 0,
            Timg1 = 1,
        }
        #[derive(Clone, Copy, PartialEq, Eq, Debug)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum UartInstance {
            Uart0 = 0,
            Uart1 = 1,
            Uart2 = 2,
        }
        /// Selects the output frequency of `XTAL_CLK`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum XtalClkConfig {
            /// 40 MHz
            _40,
        }
        impl XtalClkConfig {
            pub fn value(&self) -> u32 {
                match self {
                    XtalClkConfig::_40 => 40000000,
                }
            }
        }
        /// The list of clock signals that the `HP_ROOT_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum HpRootClkConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
            /// Selects `PLL_F160M`.
            PllF160m,
        }
        /// Configures the `CPU_CLK` clock node.
        ///
        /// The output is calculated as `OUTPUT = HP_ROOT_CLK / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct CpuClkConfig {
            divisor: u32,
        }
        impl CpuClkConfig {
            /// Creates a new configuration for the CPU_CLK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 255,
                    "`CPU_CLK` divisor must be between 0 and 255 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// Configures the `AHB_CLK` clock node.
        ///
        /// The output is calculated as `OUTPUT = HP_ROOT_CLK / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct AhbClkConfig {
            divisor: u32,
        }
        impl AhbClkConfig {
            /// Creates a new configuration for the AHB_CLK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 255,
                    "`AHB_CLK` divisor must be between 0 and 255 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// Configures the `APB_CLK` clock node.
        ///
        /// The output is calculated as `OUTPUT = AHB_CLK / (divisor + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct ApbClkConfig {
            divisor: u32,
        }
        impl ApbClkConfig {
            /// Creates a new configuration for the APB_CLK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the divisor value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(divisor: u32) -> Self {
                ::core::assert!(
                    divisor <= 255,
                    "`APB_CLK` divisor must be between 0 and 255 (inclusive)."
                );
                Self { divisor }
            }
            pub fn divisor(self) -> u32 {
                self.divisor as u32
            }
        }
        /// The list of clock signals that the `LP_FAST_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum LpFastClkConfig {
            /// Selects `RC_FAST_CLK`.
            RcFast,
            /// Selects `XTAL_D2_CLK`.
            XtalD2,
            /// Selects `XTAL_CLK`.
            Xtal,
        }
        /// The list of clock signals that the `LP_SLOW_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum LpSlowClkConfig {
            /// Selects `RC_SLOW_CLK`.
            RcSlow,
            #[cfg(use_xtal32k)]
            /// Selects `XTAL32K_CLK`.
            Xtal32k,
            /// Selects `OSC_SLOW_CLK`.
            OscSlow,
        }
        /// The list of clock signals that the `BLE_LP_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum BleLpClkConfig {
            /// Selects `BLE_LP_XTAL_CLK`.
            Xtal,
            /// Selects `BLE_LP_RC_SLOW_CLK`.
            RcSlow,
            #[cfg(use_xtal32k)]
            /// Selects `XTAL32K_CLK`.
            Xtal32k,
        }
        /// The list of clock signals that the `CRYPTO_CLK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum CryptoClkConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
            /// Selects `CRYPTO_PLL_DIV`.
            PllF480m,
        }
        /// The list of clock signals that the `TIMG_CALIBRATION_CLOCK` multiplexer can output.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgCalibrationClockConfig {
            /// Selects `OSC_SLOW_CLK`.
            OscSlowClk,
            /// Selects `RC_SLOW_CLK`.
            RcSlowClk,
            /// Selects `RC_FAST_CLK`.
            RcFastDivClk,
            #[cfg(use_xtal32k)]
            /// Selects `XTAL32K_CLK`.
            Xtal32kClk,
        }
        /// The list of clock signals that the `APB_SARADC_FUNCTION_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum AdcFunctionClockConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
            #[default]
            /// Selects `PLL_F80M`.
            PllF80m,
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2cFunctionClockSclk {
            #[default]
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `RC_FAST_CLK`.
            RcFast,
        }
        /// Configures the `I2C0_FUNCTION_CLOCK` clock node.
        ///
        /// The output is calculated as `OUTPUT = sclk / (div_num + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct I2cFunctionClockConfig {
            sclk: I2cFunctionClockSclk,
            div_num: u32,
        }
        impl I2cFunctionClockConfig {
            /// Creates a new configuration for the FUNCTION_CLOCK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(sclk: I2cFunctionClockSclk, div_num: u32) -> Self {
                ::core::assert!(
                    div_num <= 255,
                    "`I2C0_FUNCTION_CLOCK` div_num must be between 0 and 255 (inclusive)."
                );
                Self { sclk, div_num }
            }
            pub fn sclk(self) -> I2cFunctionClockSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2sClkSclk {
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `PLL_F120M`.
            PllF120m,
            #[default]
            /// Selects `PLL_F160M`.
            PllF160m,
        }
        /// Configures the `I2S0_TX_CLK` clock node.
        ///
        /// The output is calculated as `OUTPUT = (sclk * div_a) / (div_num * div_a + div_b)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct I2sClkConfig {
            sclk: I2sClkSclk,
            div_num: u32,
            div_a: u32,
            div_b: u32,
        }
        impl I2sClkConfig {
            /// Creates a new configuration for the TX_CLK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (1 ..= 255).
            ///
            /// Panics if the div_a value is outside the
            /// valid range (1 ..= 511).
            ///
            /// Panics if the div_b value is outside the
            /// valid range (0 ..= 511).
            pub const fn new(sclk: I2sClkSclk, div_num: u32, div_a: u32, div_b: u32) -> Self {
                ::core::assert!(
                    div_num >= 1 && div_num <= 255,
                    "`I2S0_TX_CLK` div_num must be between 1 and 255 (inclusive)."
                );
                ::core::assert!(
                    div_a >= 1 && div_a <= 511,
                    "`I2S0_TX_CLK` div_a must be between 1 and 511 (inclusive)."
                );
                ::core::assert!(
                    div_b <= 511,
                    "`I2S0_TX_CLK` div_b must be between 0 and 511 (inclusive)."
                );
                Self {
                    sclk,
                    div_num,
                    div_a,
                    div_b,
                }
            }
            pub fn sclk(self) -> I2sClkSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
            pub fn div_a(self) -> u32 {
                self.div_a as u32
            }
            pub fn div_b(self) -> u32 {
                self.div_b as u32
            }
        }
        /// The list of clock signals that the `I2S0_MCLK_OUT` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum I2sMclkOutConfig {
            /// Selects `TX_CLK`.
            Tx,
            #[default]
            /// Selects `RX_CLK`.
            Rx,
        }
        /// The list of clock signals that the `SPI2_FUNCTION_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum SpiFunctionClockConfig {
            /// Selects `XTAL_CLK`.
            Xtal,
            #[default]
            /// Selects `PLL_F160M`.
            PllF160m,
            /// Selects `RC_FAST_CLK`.
            RcFast,
        }
        /// The list of clock signals that the `TIMG0_FUNCTION_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgFunctionClockConfig {
            #[default]
            /// Selects `XTAL_CLK`.
            XtalClk,
            /// Selects `RC_FAST_CLK`.
            RcFastClk,
            /// Selects `PLL_F80M`.
            PllF80m,
        }
        /// The list of clock signals that the `TIMG0_WDT_CLOCK` multiplexer can output.
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum TimgWdtClockConfig {
            #[default]
            /// Selects `XTAL_CLK`.
            XtalClk,
            /// Selects `RC_FAST_CLK`.
            RcFastClk,
            /// Selects `PLL_F80M`.
            PllF80m,
        }
        #[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum UartFunctionClockSclk {
            #[default]
            /// Selects `XTAL_CLK`.
            Xtal,
            /// Selects `PLL_F80M`.
            PllF80m,
            /// Selects `RC_FAST_CLK`.
            RcFast,
        }
        /// Configures the `UART0_FUNCTION_CLOCK` clock node.
        ///
        /// The output is calculated as `OUTPUT = sclk / (div_num + 1)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct UartFunctionClockConfig {
            sclk: UartFunctionClockSclk,
            div_num: u32,
        }
        impl UartFunctionClockConfig {
            /// Creates a new configuration for the FUNCTION_CLOCK clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the div_num value is outside the
            /// valid range (0 ..= 255).
            pub const fn new(sclk: UartFunctionClockSclk, div_num: u32) -> Self {
                ::core::assert!(
                    div_num <= 255,
                    "`UART0_FUNCTION_CLOCK` div_num must be between 0 and 255 (inclusive)."
                );
                Self { sclk, div_num }
            }
            pub fn sclk(self) -> UartFunctionClockSclk {
                self.sclk
            }
            pub fn div_num(self) -> u32 {
                self.div_num as u32
            }
        }
        /// Configures the `UART0_BAUD_RATE_GENERATOR` clock node.
        ///
        /// The output is calculated as `OUTPUT = (FUNCTION_CLOCK * 16) / (integral * 16 +
        /// fractional)`.
        #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub struct UartBaudRateGeneratorConfig {
            fractional: u32,
            integral: u32,
        }
        impl UartBaudRateGeneratorConfig {
            /// Creates a new configuration for the BAUD_RATE_GENERATOR clock node.
            ///
            /// ## Panics
            ///
            /// Panics if the fractional value is outside the
            /// valid range (0 ..= 15).
            ///
            /// Panics if the integral value is outside the
            /// valid range (0 ..= 4095).
            pub const fn new(fractional: u32, integral: u32) -> Self {
                ::core::assert!(
                    fractional <= 15,
                    "`UART0_BAUD_RATE_GENERATOR` fractional must be between 0 and 15 (inclusive)."
                );
                ::core::assert!(
                    integral <= 4095,
                    "`UART0_BAUD_RATE_GENERATOR` integral must be between 0 and 4095 (inclusive)."
                );
                Self {
                    fractional,
                    integral,
                }
            }
            pub fn fractional(self) -> u32 {
                self.fractional as u32
            }
            pub fn integral(self) -> u32 {
                self.integral as u32
            }
        }
        /// Represents the device's clock tree.
        pub struct ClockTree {
            xtal_clk: Option<XtalClkConfig>,
            hp_root_clk: Option<HpRootClkConfig>,
            cpu_clk: Option<CpuClkConfig>,
            ahb_clk: Option<AhbClkConfig>,
            apb_clk: Option<ApbClkConfig>,
            lp_fast_clk: Option<LpFastClkConfig>,
            lp_slow_clk: Option<LpSlowClkConfig>,
            ble_lp_clk: Option<BleLpClkConfig>,
            crypto_clk: Option<CryptoClkConfig>,
            timg_calibration_clock: Option<TimgCalibrationClockConfig>,
            adc_function_clock: [Option<AdcFunctionClockConfig>; 1],
            i2c_function_clock: [Option<I2cFunctionClockConfig>; 1],
            i2s_tx_clk: [Option<I2sClkConfig>; 1],
            i2s_rx_clk: [Option<I2sClkConfig>; 1],
            i2s_mclk_out: [Option<I2sMclkOutConfig>; 1],
            spi_function_clock: [Option<SpiFunctionClockConfig>; 1],
            timg_function_clock: [Option<TimgFunctionClockConfig>; 2],
            timg_wdt_clock: [Option<TimgWdtClockConfig>; 2],
            uart_function_clock: [Option<UartFunctionClockConfig>; 3],
            uart_baud_rate_generator: [Option<UartBaudRateGeneratorConfig>; 3],
            rc_fast_clk_refcount: u32,
            pll_clk_refcount: u32,
            #[cfg(use_xtal32k)]
            xtal32k_clk_refcount: u32,
            osc_slow_clk_refcount: u32,
            rc_slow_clk_refcount: u32,
            pll_f20m_refcount: u32,
            pll_f40m_refcount: u32,
            pll_f48m_refcount: u32,
            pll_f60m_refcount: u32,
            pll_f80m_refcount: u32,
            pll_f120m_refcount: u32,
            pll_f160m_refcount: u32,
            hp_root_clk_refcount: u32,
            cpu_clk_refcount: u32,
            apb_clk_refcount: u32,
            lp_fast_clk_refcount: u32,
            lp_slow_clk_refcount: u32,
            ble_lp_clk_refcount: u32,
            crypto_clk_refcount: u32,
            timg_calibration_clock_refcount: u32,
            adc_function_clock_refcount: [u32; 1],
            i2c_function_clock_refcount: [u32; 1],
            i2s_tx_clk_refcount: [u32; 1],
            i2s_rx_clk_refcount: [u32; 1],
            i2s_mclk_out_refcount: [u32; 1],
            spi_function_clock_refcount: [u32; 1],
            timg_function_clock_refcount: [u32; 2],
            timg_wdt_clock_refcount: [u32; 2],
            uart_function_clock_refcount: [u32; 3],
            uart_baud_rate_generator_refcount: [u32; 3],
        }
        impl ClockTree {
            /// Locks the clock tree for exclusive access.
            pub fn with<R>(f: impl FnOnce(&mut ClockTree) -> R) -> R {
                CLOCK_TREE.with(f)
            }
            /// Returns the current configuration of the XTAL_CLK clock tree node
            pub fn xtal_clk(&self) -> Option<XtalClkConfig> {
                self.xtal_clk
            }
            /// Returns the current configuration of the HP_ROOT_CLK clock tree node
            pub fn hp_root_clk(&self) -> Option<HpRootClkConfig> {
                self.hp_root_clk
            }
            /// Returns the current configuration of the CPU_CLK clock tree node
            pub fn cpu_clk(&self) -> Option<CpuClkConfig> {
                self.cpu_clk
            }
            /// Returns the current configuration of the AHB_CLK clock tree node
            pub fn ahb_clk(&self) -> Option<AhbClkConfig> {
                self.ahb_clk
            }
            /// Returns the current configuration of the APB_CLK clock tree node
            pub fn apb_clk(&self) -> Option<ApbClkConfig> {
                self.apb_clk
            }
            /// Returns the current configuration of the LP_FAST_CLK clock tree node
            pub fn lp_fast_clk(&self) -> Option<LpFastClkConfig> {
                self.lp_fast_clk
            }
            /// Returns the current configuration of the LP_SLOW_CLK clock tree node
            pub fn lp_slow_clk(&self) -> Option<LpSlowClkConfig> {
                self.lp_slow_clk
            }
            /// Returns the current configuration of the BLE_LP_CLK clock tree node
            pub fn ble_lp_clk(&self) -> Option<BleLpClkConfig> {
                self.ble_lp_clk
            }
            /// Returns the current configuration of the CRYPTO_CLK clock tree node
            pub fn crypto_clk(&self) -> Option<CryptoClkConfig> {
                self.crypto_clk
            }
            /// Returns the current configuration of the TIMG_CALIBRATION_CLOCK clock tree node
            pub fn timg_calibration_clock(&self) -> Option<TimgCalibrationClockConfig> {
                self.timg_calibration_clock
            }
            /// Returns the current configuration of the APB_SARADC_FUNCTION_CLOCK clock tree node
            pub fn apb_saradc_function_clock(&self) -> Option<AdcFunctionClockConfig> {
                self.adc_function_clock[AdcInstance::ApbSaradc as usize]
            }
            /// Returns the current configuration of the I2C0_FUNCTION_CLOCK clock tree node
            pub fn i2c0_function_clock(&self) -> Option<I2cFunctionClockConfig> {
                self.i2c_function_clock[I2cInstance::I2c0 as usize]
            }
            /// Returns the current configuration of the I2S0_TX_CLK clock tree node
            pub fn i2s0_tx_clk(&self) -> Option<I2sClkConfig> {
                self.i2s_tx_clk[I2sInstance::I2s0 as usize]
            }
            /// Returns the current configuration of the I2S0_RX_CLK clock tree node
            pub fn i2s0_rx_clk(&self) -> Option<I2sClkConfig> {
                self.i2s_rx_clk[I2sInstance::I2s0 as usize]
            }
            /// Returns the current configuration of the I2S0_MCLK_OUT clock tree node
            pub fn i2s0_mclk_out(&self) -> Option<I2sMclkOutConfig> {
                self.i2s_mclk_out[I2sInstance::I2s0 as usize]
            }
            /// Returns the current configuration of the SPI2_FUNCTION_CLOCK clock tree node
            pub fn spi2_function_clock(&self) -> Option<SpiFunctionClockConfig> {
                self.spi_function_clock[SpiInstance::Spi2 as usize]
            }
            /// Returns the current configuration of the TIMG0_FUNCTION_CLOCK clock tree node
            pub fn timg0_function_clock(&self) -> Option<TimgFunctionClockConfig> {
                self.timg_function_clock[TimgInstance::Timg0 as usize]
            }
            /// Returns the current configuration of the TIMG0_WDT_CLOCK clock tree node
            pub fn timg0_wdt_clock(&self) -> Option<TimgWdtClockConfig> {
                self.timg_wdt_clock[TimgInstance::Timg0 as usize]
            }
            /// Returns the current configuration of the TIMG1_FUNCTION_CLOCK clock tree node
            pub fn timg1_function_clock(&self) -> Option<TimgFunctionClockConfig> {
                self.timg_function_clock[TimgInstance::Timg1 as usize]
            }
            /// Returns the current configuration of the TIMG1_WDT_CLOCK clock tree node
            pub fn timg1_wdt_clock(&self) -> Option<TimgWdtClockConfig> {
                self.timg_wdt_clock[TimgInstance::Timg1 as usize]
            }
            /// Returns the current configuration of the UART0_FUNCTION_CLOCK clock tree node
            pub fn uart0_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart0 as usize]
            }
            /// Returns the current configuration of the UART0_BAUD_RATE_GENERATOR clock tree node
            pub fn uart0_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart0 as usize]
            }
            /// Returns the current configuration of the UART1_FUNCTION_CLOCK clock tree node
            pub fn uart1_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart1 as usize]
            }
            /// Returns the current configuration of the UART1_BAUD_RATE_GENERATOR clock tree node
            pub fn uart1_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart1 as usize]
            }
            /// Returns the current configuration of the UART2_FUNCTION_CLOCK clock tree node
            pub fn uart2_function_clock(&self) -> Option<UartFunctionClockConfig> {
                self.uart_function_clock[UartInstance::Uart2 as usize]
            }
            /// Returns the current configuration of the UART2_BAUD_RATE_GENERATOR clock tree node
            pub fn uart2_baud_rate_generator(&self) -> Option<UartBaudRateGeneratorConfig> {
                self.uart_baud_rate_generator[UartInstance::Uart2 as usize]
            }
        }
        static CLOCK_TREE: ::esp_sync::NonReentrantMutex<ClockTree> =
            ::esp_sync::NonReentrantMutex::new(ClockTree {
                xtal_clk: None,
                hp_root_clk: None,
                cpu_clk: None,
                ahb_clk: None,
                apb_clk: None,
                lp_fast_clk: None,
                lp_slow_clk: None,
                ble_lp_clk: None,
                crypto_clk: None,
                timg_calibration_clock: None,
                adc_function_clock: [None; 1],
                i2c_function_clock: [None; 1],
                i2s_tx_clk: [None; 1],
                i2s_rx_clk: [None; 1],
                i2s_mclk_out: [None; 1],
                spi_function_clock: [None; 1],
                timg_function_clock: [None; 2],
                timg_wdt_clock: [None; 2],
                uart_function_clock: [None; 3],
                uart_baud_rate_generator: [None; 3],
                rc_fast_clk_refcount: 0,
                pll_clk_refcount: 0,
                #[cfg(use_xtal32k)]
                xtal32k_clk_refcount: 0,
                osc_slow_clk_refcount: 0,
                rc_slow_clk_refcount: 0,
                pll_f20m_refcount: 0,
                pll_f40m_refcount: 0,
                pll_f48m_refcount: 0,
                pll_f60m_refcount: 0,
                pll_f80m_refcount: 0,
                pll_f120m_refcount: 0,
                pll_f160m_refcount: 0,
                hp_root_clk_refcount: 0,
                cpu_clk_refcount: 0,
                apb_clk_refcount: 0,
                lp_fast_clk_refcount: 0,
                lp_slow_clk_refcount: 0,
                ble_lp_clk_refcount: 0,
                crypto_clk_refcount: 0,
                timg_calibration_clock_refcount: 0,
                adc_function_clock_refcount: [0; 1],
                i2c_function_clock_refcount: [0; 1],
                i2s_tx_clk_refcount: [0; 1],
                i2s_rx_clk_refcount: [0; 1],
                i2s_mclk_out_refcount: [0; 1],
                spi_function_clock_refcount: [0; 1],
                timg_function_clock_refcount: [0; 2],
                timg_wdt_clock_refcount: [0; 2],
                uart_function_clock_refcount: [0; 3],
                uart_baud_rate_generator_refcount: [0; 3],
            });
        static XTAL_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static HP_ROOT_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static CPU_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static AHB_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static APB_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static LP_FAST_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static LP_SLOW_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static BLE_LP_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static CRYPTO_CLK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static TIMG_CALIBRATION_CLOCK_FREQ_CACHE: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(0);
        static ADC_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static I2C_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static I2S_TX_CLK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static I2S_RX_CLK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static I2S_MCLK_OUT_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static SPI_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 1] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 1];
        static TIMG_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 2];
        static TIMG_WDT_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 2] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 2];
        static UART_FUNCTION_CLOCK_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 3] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 3];
        static UART_BAUD_RATE_GENERATOR_FREQ_CACHE: [::core::sync::atomic::AtomicU32; 3] =
            [const { ::core::sync::atomic::AtomicU32::new(0) }; 3];
        /// The clock sources of the device.
        ///
        /// A clock source is a node of the clock tree that other nodes derive their output
        /// from. Ask a node which source it runs on with its `..._root_source` function.
        #[derive(Debug, enumset::EnumSetType)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum ClockSource {
            /// `XTAL_CLK`.
            XtalClk,
            /// `RC_FAST_CLK`.
            RcFastClk,
            #[cfg(use_xtal32k)]
            /// `XTAL32K_CLK`.
            Xtal32kClk,
            /// `OSC_SLOW_CLK`.
            OscSlowClk,
            /// `RC_SLOW_CLK`.
            RcSlowClk,
        }
        /// Returns the clock source that `XTAL_CLK` currently runs on.
        pub fn xtal_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::XtalClk)
        }
        /// Returns the clock source that `RC_FAST_CLK` currently runs on.
        pub fn rc_fast_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::RcFastClk)
        }
        /// Returns the clock source that `PLL_CLK` currently runs on.
        pub fn pll_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        #[cfg(use_xtal32k)]
        /// Returns the clock source that `XTAL32K_CLK` currently runs on.
        pub fn xtal32k_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::Xtal32kClk)
        }
        /// Returns the clock source that `OSC_SLOW_CLK` currently runs on.
        pub fn osc_slow_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::OscSlowClk)
        }
        /// Returns the clock source that `RC_SLOW_CLK` currently runs on.
        pub fn rc_slow_clk_root_source(_clocks: &mut ClockTree) -> Option<ClockSource> {
            Some(ClockSource::RcSlowClk)
        }
        /// Returns the clock source that `PLL_F20M` currently runs on.
        pub fn pll_f20m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            pll_clk_root_source(clocks)
        }
        /// Returns the clock source that `PLL_F40M` currently runs on.
        pub fn pll_f40m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            pll_clk_root_source(clocks)
        }
        /// Returns the clock source that `PLL_F48M` currently runs on.
        pub fn pll_f48m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            pll_clk_root_source(clocks)
        }
        /// Returns the clock source that `PLL_F60M` currently runs on.
        pub fn pll_f60m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            pll_clk_root_source(clocks)
        }
        /// Returns the clock source that `PLL_F80M` currently runs on.
        pub fn pll_f80m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            pll_clk_root_source(clocks)
        }
        /// Returns the clock source that `PLL_F120M` currently runs on.
        pub fn pll_f120m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            pll_clk_root_source(clocks)
        }
        /// Returns the clock source that `PLL_F160M` currently runs on.
        pub fn pll_f160m_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            pll_clk_root_source(clocks)
        }
        /// Returns the clock source that `HP_ROOT_CLK` currently runs on.
        pub fn hp_root_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.hp_root_clk?;
            match config {
                HpRootClkConfig::Xtal => xtal_clk_root_source(clocks),
                HpRootClkConfig::RcFast => rc_fast_clk_root_source(clocks),
                HpRootClkConfig::PllF160m => pll_f160m_root_source(clocks),
            }
        }
        /// Returns the clock source that `CPU_CLK` currently runs on.
        pub fn cpu_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            hp_root_clk_root_source(clocks)
        }
        /// Returns the clock source that `AHB_CLK` currently runs on.
        pub fn ahb_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            hp_root_clk_root_source(clocks)
        }
        /// Returns the clock source that `APB_CLK` currently runs on.
        pub fn apb_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            ahb_clk_root_source(clocks)
        }
        /// Returns the clock source that `XTAL_D2_CLK` currently runs on.
        pub fn xtal_d2_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `LP_FAST_CLK` currently runs on.
        pub fn lp_fast_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.lp_fast_clk?;
            match config {
                LpFastClkConfig::RcFast => rc_fast_clk_root_source(clocks),
                LpFastClkConfig::XtalD2 => xtal_d2_clk_root_source(clocks),
                LpFastClkConfig::Xtal => xtal_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `LP_SLOW_CLK` currently runs on.
        pub fn lp_slow_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.lp_slow_clk?;
            match config {
                LpSlowClkConfig::RcSlow => rc_slow_clk_root_source(clocks),
                #[cfg(use_xtal32k)]
                LpSlowClkConfig::Xtal32k => xtal32k_clk_root_source(clocks),
                LpSlowClkConfig::OscSlow => osc_slow_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `BLE_LP_XTAL_CLK` currently runs on.
        pub fn ble_lp_xtal_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            xtal_clk_root_source(clocks)
        }
        /// Returns the clock source that `BLE_LP_RC_SLOW_CLK` currently runs on.
        pub fn ble_lp_rc_slow_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            rc_slow_clk_root_source(clocks)
        }
        /// Returns the clock source that `BLE_LP_CLK` currently runs on.
        pub fn ble_lp_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.ble_lp_clk?;
            match config {
                BleLpClkConfig::Xtal => ble_lp_xtal_clk_root_source(clocks),
                BleLpClkConfig::RcSlow => ble_lp_rc_slow_clk_root_source(clocks),
                #[cfg(use_xtal32k)]
                BleLpClkConfig::Xtal32k => xtal32k_clk_root_source(clocks),
            }
        }
        /// Returns the clock source that `CRYPTO_PLL_DIV` currently runs on.
        pub fn crypto_pll_div_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            pll_clk_root_source(clocks)
        }
        /// Returns the clock source that `CRYPTO_CLK` currently runs on.
        pub fn crypto_clk_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.crypto_clk?;
            match config {
                CryptoClkConfig::Xtal => xtal_clk_root_source(clocks),
                CryptoClkConfig::RcFast => rc_fast_clk_root_source(clocks),
                CryptoClkConfig::PllF480m => crypto_pll_div_root_source(clocks),
            }
        }
        /// Returns the clock source that `TIMG_CALIBRATION_CLOCK` currently runs on.
        pub fn timg_calibration_clock_root_source(clocks: &mut ClockTree) -> Option<ClockSource> {
            let config = clocks.timg_calibration_clock?;
            match config {
                TimgCalibrationClockConfig::OscSlowClk => osc_slow_clk_root_source(clocks),
                TimgCalibrationClockConfig::RcSlowClk => rc_slow_clk_root_source(clocks),
                TimgCalibrationClockConfig::RcFastDivClk => rc_fast_clk_root_source(clocks),
                #[cfg(use_xtal32k)]
                TimgCalibrationClockConfig::Xtal32kClk => xtal32k_clk_root_source(clocks),
            }
        }
        pub fn configure_xtal_clk(clocks: &mut ClockTree, config: XtalClkConfig) {
            let old_config = clocks.xtal_clk.replace(config);
            refresh_xtal_clk_downstream(clocks);
            configure_xtal_clk_impl(clocks, old_config, config);
        }
        pub fn xtal_clk_config(clocks: &mut ClockTree) -> Option<XtalClkConfig> {
            clocks.xtal_clk
        }
        fn request_xtal_clk(_clocks: &mut ClockTree) {}
        fn release_xtal_clk(_clocks: &mut ClockTree) {}
        pub fn xtal_clk_config_frequency(config: XtalClkConfig) -> u32 {
            config.value()
        }
        pub fn xtal_clk_frequency() -> u32 {
            XTAL_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn request_rc_fast_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC_FAST_CLK");
            if increment_reference_count(&mut clocks.rc_fast_clk_refcount) {
                trace!("Enabling RC_FAST_CLK");
                enable_rc_fast_clk_impl(clocks, true);
            }
        }
        pub fn release_rc_fast_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC_FAST_CLK");
            if decrement_reference_count(&mut clocks.rc_fast_clk_refcount) {
                trace!("Disabling RC_FAST_CLK");
                enable_rc_fast_clk_impl(clocks, false);
            }
        }
        static RC_FAST_CLK_FREQUENCY: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(rc_fast_clk_nominal_frequency());
        pub const fn rc_fast_clk_nominal_frequency() -> u32 {
            17500000
        }
        pub fn rc_fast_clk_frequency() -> u32 {
            RC_FAST_CLK_FREQUENCY.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn set_rc_fast_clk_frequency(clocks: &mut ClockTree, frequency: u32) {
            if !(8750000..=26250000).contains(&frequency) {
                warn!(
                    "Ignoring out-of-range RC_FAST_CLK frequency: {} Hz",
                    frequency
                );
                return;
            }
            debug!(
                "Updating RC_FAST_CLK frequency to {} Hz (nominal {} Hz)",
                frequency,
                rc_fast_clk_nominal_frequency()
            );
            RC_FAST_CLK_FREQUENCY.store(frequency, ::core::sync::atomic::Ordering::Release);
            refresh_rc_fast_clk_downstream(clocks);
        }
        pub fn request_pll_clk(clocks: &mut ClockTree) {
            trace!("Requesting PLL_CLK");
            if increment_reference_count(&mut clocks.pll_clk_refcount) {
                trace!("Enabling PLL_CLK");
                request_xtal_clk(clocks);
                enable_pll_clk_impl(clocks, true);
            }
        }
        pub fn release_pll_clk(clocks: &mut ClockTree) {
            trace!("Releasing PLL_CLK");
            if decrement_reference_count(&mut clocks.pll_clk_refcount) {
                trace!("Disabling PLL_CLK");
                enable_pll_clk_impl(clocks, false);
                release_xtal_clk(clocks);
            }
        }
        pub fn pll_clk_frequency() -> u32 {
            480000000
        }
        pub fn pll_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        #[cfg(use_xtal32k)]
        pub fn request_xtal32k_clk(clocks: &mut ClockTree) {
            trace!("Requesting XTAL32K_CLK");
            if increment_reference_count(&mut clocks.xtal32k_clk_refcount) {
                trace!("Enabling XTAL32K_CLK");
                enable_xtal32k_clk_impl(clocks, true);
            }
        }
        #[cfg(use_xtal32k)]
        pub fn release_xtal32k_clk(clocks: &mut ClockTree) {
            trace!("Releasing XTAL32K_CLK");
            if decrement_reference_count(&mut clocks.xtal32k_clk_refcount) {
                trace!("Disabling XTAL32K_CLK");
                enable_xtal32k_clk_impl(clocks, false);
            }
        }
        #[cfg(use_xtal32k)]
        pub fn xtal32k_clk_frequency() -> u32 {
            32768
        }
        pub fn request_osc_slow_clk(clocks: &mut ClockTree) {
            trace!("Requesting OSC_SLOW_CLK");
            if increment_reference_count(&mut clocks.osc_slow_clk_refcount) {
                trace!("Enabling OSC_SLOW_CLK");
                enable_osc_slow_clk_impl(clocks, true);
            }
        }
        pub fn release_osc_slow_clk(clocks: &mut ClockTree) {
            trace!("Releasing OSC_SLOW_CLK");
            if decrement_reference_count(&mut clocks.osc_slow_clk_refcount) {
                trace!("Disabling OSC_SLOW_CLK");
                enable_osc_slow_clk_impl(clocks, false);
            }
        }
        pub fn osc_slow_clk_frequency() -> u32 {
            32768
        }
        pub fn request_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Requesting RC_SLOW_CLK");
            if increment_reference_count(&mut clocks.rc_slow_clk_refcount) {
                trace!("Enabling RC_SLOW_CLK");
                enable_rc_slow_clk_impl(clocks, true);
            }
        }
        pub fn release_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Releasing RC_SLOW_CLK");
            if decrement_reference_count(&mut clocks.rc_slow_clk_refcount) {
                trace!("Disabling RC_SLOW_CLK");
                enable_rc_slow_clk_impl(clocks, false);
            }
        }
        static RC_SLOW_CLK_FREQUENCY: ::core::sync::atomic::AtomicU32 =
            ::core::sync::atomic::AtomicU32::new(rc_slow_clk_nominal_frequency());
        pub const fn rc_slow_clk_nominal_frequency() -> u32 {
            136000
        }
        pub fn rc_slow_clk_frequency() -> u32 {
            RC_SLOW_CLK_FREQUENCY.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn set_rc_slow_clk_frequency(clocks: &mut ClockTree, frequency: u32) {
            if !(68000..=204000).contains(&frequency) {
                warn!(
                    "Ignoring out-of-range RC_SLOW_CLK frequency: {} Hz",
                    frequency
                );
                return;
            }
            debug!(
                "Updating RC_SLOW_CLK frequency to {} Hz (nominal {} Hz)",
                frequency,
                rc_slow_clk_nominal_frequency()
            );
            RC_SLOW_CLK_FREQUENCY.store(frequency, ::core::sync::atomic::Ordering::Release);
            refresh_rc_slow_clk_downstream(clocks);
        }
        pub fn request_pll_f20m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_F20M");
            if increment_reference_count(&mut clocks.pll_f20m_refcount) {
                trace!("Enabling PLL_F20M");
                request_pll_clk(clocks);
                enable_pll_f20m_impl(clocks, true);
            }
        }
        pub fn release_pll_f20m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_F20M");
            if decrement_reference_count(&mut clocks.pll_f20m_refcount) {
                trace!("Disabling PLL_F20M");
                enable_pll_f20m_impl(clocks, false);
                release_pll_clk(clocks);
            }
        }
        pub fn pll_f20m_frequency() -> u32 {
            (pll_clk_frequency() / 24)
        }
        pub fn pll_f20m_source_frequency() -> u32 {
            pll_clk_frequency()
        }
        pub fn request_pll_f40m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_F40M");
            if increment_reference_count(&mut clocks.pll_f40m_refcount) {
                trace!("Enabling PLL_F40M");
                request_pll_clk(clocks);
                enable_pll_f40m_impl(clocks, true);
            }
        }
        pub fn release_pll_f40m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_F40M");
            if decrement_reference_count(&mut clocks.pll_f40m_refcount) {
                trace!("Disabling PLL_F40M");
                enable_pll_f40m_impl(clocks, false);
                release_pll_clk(clocks);
            }
        }
        pub fn pll_f40m_frequency() -> u32 {
            (pll_clk_frequency() / 12)
        }
        pub fn pll_f40m_source_frequency() -> u32 {
            pll_clk_frequency()
        }
        pub fn request_pll_f48m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_F48M");
            if increment_reference_count(&mut clocks.pll_f48m_refcount) {
                trace!("Enabling PLL_F48M");
                request_pll_clk(clocks);
                enable_pll_f48m_impl(clocks, true);
            }
        }
        pub fn release_pll_f48m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_F48M");
            if decrement_reference_count(&mut clocks.pll_f48m_refcount) {
                trace!("Disabling PLL_F48M");
                enable_pll_f48m_impl(clocks, false);
                release_pll_clk(clocks);
            }
        }
        pub fn pll_f48m_frequency() -> u32 {
            (pll_clk_frequency() / 10)
        }
        pub fn pll_f48m_source_frequency() -> u32 {
            pll_clk_frequency()
        }
        pub fn request_pll_f60m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_F60M");
            if increment_reference_count(&mut clocks.pll_f60m_refcount) {
                trace!("Enabling PLL_F60M");
                request_pll_clk(clocks);
                enable_pll_f60m_impl(clocks, true);
            }
        }
        pub fn release_pll_f60m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_F60M");
            if decrement_reference_count(&mut clocks.pll_f60m_refcount) {
                trace!("Disabling PLL_F60M");
                enable_pll_f60m_impl(clocks, false);
                release_pll_clk(clocks);
            }
        }
        pub fn pll_f60m_frequency() -> u32 {
            (pll_clk_frequency() / 8)
        }
        pub fn pll_f60m_source_frequency() -> u32 {
            pll_clk_frequency()
        }
        pub fn request_pll_f80m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_F80M");
            if increment_reference_count(&mut clocks.pll_f80m_refcount) {
                trace!("Enabling PLL_F80M");
                request_pll_clk(clocks);
                enable_pll_f80m_impl(clocks, true);
            }
        }
        pub fn release_pll_f80m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_F80M");
            if decrement_reference_count(&mut clocks.pll_f80m_refcount) {
                trace!("Disabling PLL_F80M");
                enable_pll_f80m_impl(clocks, false);
                release_pll_clk(clocks);
            }
        }
        pub fn pll_f80m_frequency() -> u32 {
            (pll_clk_frequency() / 6)
        }
        pub fn pll_f80m_source_frequency() -> u32 {
            pll_clk_frequency()
        }
        pub fn request_pll_f120m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_F120M");
            if increment_reference_count(&mut clocks.pll_f120m_refcount) {
                trace!("Enabling PLL_F120M");
                request_pll_clk(clocks);
                enable_pll_f120m_impl(clocks, true);
            }
        }
        pub fn release_pll_f120m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_F120M");
            if decrement_reference_count(&mut clocks.pll_f120m_refcount) {
                trace!("Disabling PLL_F120M");
                enable_pll_f120m_impl(clocks, false);
                release_pll_clk(clocks);
            }
        }
        pub fn pll_f120m_frequency() -> u32 {
            (pll_clk_frequency() / 4)
        }
        pub fn pll_f120m_source_frequency() -> u32 {
            pll_clk_frequency()
        }
        pub fn request_pll_f160m(clocks: &mut ClockTree) {
            trace!("Requesting PLL_F160M");
            if increment_reference_count(&mut clocks.pll_f160m_refcount) {
                trace!("Enabling PLL_F160M");
                request_pll_clk(clocks);
                enable_pll_f160m_impl(clocks, true);
            }
        }
        pub fn release_pll_f160m(clocks: &mut ClockTree) {
            trace!("Releasing PLL_F160M");
            if decrement_reference_count(&mut clocks.pll_f160m_refcount) {
                trace!("Disabling PLL_F160M");
                enable_pll_f160m_impl(clocks, false);
                release_pll_clk(clocks);
            }
        }
        pub fn pll_f160m_frequency() -> u32 {
            (pll_clk_frequency() / 3)
        }
        pub fn pll_f160m_source_frequency() -> u32 {
            pll_clk_frequency()
        }
        pub fn configure_hp_root_clk(clocks: &mut ClockTree, new_selector: HpRootClkConfig) {
            let old_selector = clocks.hp_root_clk.replace(new_selector);
            refresh_hp_root_clk_downstream(clocks);
            let active = clocks.hp_root_clk_refcount > 0;
            if active {
                match new_selector {
                    HpRootClkConfig::Xtal => request_xtal_clk(clocks),
                    HpRootClkConfig::RcFast => request_rc_fast_clk(clocks),
                    HpRootClkConfig::PllF160m => request_pll_f160m(clocks),
                }
            }
            configure_hp_root_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    HpRootClkConfig::Xtal => release_xtal_clk(clocks),
                    HpRootClkConfig::RcFast => release_rc_fast_clk(clocks),
                    HpRootClkConfig::PllF160m => release_pll_f160m(clocks),
                }
            }
        }
        pub fn hp_root_clk_config(clocks: &mut ClockTree) -> Option<HpRootClkConfig> {
            clocks.hp_root_clk
        }
        pub fn request_hp_root_clk(clocks: &mut ClockTree) {
            trace!("Requesting HP_ROOT_CLK");
            if increment_reference_count(&mut clocks.hp_root_clk_refcount) {
                trace!("Enabling HP_ROOT_CLK");
                match unwrap!(clocks.hp_root_clk) {
                    HpRootClkConfig::Xtal => request_xtal_clk(clocks),
                    HpRootClkConfig::RcFast => request_rc_fast_clk(clocks),
                    HpRootClkConfig::PllF160m => request_pll_f160m(clocks),
                }
                enable_hp_root_clk_impl(clocks, true);
            }
        }
        pub fn release_hp_root_clk(clocks: &mut ClockTree) {
            trace!("Releasing HP_ROOT_CLK");
            if decrement_reference_count(&mut clocks.hp_root_clk_refcount) {
                trace!("Disabling HP_ROOT_CLK");
                enable_hp_root_clk_impl(clocks, false);
                match unwrap!(clocks.hp_root_clk) {
                    HpRootClkConfig::Xtal => release_xtal_clk(clocks),
                    HpRootClkConfig::RcFast => release_rc_fast_clk(clocks),
                    HpRootClkConfig::PllF160m => release_pll_f160m(clocks),
                }
            }
        }
        pub fn hp_root_clk_config_frequency(config: HpRootClkConfig) -> u32 {
            match config {
                HpRootClkConfig::Xtal => xtal_clk_frequency(),
                HpRootClkConfig::RcFast => rc_fast_clk_frequency(),
                HpRootClkConfig::PllF160m => pll_f160m_frequency(),
            }
        }
        pub fn hp_root_clk_frequency() -> u32 {
            HP_ROOT_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn hp_root_clk_source_frequency(source: HpRootClkConfig) -> u32 {
            hp_root_clk_config_frequency(source)
        }
        pub fn configure_cpu_clk(clocks: &mut ClockTree, config: CpuClkConfig) {
            let old_config = clocks.cpu_clk.replace(config);
            refresh_cpu_clk_downstream(clocks);
            configure_cpu_clk_impl(clocks, old_config, config);
        }
        pub fn cpu_clk_config(clocks: &mut ClockTree) -> Option<CpuClkConfig> {
            clocks.cpu_clk
        }
        pub fn request_cpu_clk(clocks: &mut ClockTree) {
            trace!("Requesting CPU_CLK");
            if increment_reference_count(&mut clocks.cpu_clk_refcount) {
                trace!("Enabling CPU_CLK");
                request_hp_root_clk(clocks);
                enable_cpu_clk_impl(clocks, true);
            }
        }
        pub fn release_cpu_clk(clocks: &mut ClockTree) {
            trace!("Releasing CPU_CLK");
            if decrement_reference_count(&mut clocks.cpu_clk_refcount) {
                trace!("Disabling CPU_CLK");
                enable_cpu_clk_impl(clocks, false);
                release_hp_root_clk(clocks);
            }
        }
        pub fn cpu_clk_config_frequency(config: CpuClkConfig) -> u32 {
            (hp_root_clk_frequency() / (config.divisor() + 1))
        }
        pub fn cpu_clk_frequency() -> u32 {
            CPU_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn cpu_clk_source_frequency() -> u32 {
            hp_root_clk_frequency()
        }
        pub fn configure_ahb_clk(clocks: &mut ClockTree, config: AhbClkConfig) {
            let old_config = clocks.ahb_clk.replace(config);
            refresh_ahb_clk_downstream(clocks);
            configure_ahb_clk_impl(clocks, old_config, config);
        }
        pub fn ahb_clk_config(clocks: &mut ClockTree) -> Option<AhbClkConfig> {
            clocks.ahb_clk
        }
        pub fn request_ahb_clk(clocks: &mut ClockTree) {
            trace!("Enabling AHB_CLK");
            request_hp_root_clk(clocks);
            enable_ahb_clk_impl(clocks, true);
        }
        pub fn release_ahb_clk(clocks: &mut ClockTree) {
            trace!("Disabling AHB_CLK");
            enable_ahb_clk_impl(clocks, false);
            release_hp_root_clk(clocks);
        }
        pub fn ahb_clk_config_frequency(config: AhbClkConfig) -> u32 {
            (hp_root_clk_frequency() / (config.divisor() + 1))
        }
        pub fn ahb_clk_frequency() -> u32 {
            AHB_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn ahb_clk_source_frequency() -> u32 {
            hp_root_clk_frequency()
        }
        pub fn configure_apb_clk(clocks: &mut ClockTree, config: ApbClkConfig) {
            let old_config = clocks.apb_clk.replace(config);
            refresh_apb_clk_downstream(clocks);
            configure_apb_clk_impl(clocks, old_config, config);
        }
        pub fn apb_clk_config(clocks: &mut ClockTree) -> Option<ApbClkConfig> {
            clocks.apb_clk
        }
        pub fn request_apb_clk(clocks: &mut ClockTree) {
            trace!("Requesting APB_CLK");
            if increment_reference_count(&mut clocks.apb_clk_refcount) {
                trace!("Enabling APB_CLK");
                request_ahb_clk(clocks);
                enable_apb_clk_impl(clocks, true);
            }
        }
        pub fn release_apb_clk(clocks: &mut ClockTree) {
            trace!("Releasing APB_CLK");
            if decrement_reference_count(&mut clocks.apb_clk_refcount) {
                trace!("Disabling APB_CLK");
                enable_apb_clk_impl(clocks, false);
                release_ahb_clk(clocks);
            }
        }
        pub fn apb_clk_config_frequency(config: ApbClkConfig) -> u32 {
            (ahb_clk_frequency() / (config.divisor() + 1))
        }
        pub fn apb_clk_frequency() -> u32 {
            APB_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn apb_clk_source_frequency() -> u32 {
            ahb_clk_frequency()
        }
        pub fn request_xtal_d2_clk(clocks: &mut ClockTree) {
            trace!("Enabling XTAL_D2_CLK");
            request_xtal_clk(clocks);
            enable_xtal_d2_clk_impl(clocks, true);
        }
        pub fn release_xtal_d2_clk(clocks: &mut ClockTree) {
            trace!("Disabling XTAL_D2_CLK");
            enable_xtal_d2_clk_impl(clocks, false);
            release_xtal_clk(clocks);
        }
        pub fn xtal_d2_clk_frequency() -> u32 {
            (xtal_clk_frequency() / 2)
        }
        pub fn xtal_d2_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn configure_lp_fast_clk(clocks: &mut ClockTree, new_selector: LpFastClkConfig) {
            let old_selector = clocks.lp_fast_clk.replace(new_selector);
            refresh_lp_fast_clk_downstream(clocks);
            let active = clocks.lp_fast_clk_refcount > 0;
            if active {
                match new_selector {
                    LpFastClkConfig::RcFast => request_rc_fast_clk(clocks),
                    LpFastClkConfig::XtalD2 => request_xtal_d2_clk(clocks),
                    LpFastClkConfig::Xtal => request_xtal_clk(clocks),
                }
            }
            configure_lp_fast_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    LpFastClkConfig::RcFast => release_rc_fast_clk(clocks),
                    LpFastClkConfig::XtalD2 => release_xtal_d2_clk(clocks),
                    LpFastClkConfig::Xtal => release_xtal_clk(clocks),
                }
            }
        }
        pub fn lp_fast_clk_config(clocks: &mut ClockTree) -> Option<LpFastClkConfig> {
            clocks.lp_fast_clk
        }
        pub fn request_lp_fast_clk(clocks: &mut ClockTree) {
            trace!("Requesting LP_FAST_CLK");
            if increment_reference_count(&mut clocks.lp_fast_clk_refcount) {
                trace!("Enabling LP_FAST_CLK");
                match unwrap!(clocks.lp_fast_clk) {
                    LpFastClkConfig::RcFast => request_rc_fast_clk(clocks),
                    LpFastClkConfig::XtalD2 => request_xtal_d2_clk(clocks),
                    LpFastClkConfig::Xtal => request_xtal_clk(clocks),
                }
                enable_lp_fast_clk_impl(clocks, true);
            }
        }
        pub fn release_lp_fast_clk(clocks: &mut ClockTree) {
            trace!("Releasing LP_FAST_CLK");
            if decrement_reference_count(&mut clocks.lp_fast_clk_refcount) {
                trace!("Disabling LP_FAST_CLK");
                enable_lp_fast_clk_impl(clocks, false);
                match unwrap!(clocks.lp_fast_clk) {
                    LpFastClkConfig::RcFast => release_rc_fast_clk(clocks),
                    LpFastClkConfig::XtalD2 => release_xtal_d2_clk(clocks),
                    LpFastClkConfig::Xtal => release_xtal_clk(clocks),
                }
            }
        }
        pub fn lp_fast_clk_config_frequency(config: LpFastClkConfig) -> u32 {
            match config {
                LpFastClkConfig::RcFast => rc_fast_clk_frequency(),
                LpFastClkConfig::XtalD2 => xtal_d2_clk_frequency(),
                LpFastClkConfig::Xtal => xtal_clk_frequency(),
            }
        }
        pub fn lp_fast_clk_frequency() -> u32 {
            LP_FAST_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn lp_fast_clk_source_frequency(source: LpFastClkConfig) -> u32 {
            lp_fast_clk_config_frequency(source)
        }
        pub fn configure_lp_slow_clk(clocks: &mut ClockTree, new_selector: LpSlowClkConfig) {
            let old_selector = clocks.lp_slow_clk.replace(new_selector);
            refresh_lp_slow_clk_downstream(clocks);
            let active = clocks.lp_slow_clk_refcount > 0;
            if active {
                match new_selector {
                    LpSlowClkConfig::RcSlow => request_rc_slow_clk(clocks),
                    #[cfg(use_xtal32k)]
                    LpSlowClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                    LpSlowClkConfig::OscSlow => request_osc_slow_clk(clocks),
                }
            }
            configure_lp_slow_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    LpSlowClkConfig::RcSlow => release_rc_slow_clk(clocks),
                    #[cfg(use_xtal32k)]
                    LpSlowClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                    LpSlowClkConfig::OscSlow => release_osc_slow_clk(clocks),
                }
            }
        }
        pub fn lp_slow_clk_config(clocks: &mut ClockTree) -> Option<LpSlowClkConfig> {
            clocks.lp_slow_clk
        }
        pub fn request_lp_slow_clk(clocks: &mut ClockTree) {
            trace!("Requesting LP_SLOW_CLK");
            if increment_reference_count(&mut clocks.lp_slow_clk_refcount) {
                trace!("Enabling LP_SLOW_CLK");
                match unwrap!(clocks.lp_slow_clk) {
                    LpSlowClkConfig::RcSlow => request_rc_slow_clk(clocks),
                    #[cfg(use_xtal32k)]
                    LpSlowClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                    LpSlowClkConfig::OscSlow => request_osc_slow_clk(clocks),
                }
                enable_lp_slow_clk_impl(clocks, true);
            }
        }
        pub fn release_lp_slow_clk(clocks: &mut ClockTree) {
            trace!("Releasing LP_SLOW_CLK");
            if decrement_reference_count(&mut clocks.lp_slow_clk_refcount) {
                trace!("Disabling LP_SLOW_CLK");
                enable_lp_slow_clk_impl(clocks, false);
                match unwrap!(clocks.lp_slow_clk) {
                    LpSlowClkConfig::RcSlow => release_rc_slow_clk(clocks),
                    #[cfg(use_xtal32k)]
                    LpSlowClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                    LpSlowClkConfig::OscSlow => release_osc_slow_clk(clocks),
                }
            }
        }
        pub fn lp_slow_clk_config_frequency(config: LpSlowClkConfig) -> u32 {
            match config {
                LpSlowClkConfig::RcSlow => rc_slow_clk_frequency(),
                #[cfg(use_xtal32k)]
                LpSlowClkConfig::Xtal32k => xtal32k_clk_frequency(),
                LpSlowClkConfig::OscSlow => osc_slow_clk_frequency(),
            }
        }
        pub fn lp_slow_clk_frequency() -> u32 {
            LP_SLOW_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn lp_slow_clk_source_frequency(source: LpSlowClkConfig) -> u32 {
            lp_slow_clk_config_frequency(source)
        }
        pub fn request_ble_lp_xtal_clk(clocks: &mut ClockTree) {
            trace!("Enabling BLE_LP_XTAL_CLK");
            request_xtal_clk(clocks);
            enable_ble_lp_xtal_clk_impl(clocks, true);
        }
        pub fn release_ble_lp_xtal_clk(clocks: &mut ClockTree) {
            trace!("Disabling BLE_LP_XTAL_CLK");
            enable_ble_lp_xtal_clk_impl(clocks, false);
            release_xtal_clk(clocks);
        }
        pub fn ble_lp_xtal_clk_frequency() -> u32 {
            100000
        }
        pub fn ble_lp_xtal_clk_source_frequency() -> u32 {
            xtal_clk_frequency()
        }
        pub fn request_ble_lp_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Enabling BLE_LP_RC_SLOW_CLK");
            request_rc_slow_clk(clocks);
            enable_ble_lp_rc_slow_clk_impl(clocks, true);
        }
        pub fn release_ble_lp_rc_slow_clk(clocks: &mut ClockTree) {
            trace!("Disabling BLE_LP_RC_SLOW_CLK");
            enable_ble_lp_rc_slow_clk_impl(clocks, false);
            release_rc_slow_clk(clocks);
        }
        pub fn ble_lp_rc_slow_clk_frequency() -> u32 {
            (rc_slow_clk_frequency() / 5)
        }
        pub fn ble_lp_rc_slow_clk_source_frequency() -> u32 {
            rc_slow_clk_frequency()
        }
        pub fn configure_ble_lp_clk(clocks: &mut ClockTree, new_selector: BleLpClkConfig) {
            let old_selector = clocks.ble_lp_clk.replace(new_selector);
            refresh_ble_lp_clk_downstream(clocks);
            let active = clocks.ble_lp_clk_refcount > 0;
            if active {
                match new_selector {
                    BleLpClkConfig::Xtal => request_ble_lp_xtal_clk(clocks),
                    BleLpClkConfig::RcSlow => request_ble_lp_rc_slow_clk(clocks),
                    #[cfg(use_xtal32k)]
                    BleLpClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                }
            }
            configure_ble_lp_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    BleLpClkConfig::Xtal => release_ble_lp_xtal_clk(clocks),
                    BleLpClkConfig::RcSlow => release_ble_lp_rc_slow_clk(clocks),
                    #[cfg(use_xtal32k)]
                    BleLpClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                }
            }
        }
        pub fn ble_lp_clk_config(clocks: &mut ClockTree) -> Option<BleLpClkConfig> {
            clocks.ble_lp_clk
        }
        pub fn request_ble_lp_clk(clocks: &mut ClockTree) {
            trace!("Requesting BLE_LP_CLK");
            if increment_reference_count(&mut clocks.ble_lp_clk_refcount) {
                trace!("Enabling BLE_LP_CLK");
                match unwrap!(clocks.ble_lp_clk) {
                    BleLpClkConfig::Xtal => request_ble_lp_xtal_clk(clocks),
                    BleLpClkConfig::RcSlow => request_ble_lp_rc_slow_clk(clocks),
                    #[cfg(use_xtal32k)]
                    BleLpClkConfig::Xtal32k => request_xtal32k_clk(clocks),
                }
                enable_ble_lp_clk_impl(clocks, true);
            }
        }
        pub fn release_ble_lp_clk(clocks: &mut ClockTree) {
            trace!("Releasing BLE_LP_CLK");
            if decrement_reference_count(&mut clocks.ble_lp_clk_refcount) {
                trace!("Disabling BLE_LP_CLK");
                enable_ble_lp_clk_impl(clocks, false);
                match unwrap!(clocks.ble_lp_clk) {
                    BleLpClkConfig::Xtal => release_ble_lp_xtal_clk(clocks),
                    BleLpClkConfig::RcSlow => release_ble_lp_rc_slow_clk(clocks),
                    #[cfg(use_xtal32k)]
                    BleLpClkConfig::Xtal32k => release_xtal32k_clk(clocks),
                }
            }
        }
        pub fn ble_lp_clk_config_frequency(config: BleLpClkConfig) -> u32 {
            match config {
                BleLpClkConfig::Xtal => ble_lp_xtal_clk_frequency(),
                BleLpClkConfig::RcSlow => ble_lp_rc_slow_clk_frequency(),
                #[cfg(use_xtal32k)]
                BleLpClkConfig::Xtal32k => xtal32k_clk_frequency(),
            }
        }
        pub fn ble_lp_clk_frequency() -> u32 {
            BLE_LP_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn ble_lp_clk_source_frequency(source: BleLpClkConfig) -> u32 {
            ble_lp_clk_config_frequency(source)
        }
        pub fn request_crypto_pll_div(clocks: &mut ClockTree) {
            trace!("Enabling CRYPTO_PLL_DIV");
            request_pll_clk(clocks);
            enable_crypto_pll_div_impl(clocks, true);
        }
        pub fn release_crypto_pll_div(clocks: &mut ClockTree) {
            trace!("Disabling CRYPTO_PLL_DIV");
            enable_crypto_pll_div_impl(clocks, false);
            release_pll_clk(clocks);
        }
        pub fn crypto_pll_div_frequency() -> u32 {
            (pll_clk_frequency() / 3)
        }
        pub fn crypto_pll_div_source_frequency() -> u32 {
            pll_clk_frequency()
        }
        pub fn configure_crypto_clk(clocks: &mut ClockTree, new_selector: CryptoClkConfig) {
            let old_selector = clocks.crypto_clk.replace(new_selector);
            refresh_crypto_clk_downstream(clocks);
            let active = clocks.crypto_clk_refcount > 0;
            if active {
                match new_selector {
                    CryptoClkConfig::Xtal => request_xtal_clk(clocks),
                    CryptoClkConfig::RcFast => request_rc_fast_clk(clocks),
                    CryptoClkConfig::PllF480m => request_crypto_pll_div(clocks),
                }
            }
            configure_crypto_clk_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    CryptoClkConfig::Xtal => release_xtal_clk(clocks),
                    CryptoClkConfig::RcFast => release_rc_fast_clk(clocks),
                    CryptoClkConfig::PllF480m => release_crypto_pll_div(clocks),
                }
            }
        }
        pub fn crypto_clk_config(clocks: &mut ClockTree) -> Option<CryptoClkConfig> {
            clocks.crypto_clk
        }
        pub fn request_crypto_clk(clocks: &mut ClockTree) {
            trace!("Requesting CRYPTO_CLK");
            if increment_reference_count(&mut clocks.crypto_clk_refcount) {
                trace!("Enabling CRYPTO_CLK");
                match unwrap!(clocks.crypto_clk) {
                    CryptoClkConfig::Xtal => request_xtal_clk(clocks),
                    CryptoClkConfig::RcFast => request_rc_fast_clk(clocks),
                    CryptoClkConfig::PllF480m => request_crypto_pll_div(clocks),
                }
                enable_crypto_clk_impl(clocks, true);
            }
        }
        pub fn release_crypto_clk(clocks: &mut ClockTree) {
            trace!("Releasing CRYPTO_CLK");
            if decrement_reference_count(&mut clocks.crypto_clk_refcount) {
                trace!("Disabling CRYPTO_CLK");
                enable_crypto_clk_impl(clocks, false);
                match unwrap!(clocks.crypto_clk) {
                    CryptoClkConfig::Xtal => release_xtal_clk(clocks),
                    CryptoClkConfig::RcFast => release_rc_fast_clk(clocks),
                    CryptoClkConfig::PllF480m => release_crypto_pll_div(clocks),
                }
            }
        }
        pub fn crypto_clk_config_frequency(config: CryptoClkConfig) -> u32 {
            match config {
                CryptoClkConfig::Xtal => xtal_clk_frequency(),
                CryptoClkConfig::RcFast => rc_fast_clk_frequency(),
                CryptoClkConfig::PllF480m => crypto_pll_div_frequency(),
            }
        }
        pub fn crypto_clk_frequency() -> u32 {
            CRYPTO_CLK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn crypto_clk_source_frequency(source: CryptoClkConfig) -> u32 {
            crypto_clk_config_frequency(source)
        }
        pub fn configure_timg_calibration_clock(
            clocks: &mut ClockTree,
            new_selector: TimgCalibrationClockConfig,
        ) {
            let old_selector = clocks.timg_calibration_clock.replace(new_selector);
            refresh_timg_calibration_clock_downstream(clocks);
            let active = clocks.timg_calibration_clock_refcount > 0;
            if active {
                match new_selector {
                    TimgCalibrationClockConfig::OscSlowClk => request_osc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcSlowClk => request_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => request_rc_fast_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => request_xtal32k_clk(clocks),
                }
            }
            configure_timg_calibration_clock_impl(clocks, old_selector, new_selector);
            if active && let Some(old_selector) = old_selector {
                match old_selector {
                    TimgCalibrationClockConfig::OscSlowClk => release_osc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcSlowClk => release_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => release_rc_fast_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => release_xtal32k_clk(clocks),
                }
            }
        }
        pub fn timg_calibration_clock_config(
            clocks: &mut ClockTree,
        ) -> Option<TimgCalibrationClockConfig> {
            clocks.timg_calibration_clock
        }
        pub fn request_timg_calibration_clock(clocks: &mut ClockTree) {
            trace!("Requesting TIMG_CALIBRATION_CLOCK");
            if increment_reference_count(&mut clocks.timg_calibration_clock_refcount) {
                trace!("Enabling TIMG_CALIBRATION_CLOCK");
                crate::rtc_cntl::WakeLock::acquire();
                match unwrap!(clocks.timg_calibration_clock) {
                    TimgCalibrationClockConfig::OscSlowClk => request_osc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcSlowClk => request_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => request_rc_fast_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => request_xtal32k_clk(clocks),
                }
                enable_timg_calibration_clock_impl(clocks, true);
            }
        }
        pub fn release_timg_calibration_clock(clocks: &mut ClockTree) {
            trace!("Releasing TIMG_CALIBRATION_CLOCK");
            if decrement_reference_count(&mut clocks.timg_calibration_clock_refcount) {
                trace!("Disabling TIMG_CALIBRATION_CLOCK");
                crate::rtc_cntl::WakeLock::release();
                enable_timg_calibration_clock_impl(clocks, false);
                match unwrap!(clocks.timg_calibration_clock) {
                    TimgCalibrationClockConfig::OscSlowClk => release_osc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcSlowClk => release_rc_slow_clk(clocks),
                    TimgCalibrationClockConfig::RcFastDivClk => release_rc_fast_clk(clocks),
                    #[cfg(use_xtal32k)]
                    TimgCalibrationClockConfig::Xtal32kClk => release_xtal32k_clk(clocks),
                }
            }
        }
        pub fn timg_calibration_clock_config_frequency(config: TimgCalibrationClockConfig) -> u32 {
            match config {
                TimgCalibrationClockConfig::OscSlowClk => osc_slow_clk_frequency(),
                TimgCalibrationClockConfig::RcSlowClk => rc_slow_clk_frequency(),
                TimgCalibrationClockConfig::RcFastDivClk => rc_fast_clk_frequency(),
                #[cfg(use_xtal32k)]
                TimgCalibrationClockConfig::Xtal32kClk => xtal32k_clk_frequency(),
            }
        }
        pub fn timg_calibration_clock_frequency() -> u32 {
            TIMG_CALIBRATION_CLOCK_FREQ_CACHE.load(::core::sync::atomic::Ordering::Acquire)
        }
        pub fn timg_calibration_clock_source_frequency(source: TimgCalibrationClockConfig) -> u32 {
            timg_calibration_clock_config_frequency(source)
        }
        impl AdcInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                new_selector: AdcFunctionClockConfig,
            ) {
                let old_selector = clocks.adc_function_clock[self as usize].replace(new_selector);
                refresh_adc_function_clock_downstream(clocks, self);
                let active = clocks.adc_function_clock_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        AdcFunctionClockConfig::Xtal => request_xtal_clk(clocks),
                        AdcFunctionClockConfig::RcFast => request_rc_fast_clk(clocks),
                        AdcFunctionClockConfig::PllF80m => request_pll_f80m(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        AdcFunctionClockConfig::Xtal => release_xtal_clk(clocks),
                        AdcFunctionClockConfig::RcFast => release_rc_fast_clk(clocks),
                        AdcFunctionClockConfig::PllF80m => release_pll_f80m(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<AdcFunctionClockConfig> {
                clocks.adc_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(&mut clocks.adc_function_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.adc_function_clock[self as usize]) {
                        AdcFunctionClockConfig::Xtal => request_xtal_clk(clocks),
                        AdcFunctionClockConfig::RcFast => request_rc_fast_clk(clocks),
                        AdcFunctionClockConfig::PllF80m => request_pll_f80m(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(&mut clocks.adc_function_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.adc_function_clock[self as usize]) {
                        AdcFunctionClockConfig::Xtal => release_xtal_clk(clocks),
                        AdcFunctionClockConfig::RcFast => release_rc_fast_clk(clocks),
                        AdcFunctionClockConfig::PllF80m => release_pll_f80m(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: AdcFunctionClockConfig) -> u32 {
                match config {
                    AdcFunctionClockConfig::Xtal => xtal_clk_frequency(),
                    AdcFunctionClockConfig::RcFast => rc_fast_clk_frequency(),
                    AdcFunctionClockConfig::PllF80m => pll_f80m_frequency(),
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                ADC_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(source: AdcFunctionClockConfig) -> u32 {
                Self::function_clock_config_frequency(source)
            }
        }
        impl I2cInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                config: I2cFunctionClockConfig,
            ) {
                let old_config = clocks.i2c_function_clock[self as usize].replace(config);
                refresh_i2c_function_clock_downstream(clocks, self);
                let active = clocks.i2c_function_clock_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        I2cFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        I2cFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<I2cFunctionClockConfig> {
                clocks.i2c_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(&mut clocks.i2c_function_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.i2c_function_clock[self as usize]).sclk {
                        I2cFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(&mut clocks.i2c_function_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.i2c_function_clock[self as usize]).sclk {
                        I2cFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                        I2cFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: I2cFunctionClockConfig) -> u32 {
                (match config.sclk {
                    I2cFunctionClockSclk::Xtal => xtal_clk_frequency(),
                    I2cFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                } / (config.div_num() + 1))
            }
            pub fn function_clock_frequency(self) -> u32 {
                I2C_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(sclk: I2cFunctionClockSclk) -> u32 {
                match sclk {
                    I2cFunctionClockSclk::Xtal => xtal_clk_frequency(),
                    I2cFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                }
            }
        }
        impl I2sInstance {
            pub fn configure_tx_clk(self, clocks: &mut ClockTree, config: I2sClkConfig) {
                let old_config = clocks.i2s_tx_clk[self as usize].replace(config);
                refresh_i2s_tx_clk_downstream(clocks, self);
                let active = clocks.i2s_tx_clk_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        I2sClkSclk::Xtal => request_xtal_clk(clocks),
                        I2sClkSclk::PllF120m => request_pll_f120m(clocks),
                        I2sClkSclk::PllF160m => request_pll_f160m(clocks),
                    }
                }
                self.configure_tx_clk_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        I2sClkSclk::Xtal => release_xtal_clk(clocks),
                        I2sClkSclk::PllF120m => release_pll_f120m(clocks),
                        I2sClkSclk::PllF160m => release_pll_f160m(clocks),
                    }
                }
            }
            pub fn tx_clk_config(self, clocks: &mut ClockTree) -> Option<I2sClkConfig> {
                clocks.i2s_tx_clk[self as usize]
            }
            pub fn request_tx_clk(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::TX_CLK", self);
                if increment_reference_count(&mut clocks.i2s_tx_clk_refcount[self as usize]) {
                    trace!("Enabling {:?}::TX_CLK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.i2s_tx_clk[self as usize]).sclk {
                        I2sClkSclk::Xtal => request_xtal_clk(clocks),
                        I2sClkSclk::PllF120m => request_pll_f120m(clocks),
                        I2sClkSclk::PllF160m => request_pll_f160m(clocks),
                    }
                    self.enable_tx_clk_impl(clocks, true);
                }
            }
            pub fn release_tx_clk(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::TX_CLK", self);
                if decrement_reference_count(&mut clocks.i2s_tx_clk_refcount[self as usize]) {
                    trace!("Disabling {:?}::TX_CLK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_tx_clk_impl(clocks, false);
                    match unwrap!(clocks.i2s_tx_clk[self as usize]).sclk {
                        I2sClkSclk::Xtal => release_xtal_clk(clocks),
                        I2sClkSclk::PllF120m => release_pll_f120m(clocks),
                        I2sClkSclk::PllF160m => release_pll_f160m(clocks),
                    }
                }
            }
            pub fn tx_clk_config_frequency(config: I2sClkConfig) -> u32 {
                (((match config.sclk {
                    I2sClkSclk::Xtal => xtal_clk_frequency(),
                    I2sClkSclk::PllF120m => pll_f120m_frequency(),
                    I2sClkSclk::PllF160m => pll_f160m_frequency(),
                } as u64)
                    * (config.div_a() as u64))
                    / (((config.div_num() * config.div_a()) + config.div_b()) as u64))
                    as u32
            }
            pub fn tx_clk_frequency(self) -> u32 {
                I2S_TX_CLK_FREQ_CACHE[self as usize].load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn tx_clk_source_frequency(sclk: I2sClkSclk) -> u32 {
                match sclk {
                    I2sClkSclk::Xtal => xtal_clk_frequency(),
                    I2sClkSclk::PllF120m => pll_f120m_frequency(),
                    I2sClkSclk::PllF160m => pll_f160m_frequency(),
                }
            }
            pub fn configure_rx_clk(self, clocks: &mut ClockTree, config: I2sClkConfig) {
                let old_config = clocks.i2s_rx_clk[self as usize].replace(config);
                refresh_i2s_rx_clk_downstream(clocks, self);
                let active = clocks.i2s_rx_clk_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        I2sClkSclk::Xtal => request_xtal_clk(clocks),
                        I2sClkSclk::PllF120m => request_pll_f120m(clocks),
                        I2sClkSclk::PllF160m => request_pll_f160m(clocks),
                    }
                }
                self.configure_rx_clk_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        I2sClkSclk::Xtal => release_xtal_clk(clocks),
                        I2sClkSclk::PllF120m => release_pll_f120m(clocks),
                        I2sClkSclk::PllF160m => release_pll_f160m(clocks),
                    }
                }
            }
            pub fn rx_clk_config(self, clocks: &mut ClockTree) -> Option<I2sClkConfig> {
                clocks.i2s_rx_clk[self as usize]
            }
            pub fn request_rx_clk(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::RX_CLK", self);
                if increment_reference_count(&mut clocks.i2s_rx_clk_refcount[self as usize]) {
                    trace!("Enabling {:?}::RX_CLK", self);
                    crate::rtc_cntl::WakeLock::acquire();
                    match unwrap!(clocks.i2s_rx_clk[self as usize]).sclk {
                        I2sClkSclk::Xtal => request_xtal_clk(clocks),
                        I2sClkSclk::PllF120m => request_pll_f120m(clocks),
                        I2sClkSclk::PllF160m => request_pll_f160m(clocks),
                    }
                    self.enable_rx_clk_impl(clocks, true);
                }
            }
            pub fn release_rx_clk(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::RX_CLK", self);
                if decrement_reference_count(&mut clocks.i2s_rx_clk_refcount[self as usize]) {
                    trace!("Disabling {:?}::RX_CLK", self);
                    crate::rtc_cntl::WakeLock::release();
                    self.enable_rx_clk_impl(clocks, false);
                    match unwrap!(clocks.i2s_rx_clk[self as usize]).sclk {
                        I2sClkSclk::Xtal => release_xtal_clk(clocks),
                        I2sClkSclk::PllF120m => release_pll_f120m(clocks),
                        I2sClkSclk::PllF160m => release_pll_f160m(clocks),
                    }
                }
            }
            pub fn rx_clk_config_frequency(config: I2sClkConfig) -> u32 {
                (((match config.sclk {
                    I2sClkSclk::Xtal => xtal_clk_frequency(),
                    I2sClkSclk::PllF120m => pll_f120m_frequency(),
                    I2sClkSclk::PllF160m => pll_f160m_frequency(),
                } as u64)
                    * (config.div_a() as u64))
                    / (((config.div_num() * config.div_a()) + config.div_b()) as u64))
                    as u32
            }
            pub fn rx_clk_frequency(self) -> u32 {
                I2S_RX_CLK_FREQ_CACHE[self as usize].load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn rx_clk_source_frequency(sclk: I2sClkSclk) -> u32 {
                match sclk {
                    I2sClkSclk::Xtal => xtal_clk_frequency(),
                    I2sClkSclk::PllF120m => pll_f120m_frequency(),
                    I2sClkSclk::PllF160m => pll_f160m_frequency(),
                }
            }
            pub fn configure_mclk_out(
                self,
                clocks: &mut ClockTree,
                new_selector: I2sMclkOutConfig,
            ) {
                let old_selector = clocks.i2s_mclk_out[self as usize].replace(new_selector);
                refresh_i2s_mclk_out_downstream(clocks, self);
                let active = clocks.i2s_mclk_out_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        I2sMclkOutConfig::Tx => self.request_tx_clk(clocks),
                        I2sMclkOutConfig::Rx => self.request_rx_clk(clocks),
                    }
                }
                self.configure_mclk_out_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        I2sMclkOutConfig::Tx => self.release_tx_clk(clocks),
                        I2sMclkOutConfig::Rx => self.release_rx_clk(clocks),
                    }
                }
            }
            pub fn mclk_out_config(self, clocks: &mut ClockTree) -> Option<I2sMclkOutConfig> {
                clocks.i2s_mclk_out[self as usize]
            }
            pub fn request_mclk_out(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::MCLK_OUT", self);
                if increment_reference_count(&mut clocks.i2s_mclk_out_refcount[self as usize]) {
                    trace!("Enabling {:?}::MCLK_OUT", self);
                    match unwrap!(clocks.i2s_mclk_out[self as usize]) {
                        I2sMclkOutConfig::Tx => self.request_tx_clk(clocks),
                        I2sMclkOutConfig::Rx => self.request_rx_clk(clocks),
                    }
                    self.enable_mclk_out_impl(clocks, true);
                }
            }
            pub fn release_mclk_out(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::MCLK_OUT", self);
                if decrement_reference_count(&mut clocks.i2s_mclk_out_refcount[self as usize]) {
                    trace!("Disabling {:?}::MCLK_OUT", self);
                    self.enable_mclk_out_impl(clocks, false);
                    match unwrap!(clocks.i2s_mclk_out[self as usize]) {
                        I2sMclkOutConfig::Tx => self.release_tx_clk(clocks),
                        I2sMclkOutConfig::Rx => self.release_rx_clk(clocks),
                    }
                }
            }
            pub fn mclk_out_config_frequency(self, config: I2sMclkOutConfig) -> u32 {
                match config {
                    I2sMclkOutConfig::Tx => self.tx_clk_frequency(),
                    I2sMclkOutConfig::Rx => self.rx_clk_frequency(),
                }
            }
            pub fn mclk_out_frequency(self) -> u32 {
                I2S_MCLK_OUT_FREQ_CACHE[self as usize].load(::core::sync::atomic::Ordering::Acquire)
            }
        }
        impl SpiInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                new_selector: SpiFunctionClockConfig,
            ) {
                let old_selector = clocks.spi_function_clock[self as usize].replace(new_selector);
                refresh_spi_function_clock_downstream(clocks, self);
                let active = clocks.spi_function_clock_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        SpiFunctionClockConfig::Xtal => request_xtal_clk(clocks),
                        SpiFunctionClockConfig::PllF160m => request_pll_f160m(clocks),
                        SpiFunctionClockConfig::RcFast => request_rc_fast_clk(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        SpiFunctionClockConfig::Xtal => release_xtal_clk(clocks),
                        SpiFunctionClockConfig::PllF160m => release_pll_f160m(clocks),
                        SpiFunctionClockConfig::RcFast => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<SpiFunctionClockConfig> {
                clocks.spi_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(&mut clocks.spi_function_clock_refcount[self as usize])
                {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.spi_function_clock[self as usize]) {
                        SpiFunctionClockConfig::Xtal => request_xtal_clk(clocks),
                        SpiFunctionClockConfig::PllF160m => request_pll_f160m(clocks),
                        SpiFunctionClockConfig::RcFast => request_rc_fast_clk(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(&mut clocks.spi_function_clock_refcount[self as usize])
                {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.spi_function_clock[self as usize]) {
                        SpiFunctionClockConfig::Xtal => release_xtal_clk(clocks),
                        SpiFunctionClockConfig::PllF160m => release_pll_f160m(clocks),
                        SpiFunctionClockConfig::RcFast => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: SpiFunctionClockConfig) -> u32 {
                match config {
                    SpiFunctionClockConfig::Xtal => xtal_clk_frequency(),
                    SpiFunctionClockConfig::PllF160m => pll_f160m_frequency(),
                    SpiFunctionClockConfig::RcFast => rc_fast_clk_frequency(),
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                SPI_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(source: SpiFunctionClockConfig) -> u32 {
                Self::function_clock_config_frequency(source)
            }
        }
        impl TimgInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                new_selector: TimgFunctionClockConfig,
            ) {
                let old_selector = clocks.timg_function_clock[self as usize].replace(new_selector);
                refresh_timg_function_clock_downstream(clocks, self);
                let active = clocks.timg_function_clock_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        TimgFunctionClockConfig::XtalClk => request_xtal_clk(clocks),
                        TimgFunctionClockConfig::RcFastClk => request_rc_fast_clk(clocks),
                        TimgFunctionClockConfig::PllF80m => request_pll_f80m(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        TimgFunctionClockConfig::XtalClk => release_xtal_clk(clocks),
                        TimgFunctionClockConfig::RcFastClk => release_rc_fast_clk(clocks),
                        TimgFunctionClockConfig::PllF80m => release_pll_f80m(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<TimgFunctionClockConfig> {
                clocks.timg_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(
                    &mut clocks.timg_function_clock_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.timg_function_clock[self as usize]) {
                        TimgFunctionClockConfig::XtalClk => request_xtal_clk(clocks),
                        TimgFunctionClockConfig::RcFastClk => request_rc_fast_clk(clocks),
                        TimgFunctionClockConfig::PllF80m => request_pll_f80m(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(
                    &mut clocks.timg_function_clock_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.timg_function_clock[self as usize]) {
                        TimgFunctionClockConfig::XtalClk => release_xtal_clk(clocks),
                        TimgFunctionClockConfig::RcFastClk => release_rc_fast_clk(clocks),
                        TimgFunctionClockConfig::PllF80m => release_pll_f80m(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: TimgFunctionClockConfig) -> u32 {
                match config {
                    TimgFunctionClockConfig::XtalClk => xtal_clk_frequency(),
                    TimgFunctionClockConfig::RcFastClk => rc_fast_clk_frequency(),
                    TimgFunctionClockConfig::PllF80m => pll_f80m_frequency(),
                }
            }
            pub fn function_clock_frequency(self) -> u32 {
                TIMG_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(source: TimgFunctionClockConfig) -> u32 {
                Self::function_clock_config_frequency(source)
            }
            pub fn configure_wdt_clock(
                self,
                clocks: &mut ClockTree,
                new_selector: TimgWdtClockConfig,
            ) {
                let old_selector = clocks.timg_wdt_clock[self as usize].replace(new_selector);
                refresh_timg_wdt_clock_downstream(clocks, self);
                let active = clocks.timg_wdt_clock_refcount[self as usize] > 0;
                if active {
                    match new_selector {
                        TimgWdtClockConfig::XtalClk => request_xtal_clk(clocks),
                        TimgWdtClockConfig::RcFastClk => request_rc_fast_clk(clocks),
                        TimgWdtClockConfig::PllF80m => request_pll_f80m(clocks),
                    }
                }
                self.configure_wdt_clock_impl(clocks, old_selector, new_selector);
                if active && let Some(old_selector) = old_selector {
                    match old_selector {
                        TimgWdtClockConfig::XtalClk => release_xtal_clk(clocks),
                        TimgWdtClockConfig::RcFastClk => release_rc_fast_clk(clocks),
                        TimgWdtClockConfig::PllF80m => release_pll_f80m(clocks),
                    }
                }
            }
            pub fn wdt_clock_config(self, clocks: &mut ClockTree) -> Option<TimgWdtClockConfig> {
                clocks.timg_wdt_clock[self as usize]
            }
            pub fn request_wdt_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::WDT_CLOCK", self);
                if increment_reference_count(&mut clocks.timg_wdt_clock_refcount[self as usize]) {
                    trace!("Enabling {:?}::WDT_CLOCK", self);
                    match unwrap!(clocks.timg_wdt_clock[self as usize]) {
                        TimgWdtClockConfig::XtalClk => request_xtal_clk(clocks),
                        TimgWdtClockConfig::RcFastClk => request_rc_fast_clk(clocks),
                        TimgWdtClockConfig::PllF80m => request_pll_f80m(clocks),
                    }
                    self.enable_wdt_clock_impl(clocks, true);
                }
            }
            pub fn release_wdt_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::WDT_CLOCK", self);
                if decrement_reference_count(&mut clocks.timg_wdt_clock_refcount[self as usize]) {
                    trace!("Disabling {:?}::WDT_CLOCK", self);
                    self.enable_wdt_clock_impl(clocks, false);
                    match unwrap!(clocks.timg_wdt_clock[self as usize]) {
                        TimgWdtClockConfig::XtalClk => release_xtal_clk(clocks),
                        TimgWdtClockConfig::RcFastClk => release_rc_fast_clk(clocks),
                        TimgWdtClockConfig::PllF80m => release_pll_f80m(clocks),
                    }
                }
            }
            pub fn wdt_clock_config_frequency(config: TimgWdtClockConfig) -> u32 {
                match config {
                    TimgWdtClockConfig::XtalClk => xtal_clk_frequency(),
                    TimgWdtClockConfig::RcFastClk => rc_fast_clk_frequency(),
                    TimgWdtClockConfig::PllF80m => pll_f80m_frequency(),
                }
            }
            pub fn wdt_clock_frequency(self) -> u32 {
                TIMG_WDT_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn wdt_clock_source_frequency(source: TimgWdtClockConfig) -> u32 {
                Self::wdt_clock_config_frequency(source)
            }
        }
        impl UartInstance {
            pub fn configure_function_clock(
                self,
                clocks: &mut ClockTree,
                config: UartFunctionClockConfig,
            ) {
                let old_config = clocks.uart_function_clock[self as usize].replace(config);
                refresh_uart_function_clock_downstream(clocks, self);
                let active = clocks.uart_function_clock_refcount[self as usize] > 0;
                if active {
                    match config.sclk {
                        UartFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                        UartFunctionClockSclk::PllF80m => request_pll_f80m(clocks),
                        UartFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                    }
                }
                self.configure_function_clock_impl(clocks, old_config, config);
                if active && let Some(old_config) = old_config {
                    match old_config.sclk {
                        UartFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                        UartFunctionClockSclk::PllF80m => release_pll_f80m(clocks),
                        UartFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<UartFunctionClockConfig> {
                clocks.uart_function_clock[self as usize]
            }
            pub fn request_function_clock(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::FUNCTION_CLOCK", self);
                if increment_reference_count(
                    &mut clocks.uart_function_clock_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::FUNCTION_CLOCK", self);
                    match unwrap!(clocks.uart_function_clock[self as usize]).sclk {
                        UartFunctionClockSclk::Xtal => request_xtal_clk(clocks),
                        UartFunctionClockSclk::PllF80m => request_pll_f80m(clocks),
                        UartFunctionClockSclk::RcFast => request_rc_fast_clk(clocks),
                    }
                    self.enable_function_clock_impl(clocks, true);
                }
            }
            pub fn release_function_clock(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::FUNCTION_CLOCK", self);
                if decrement_reference_count(
                    &mut clocks.uart_function_clock_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::FUNCTION_CLOCK", self);
                    self.enable_function_clock_impl(clocks, false);
                    match unwrap!(clocks.uart_function_clock[self as usize]).sclk {
                        UartFunctionClockSclk::Xtal => release_xtal_clk(clocks),
                        UartFunctionClockSclk::PllF80m => release_pll_f80m(clocks),
                        UartFunctionClockSclk::RcFast => release_rc_fast_clk(clocks),
                    }
                }
            }
            pub fn function_clock_config_frequency(config: UartFunctionClockConfig) -> u32 {
                (match config.sclk {
                    UartFunctionClockSclk::Xtal => xtal_clk_frequency(),
                    UartFunctionClockSclk::PllF80m => pll_f80m_frequency(),
                    UartFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                } / (config.div_num() + 1))
            }
            pub fn function_clock_frequency(self) -> u32 {
                UART_FUNCTION_CLOCK_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
            pub fn function_clock_source_frequency(sclk: UartFunctionClockSclk) -> u32 {
                match sclk {
                    UartFunctionClockSclk::Xtal => xtal_clk_frequency(),
                    UartFunctionClockSclk::PllF80m => pll_f80m_frequency(),
                    UartFunctionClockSclk::RcFast => rc_fast_clk_frequency(),
                }
            }
            pub fn configure_baud_rate_generator(
                self,
                clocks: &mut ClockTree,
                config: UartBaudRateGeneratorConfig,
            ) {
                let old_config = clocks.uart_baud_rate_generator[self as usize].replace(config);
                refresh_uart_baud_rate_generator_downstream(clocks, self);
                self.configure_baud_rate_generator_impl(clocks, old_config, config);
            }
            pub fn baud_rate_generator_config(
                self,
                clocks: &mut ClockTree,
            ) -> Option<UartBaudRateGeneratorConfig> {
                clocks.uart_baud_rate_generator[self as usize]
            }
            pub fn request_baud_rate_generator(self, clocks: &mut ClockTree) {
                trace!("Requesting {:?}::BAUD_RATE_GENERATOR", self);
                if increment_reference_count(
                    &mut clocks.uart_baud_rate_generator_refcount[self as usize],
                ) {
                    trace!("Enabling {:?}::BAUD_RATE_GENERATOR", self);
                    self.request_function_clock(clocks);
                    self.enable_baud_rate_generator_impl(clocks, true);
                }
            }
            pub fn release_baud_rate_generator(self, clocks: &mut ClockTree) {
                trace!("Releasing {:?}::BAUD_RATE_GENERATOR", self);
                if decrement_reference_count(
                    &mut clocks.uart_baud_rate_generator_refcount[self as usize],
                ) {
                    trace!("Disabling {:?}::BAUD_RATE_GENERATOR", self);
                    self.enable_baud_rate_generator_impl(clocks, false);
                    self.release_function_clock(clocks);
                }
            }
            pub fn baud_rate_generator_config_frequency(
                self,
                config: UartBaudRateGeneratorConfig,
            ) -> u32 {
                ((self.function_clock_frequency() * 16)
                    / ((config.integral() * 16) + config.fractional()))
            }
            pub fn baud_rate_generator_frequency(self) -> u32 {
                UART_BAUD_RATE_GENERATOR_FREQ_CACHE[self as usize]
                    .load(::core::sync::atomic::Ordering::Acquire)
            }
        }
        /// Clock tree configuration.
        ///
        /// The fields of this struct are optional, with the following caveats:
        /// - If `XTAL_CLK` is not specified, the crystal frequency will be automatically detected
        ///   if possible.
        /// - The CPU and its upstream clock nodes will be set to a default configuration.
        /// - Other unspecified clock sources will not be useable by peripherals.
        #[derive(Debug, Clone, Copy, PartialEq, Eq)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[instability::unstable]
        pub struct ClockConfig {
            /// `XTAL_CLK` configuration.
            pub xtal_clk: Option<XtalClkConfig>,
            /// `HP_ROOT_CLK` configuration.
            pub hp_root_clk: Option<HpRootClkConfig>,
            /// `CPU_CLK` configuration.
            pub cpu_clk: Option<CpuClkConfig>,
            /// `AHB_CLK` configuration.
            pub ahb_clk: Option<AhbClkConfig>,
            /// `APB_CLK` configuration.
            pub apb_clk: Option<ApbClkConfig>,
            /// `LP_FAST_CLK` configuration.
            pub lp_fast_clk: Option<LpFastClkConfig>,
            /// `LP_SLOW_CLK` configuration.
            pub lp_slow_clk: Option<LpSlowClkConfig>,
            /// `BLE_LP_CLK` configuration.
            pub ble_lp_clk: Option<BleLpClkConfig>,
            /// `CRYPTO_CLK` configuration.
            pub crypto_clk: Option<CryptoClkConfig>,
            /// `TIMG_CALIBRATION_CLOCK` configuration.
            pub timg_calibration_clock: Option<TimgCalibrationClockConfig>,
        }
        impl ClockConfig {
            fn apply(&self, clocks: &mut ClockTree) {
                if let Some(config) = self.xtal_clk {
                    configure_xtal_clk(clocks, config);
                }
                if let Some(config) = self.hp_root_clk {
                    configure_hp_root_clk(clocks, config);
                }
                if let Some(config) = self.cpu_clk {
                    configure_cpu_clk(clocks, config);
                }
                if let Some(config) = self.ahb_clk {
                    configure_ahb_clk(clocks, config);
                }
                if let Some(config) = self.apb_clk {
                    configure_apb_clk(clocks, config);
                }
                if let Some(config) = self.lp_fast_clk {
                    configure_lp_fast_clk(clocks, config);
                }
                if let Some(config) = self.lp_slow_clk {
                    configure_lp_slow_clk(clocks, config);
                }
                if let Some(config) = self.ble_lp_clk {
                    configure_ble_lp_clk(clocks, config);
                }
                if let Some(config) = self.crypto_clk {
                    configure_crypto_clk(clocks, config);
                }
                if let Some(config) = self.timg_calibration_clock {
                    configure_timg_calibration_clock(clocks, config);
                }
            }
        }
        fn increment_reference_count(refcount: &mut u32) -> bool {
            let first = *refcount == 0;
            *refcount = unwrap!(refcount.checked_add(1), "Reference count overflow");
            first
        }
        fn decrement_reference_count(refcount: &mut u32) -> bool {
            *refcount = refcount.saturating_sub(1);
            let last = *refcount == 0;
            last
        }
        fn refresh_xtal_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.xtal_clk {
                XTAL_CLK_FREQ_CACHE.store(
                    xtal_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_hp_root_clk_downstream(clocks);
            refresh_lp_fast_clk_downstream(clocks);
            refresh_ble_lp_clk_downstream(clocks);
            refresh_crypto_clk_downstream(clocks);
            for child_instance in [AdcInstance::ApbSaradc] {
                refresh_adc_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [I2cInstance::I2c0] {
                refresh_i2c_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [I2sInstance::I2s0] {
                refresh_i2s_tx_clk_downstream(clocks, child_instance);
                refresh_i2s_rx_clk_downstream(clocks, child_instance);
            }
            for child_instance in [SpiInstance::Spi2] {
                refresh_spi_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [TimgInstance::Timg0, TimgInstance::Timg1] {
                refresh_timg_function_clock_downstream(clocks, child_instance);
                refresh_timg_wdt_clock_downstream(clocks, child_instance);
            }
            for child_instance in [
                UartInstance::Uart0,
                UartInstance::Uart1,
                UartInstance::Uart2,
            ] {
                refresh_uart_function_clock_downstream(clocks, child_instance);
            }
        }
        fn refresh_rc_fast_clk_downstream(clocks: &mut ClockTree) {
            refresh_hp_root_clk_downstream(clocks);
            refresh_lp_fast_clk_downstream(clocks);
            refresh_crypto_clk_downstream(clocks);
            refresh_timg_calibration_clock_downstream(clocks);
            for child_instance in [AdcInstance::ApbSaradc] {
                refresh_adc_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [I2cInstance::I2c0] {
                refresh_i2c_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [SpiInstance::Spi2] {
                refresh_spi_function_clock_downstream(clocks, child_instance);
            }
            for child_instance in [TimgInstance::Timg0, TimgInstance::Timg1] {
                refresh_timg_function_clock_downstream(clocks, child_instance);
                refresh_timg_wdt_clock_downstream(clocks, child_instance);
            }
            for child_instance in [
                UartInstance::Uart0,
                UartInstance::Uart1,
                UartInstance::Uart2,
            ] {
                refresh_uart_function_clock_downstream(clocks, child_instance);
            }
        }
        fn refresh_rc_slow_clk_downstream(clocks: &mut ClockTree) {
            refresh_lp_slow_clk_downstream(clocks);
            refresh_ble_lp_clk_downstream(clocks);
            refresh_timg_calibration_clock_downstream(clocks);
        }
        fn refresh_hp_root_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.hp_root_clk {
                HP_ROOT_CLK_FREQ_CACHE.store(
                    hp_root_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_cpu_clk_downstream(clocks);
            refresh_ahb_clk_downstream(clocks);
        }
        fn refresh_cpu_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.cpu_clk {
                CPU_CLK_FREQ_CACHE.store(
                    cpu_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_ahb_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.ahb_clk {
                AHB_CLK_FREQ_CACHE.store(
                    ahb_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_apb_clk_downstream(clocks);
        }
        fn refresh_apb_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.apb_clk {
                APB_CLK_FREQ_CACHE.store(
                    apb_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_lp_fast_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.lp_fast_clk {
                LP_FAST_CLK_FREQ_CACHE.store(
                    lp_fast_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_lp_slow_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.lp_slow_clk {
                LP_SLOW_CLK_FREQ_CACHE.store(
                    lp_slow_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_ble_lp_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.ble_lp_clk {
                BLE_LP_CLK_FREQ_CACHE.store(
                    ble_lp_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_crypto_clk_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.crypto_clk {
                CRYPTO_CLK_FREQ_CACHE.store(
                    crypto_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_timg_calibration_clock_downstream(clocks: &mut ClockTree) {
            if let Some(config) = clocks.timg_calibration_clock {
                TIMG_CALIBRATION_CLOCK_FREQ_CACHE.store(
                    timg_calibration_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_adc_function_clock_downstream(clocks: &mut ClockTree, instance: AdcInstance) {
            if let Some(config) = clocks.adc_function_clock[instance as usize] {
                ADC_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    AdcInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_i2c_function_clock_downstream(clocks: &mut ClockTree, instance: I2cInstance) {
            if let Some(config) = clocks.i2c_function_clock[instance as usize] {
                I2C_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    I2cInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_i2s_tx_clk_downstream(clocks: &mut ClockTree, instance: I2sInstance) {
            if let Some(config) = clocks.i2s_tx_clk[instance as usize] {
                I2S_TX_CLK_FREQ_CACHE[instance as usize].store(
                    I2sInstance::tx_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_i2s_mclk_out_downstream(clocks, instance);
        }
        fn refresh_i2s_rx_clk_downstream(clocks: &mut ClockTree, instance: I2sInstance) {
            if let Some(config) = clocks.i2s_rx_clk[instance as usize] {
                I2S_RX_CLK_FREQ_CACHE[instance as usize].store(
                    I2sInstance::rx_clk_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_i2s_mclk_out_downstream(clocks, instance);
        }
        fn refresh_i2s_mclk_out_downstream(clocks: &mut ClockTree, instance: I2sInstance) {
            if let Some(config) = clocks.i2s_mclk_out[instance as usize] {
                I2S_MCLK_OUT_FREQ_CACHE[instance as usize].store(
                    instance.mclk_out_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_spi_function_clock_downstream(clocks: &mut ClockTree, instance: SpiInstance) {
            if let Some(config) = clocks.spi_function_clock[instance as usize] {
                SPI_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    SpiInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_timg_function_clock_downstream(clocks: &mut ClockTree, instance: TimgInstance) {
            if let Some(config) = clocks.timg_function_clock[instance as usize] {
                TIMG_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    TimgInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_timg_wdt_clock_downstream(clocks: &mut ClockTree, instance: TimgInstance) {
            if let Some(config) = clocks.timg_wdt_clock[instance as usize] {
                TIMG_WDT_CLOCK_FREQ_CACHE[instance as usize].store(
                    TimgInstance::wdt_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
        fn refresh_uart_function_clock_downstream(clocks: &mut ClockTree, instance: UartInstance) {
            if let Some(config) = clocks.uart_function_clock[instance as usize] {
                UART_FUNCTION_CLOCK_FREQ_CACHE[instance as usize].store(
                    UartInstance::function_clock_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
            refresh_uart_baud_rate_generator_downstream(clocks, instance);
        }
        fn refresh_uart_baud_rate_generator_downstream(
            clocks: &mut ClockTree,
            instance: UartInstance,
        ) {
            if let Some(config) = clocks.uart_baud_rate_generator[instance as usize] {
                UART_BAUD_RATE_GENERATOR_FREQ_CACHE[instance as usize].store(
                    instance.baud_rate_generator_config_frequency(config),
                    ::core::sync::atomic::Ordering::Release,
                );
            }
        }
    };
}
/// Implement the `Peripheral` enum and enable/disable/reset functions.
///
/// This macro is intended to be placed in `esp_hal::system`.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! implement_peripheral_clocks {
    () => {
        #[doc(hidden)]
        #[derive(Debug, Clone, Copy, PartialEq, Eq)]
        #[repr(u8)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        pub enum Peripheral {
            /// AHB_GDMA peripheral clock signal
            AhbGdma,
            /// APB_SAR_ADC peripheral clock signal
            ApbSarAdc,
            /// ECC peripheral clock signal
            Ecc,
            /// I2C_EXT0 peripheral clock signal
            I2cExt0,
            /// I2S0 peripheral clock signal
            I2s0,
            /// SHA peripheral clock signal
            Sha,
            /// SPI2 peripheral clock signal
            Spi2,
            /// SYSTIMER peripheral clock signal
            Systimer,
            /// TIMG0 peripheral clock signal
            Timg0,
            /// TIMG1 peripheral clock signal
            Timg1,
            /// UART0 peripheral clock signal
            Uart0,
            /// UART1 peripheral clock signal
            Uart1,
            /// UART2 peripheral clock signal
            Uart2,
            /// USB_DEVICE peripheral clock signal
            UsbDevice,
        }
        impl Peripheral {
            const KEEP_ENABLED: &[Peripheral] =
                &[Self::Systimer, Self::Timg0, Self::Uart0, Self::UsbDevice];
            const COUNT: usize = Self::ALL.len();
            const ALL: &[Self] = &[
                Self::AhbGdma,
                Self::ApbSarAdc,
                Self::Ecc,
                Self::I2cExt0,
                Self::I2s0,
                Self::Sha,
                Self::Spi2,
                Self::Systimer,
                Self::Timg0,
                Self::Timg1,
                Self::Uart0,
                Self::Uart1,
                Self::Uart2,
                Self::UsbDevice,
            ];
        }
        unsafe fn enable_internal_racey(peripheral: Peripheral, enable: bool) {
            match peripheral {
                Peripheral::AhbGdma => {
                    crate::peripherals::SYSTEM::regs()
                        .gdma_conf()
                        .modify(|_, w| w.gdma_clk_en().bit(enable));
                }
                Peripheral::ApbSarAdc => {
                    crate::peripherals::SYSTEM::regs()
                        .saradc_conf()
                        .modify(|_, w| w.saradc_reg_clk_en().bit(enable));
                }
                Peripheral::Ecc => {
                    crate::peripherals::SYSTEM::regs()
                        .ecc_conf()
                        .modify(|_, w| w.ecc_clk_en().bit(enable));
                }
                Peripheral::I2cExt0 => {
                    crate::peripherals::SYSTEM::regs()
                        .i2c0_conf()
                        .modify(|_, w| w.i2c0_clk_en().bit(enable));
                }
                Peripheral::I2s0 => {
                    crate::peripherals::SYSTEM::regs()
                        .i2s_conf()
                        .modify(|_, w| w.i2s_clk_en().bit(enable));
                }
                Peripheral::Sha => {
                    crate::peripherals::SYSTEM::regs()
                        .sha_conf()
                        .modify(|_, w| w.sha_clk_en().bit(enable));
                }
                Peripheral::Spi2 => {
                    crate::peripherals::SYSTEM::regs()
                        .spi2_conf()
                        .modify(|_, w| w.spi2_clk_en().bit(enable));
                }
                Peripheral::Systimer => {
                    crate::peripherals::SYSTEM::regs()
                        .systimer_conf()
                        .modify(|_, w| w.systimer_clk_en().bit(enable));
                }
                Peripheral::Timg0 => {
                    crate::peripherals::SYSTEM::regs()
                        .timergroup(0)
                        .conf()
                        .modify(|_, w| w.clk_en().bit(enable));
                }
                Peripheral::Timg1 => {
                    crate::peripherals::SYSTEM::regs()
                        .timergroup(1)
                        .conf()
                        .modify(|_, w| w.clk_en().bit(enable));
                }
                Peripheral::Uart0 => {
                    crate::peripherals::SYSTEM::regs()
                        .uart(0)
                        .conf()
                        .modify(|_, w| w.clk_en().bit(enable));
                }
                Peripheral::Uart1 => {
                    crate::peripherals::SYSTEM::regs()
                        .uart(1)
                        .conf()
                        .modify(|_, w| w.clk_en().bit(enable));
                }
                Peripheral::Uart2 => {
                    crate::peripherals::SYSTEM::regs()
                        .uart(2)
                        .conf()
                        .modify(|_, w| w.clk_en().bit(enable));
                }
                Peripheral::UsbDevice => {
                    crate::peripherals::SYSTEM::regs()
                        .usb_device_conf()
                        .modify(|_, w| w.usb_device_clk_en().bit(enable));
                }
            }
        }
        unsafe fn assert_peri_reset_racey(peripheral: Peripheral, reset: bool) {
            match peripheral {
                Peripheral::AhbGdma => {
                    crate::peripherals::SYSTEM::regs()
                        .gdma_conf()
                        .modify(|_, w| w.gdma_rst_en().bit(reset));
                }
                Peripheral::ApbSarAdc => {
                    crate::peripherals::SYSTEM::regs()
                        .saradc_conf()
                        .modify(|_, w| w.saradc_reg_rst_en().bit(reset));
                }
                Peripheral::Ecc => {
                    crate::peripherals::SYSTEM::regs()
                        .ecc_conf()
                        .modify(|_, w| w.ecc_rst_en().bit(reset));
                }
                Peripheral::I2cExt0 => {
                    crate::peripherals::SYSTEM::regs()
                        .i2c0_conf()
                        .modify(|_, w| w.i2c0_rst_en().bit(reset));
                }
                Peripheral::I2s0 => {
                    crate::peripherals::SYSTEM::regs()
                        .i2s_conf()
                        .modify(|_, w| w.i2s_rst_en().bit(reset));
                }
                Peripheral::Sha => {
                    crate::peripherals::SYSTEM::regs()
                        .sha_conf()
                        .modify(|_, w| w.sha_rst_en().bit(reset));
                }
                Peripheral::Spi2 => {
                    crate::peripherals::SYSTEM::regs()
                        .spi2_conf()
                        .modify(|_, w| w.spi2_rst_en().bit(reset));
                }
                Peripheral::Systimer => {
                    crate::peripherals::SYSTEM::regs()
                        .systimer_conf()
                        .modify(|_, w| w.systimer_rst_en().bit(reset));
                }
                Peripheral::Timg0 => {
                    crate::peripherals::SYSTEM::regs()
                        .timergroup(0)
                        .conf()
                        .modify(|_, w| w.rst_en().bit(reset));
                }
                Peripheral::Timg1 => {
                    crate::peripherals::SYSTEM::regs()
                        .timergroup(1)
                        .conf()
                        .modify(|_, w| w.rst_en().bit(reset));
                }
                Peripheral::Uart0 => {
                    crate::peripherals::SYSTEM::regs()
                        .uart(0)
                        .conf()
                        .modify(|_, w| w.rst_en().bit(reset));
                }
                Peripheral::Uart1 => {
                    crate::peripherals::SYSTEM::regs()
                        .uart(1)
                        .conf()
                        .modify(|_, w| w.rst_en().bit(reset));
                }
                Peripheral::Uart2 => {
                    crate::peripherals::SYSTEM::regs()
                        .uart(2)
                        .conf()
                        .modify(|_, w| w.rst_en().bit(reset));
                }
                Peripheral::UsbDevice => {
                    crate::peripherals::SYSTEM::regs()
                        .usb_device_conf()
                        .modify(|_, w| w.usb_device_rst_en().bit(reset));
                }
            }
        }
    };
}
/// Macro to get the address range of the given memory region.
///
/// This macro provides two syntax options for each memory region:
///
/// - `memory_range!("region_name")` returns the address range as a range expression (`start..end`).
/// - `memory_range!(size as str, "region_name")` returns the size of the region as a string
///   literal.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! memory_range {
    ("DRAM") => {
        0x40800000..0x40850000
    };
    (size as str, "DRAM") => {
        "327680"
    };
    ("DRAM2_UNINIT") => {
        0x4083EA70..0x4084EA70
    };
    (size as str, "DRAM2_UNINIT") => {
        "65536"
    };
    ("IROM") => {
        0x42000000..0x44000000
    };
    (size as str, "IROM") => {
        "33554432"
    };
    ("DROM") => {
        0x42000000..0x44000000
    };
    (size as str, "DROM") => {
        "33554432"
    };
}
/// This macro can be used to generate code for each peripheral instance of the I2C master driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($id:literal, $instance:ident, $sys:ident, $scl:ident, $sda:ident)`
///
/// Macro fragments:
/// - `$id`: the index of the I2C instance
/// - `$instance`: the name of the I2C instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$scl`, `$sda`: peripheral signal names.
///
/// Example data: `(0, I2C0, I2cExt0, I2CEXT0_SCL, I2CEXT0_SDA)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_i2c_master {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_i2c_master { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_i2c_master!((0, I2C0, I2cExt0, I2CEXT0_SCL,
        I2CEXT0_SDA)); _for_each_inner_i2c_master!((all(0, I2C0, I2cExt0, I2CEXT0_SCL,
        I2CEXT0_SDA)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the I2S driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $mclk:ident, $bclk:ident, $ws:ident, $bclk_rx:ident,
/// $ws_rx:ident, [$($dout:ident),*], [$($din:ident),*], $pdm_tx:literal, $pdm_rx:literal,
/// $pcm2pdm:literal, $pdm2pcm:literal)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the I2S instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$mclk`: the MCLK output signal (a placeholder on chips without a GPIO-matrix MCLK).
/// - `$bclk`, `$ws`: TX bit clock and word select output signals.
/// - `$bclk_rx`, `$ws_rx`: RX bit clock and word select output signals.
/// - `$dout`, `$din`: data-out and data-in signal names.
/// - `$pdm_tx`, `$pdm_rx`: whether the instance supports PDM TX/RX.
/// - `$pcm2pdm`, `$pdm2pcm`: whether the instance supports the hardware PCM<->PDM format conversion
///   filter on TX/RX.
///
/// Example data:
/// - `(I2S0, I2s0, I2S_MCLK, I2SO_BCK, I2SO_WS, I2SI_BCK, I2SI_WS, [I2SO_SD], [I2SI_SD], true,
///   true, true, true)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_i2s {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_i2s { $(($pattern) => $code;)* ($other : tt) => {} }
        _for_each_inner_i2s!((I2S0)); _for_each_inner_i2s!((I2S0, I2s0, I2S_MCLK,
        I2SO_BCK, I2SO_WS, I2SI_BCK, I2SI_WS, [I2SO_SD], [I2SI_SD], true, true, true,
        false)); _for_each_inner_i2s!((names(I2S0))); _for_each_inner_i2s!((all(I2S0,
        I2s0, I2S_MCLK, I2SO_BCK, I2SO_WS, I2SI_BCK, I2SI_WS, [I2SO_SD], [I2SI_SD], true,
        true, true, false)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the UART driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($id:literal, $instance:ident, $sys:ident, $rx:ident, $tx:ident, $cts:ident,
/// $rts:ident)`
///
/// Macro fragments:
///
/// - `$id`: the index of the UART instance
/// - `$instance`: the name of the UART instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$rx`, `$tx`, `$cts`, `$rts`: signal names.
///
/// Example data: `(0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_uart {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_uart { $(($pattern) => $code;)* ($other : tt) => {}
        } _for_each_inner_uart!((0, UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS,
        wakeup_source = true)); _for_each_inner_uart!((1, UART1, Uart1, U1RXD, U1TXD,
        U1CTS, U1RTS, wakeup_source = true)); _for_each_inner_uart!((2, UART2, Uart2,
        U2RXD, U2TXD, U2CTS, U2RTS, wakeup_source = true)); _for_each_inner_uart!((all(0,
        UART0, Uart0, U0RXD, U0TXD, U0CTS, U0RTS, wakeup_source = true), (1, UART1,
        Uart1, U1RXD, U1TXD, U1CTS, U1RTS, wakeup_source = true), (2, UART2, Uart2,
        U2RXD, U2TXD, U2CTS, U2RTS, wakeup_source = true)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the SPI master driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $sclk:ident [$($cs:ident),*] [$($sio:ident),*]
/// $($is_qspi:literal)?)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the SPI instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$cs`, `$sio`: chip select and SIO signal names.
/// - `$is_qspi`: a `true` literal present if the SPI instance supports QSPI.
///
/// Example data:
/// - `(SPI2, Spi2, FSPICLK [FSPICS0, FSPICS1, FSPICS2, FSPICS3, FSPICS4, FSPICS5] [FSPID, FSPIQ,
///   FSPIWP, FSPIHD, FSPIIO4, FSPIIO5, FSPIIO6, FSPIIO7], true)`
/// - `(SPI3, Spi3, SPI3_CLK [SPI3_CS0, SPI3_CS1, SPI3_CS2] [SPI3_D, SPI3_Q])`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_spi_master {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_spi_master { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_spi_master!((SPI2)); _for_each_inner_spi_master!((SPI2,
        Spi2, FSPICLK[FSPICS0, FSPICS1, FSPICS2, FSPICS3, FSPICS4, FSPICS5] [FSPID,
        FSPIQ, FSPIWP, FSPIHD], true)); _for_each_inner_spi_master!((names(SPI2)));
        _for_each_inner_spi_master!((all(SPI2, Spi2, FSPICLK[FSPICS0, FSPICS1, FSPICS2,
        FSPICS3, FSPICS4, FSPICS5] [FSPID, FSPIQ, FSPIWP, FSPIHD], true)));
    };
}
/// This macro can be used to generate code for each peripheral instance of the SPI slave driver.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($instance:ident, $sys:ident, $sclk:ident, $mosi:ident, $miso:ident, $cs:ident)`
///
/// Macro fragments:
///
/// - `$instance`: the name of the SPI instance
/// - `$sys`: the name of the instance as it is in the `esp_hal::system::Peripheral` enum.
/// - `$sclk`, `$mosi`, `$miso`, `$cs`: signal names.
///
/// Example data: `(SPI2, Spi2, FSPICLK, FSPID, FSPIQ, FSPICS0)`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_spi_slave {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_spi_slave { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_spi_slave!((SPI2)); _for_each_inner_spi_slave!((SPI2,
        Spi2, FSPICLK, FSPID, FSPIQ, FSPICS0));
        _for_each_inner_spi_slave!((names(SPI2))); _for_each_inner_spi_slave!((all(SPI2,
        Spi2, FSPICLK, FSPID, FSPIQ, FSPICS0)));
    };
}
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_peripheral {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_peripheral { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO0 peripheral singleton"] GPIO0 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO1 peripheral singleton"]
        GPIO1 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO2 peripheral singleton"] GPIO2 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO3 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO3 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO4 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO4 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO5 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO5 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO6 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO6 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO7 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO7 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO8 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO8 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO9 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO9 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO10 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO10 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO11 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO11 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO12 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO12 <= virtual())); _for_each_inner_peripheral!((@
        peri_type #[doc = "GPIO13 peripheral singleton (Limitations exist)"] #[doc = ""]
        #[doc = "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO13 <= virtual())); _for_each_inner_peripheral!((@
        peri_type #[doc = "GPIO14 peripheral singleton (Limitations exist)"] #[doc = ""]
        #[doc = "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO14 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO15 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO15 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO16 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO16 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO17 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO17 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO18 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO18 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO19 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO19 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO20 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO20 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO21 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO21 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO22 peripheral singleton"]
        GPIO22 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO23 peripheral singleton"] GPIO23 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO24 peripheral singleton"]
        GPIO24 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO25 peripheral singleton"] GPIO25 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO26 peripheral singleton"]
        GPIO26 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO27 peripheral singleton"] GPIO27 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO28 peripheral singleton"]
        GPIO28 <= virtual())); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO29 peripheral singleton"] GPIO29 <= virtual()));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA_CH0 peripheral singleton"]
        DMA_CH0 <= virtual(DMA_IN_CH0 : { bind_dma_in_interrupt, enable_dma_in_interrupt,
        disable_dma_in_interrupt }, DMA_OUT_CH0 : { bind_dma_out_interrupt,
        enable_dma_out_interrupt, disable_dma_out_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "DMA_CH1 peripheral singleton"]
        DMA_CH1 <= virtual(DMA_IN_CH1 : { bind_dma_in_interrupt, enable_dma_in_interrupt,
        disable_dma_in_interrupt }, DMA_OUT_CH1 : { bind_dma_out_interrupt,
        enable_dma_out_interrupt, disable_dma_out_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "APB_SARADC peripheral singleton"] APB_SARADC <= APB_SARADC() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "ASSIST_DEBUG peripheral singleton"] ASSIST_DEBUG <= ASSIST_DEBUG() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "CACHE peripheral singleton"]
        CACHE <= CACHE() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "CLIC peripheral singleton"] CLIC <= CLIC() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "CLINT peripheral singleton"]
        CLINT <= CLINT() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "DMA peripheral singleton"] DMA <= DMA() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "ECC peripheral singleton"] ECC
        <= ECC() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "ECDSA peripheral singleton"] ECDSA <= ECDSA() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "EFUSE peripheral singleton"]
        EFUSE <= EFUSE() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "ETM peripheral singleton"] ETM <= SOC_ETM() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "GPIO peripheral singleton"]
        GPIO <= GPIO() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO_SD peripheral singleton"] GPIO_SD <= GPIO_EXT() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "HP_APM peripheral singleton"]
        HP_APM <= HP_APM() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "HP_SYS peripheral singleton"] HP_SYS <= HP_SYS() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "I2C_ANA_MST peripheral singleton"] I2C_ANA_MST <= I2C_ANA_MST() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "I2C0 peripheral singleton"]
        I2C0 <= I2C0(I2C_EXT0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "I2S0 peripheral singleton"] I2S0 <= I2S0(I2S0 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "INTERRUPT_CORE0 peripheral singleton"] INTERRUPT_CORE0 <= INTERRUPT_CORE0()
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "INTPRI peripheral singleton"] INTPRI <= INTPRI() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "IO_MUX peripheral singleton"]
        IO_MUX <= IO_MUX() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "LP_ANA peripheral singleton"] LP_ANA <= LP_ANA() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LP_AON peripheral singleton"]
        LP_AON <= LP_AON() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "LP_APM peripheral singleton"] LP_APM <= LP_APM() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "LP_CLKRST peripheral singleton"] LP_CLKRST <= LP_CLKRST() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LPWR peripheral singleton"]
        LPWR <= LP_CLKRST() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "LP_GPIO peripheral singleton"] LP_GPIO <= LP_GPIO() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "LP_IO_MUX peripheral singleton"] LP_IO_MUX <= LP_IO_MUX() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LP_PERI peripheral singleton"]
        LP_PERI <= LPPERI() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc
        = "LP_TEE peripheral singleton"] LP_TEE <= LP_TEE() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "RTC_TIMER peripheral singleton"] RTC_TIMER <= LP_TIMER() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "LP_WDT peripheral singleton"]
        LP_WDT <= LP_WDT() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "MEM_MONITOR peripheral singleton"] MEM_MONITOR <= MEM_MONITOR() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "MODEM_LPCON peripheral singleton"] MODEM_LPCON <= MODEM_LPCON() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "MODEM_SYSCON peripheral singleton"] MODEM_SYSCON <= MODEM_SYSCON() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "PAU peripheral singleton"] PAU
        <= PAU() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "PCR peripheral singleton"] PCR <= PCR() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "PMU peripheral singleton"] PMU
        <= PMU() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "RNG peripheral singleton"] RNG <= LPPERI() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SHA peripheral singleton"] SHA
        <= SHA(SHA : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt
        }) (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SLC peripheral singleton"] SLC <= SLC() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SPI0 peripheral singleton"]
        SPI0 <= SPI0() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SPI1 peripheral singleton"] SPI1 <= SPI1() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SPI2 peripheral singleton"]
        SPI2 <= SPI2(SPI2 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "SYSTEM peripheral singleton"] SYSTEM <= PCR() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "SYSTIMER peripheral singleton"]
        SYSTIMER <= SYSTIMER() (unstable))); _for_each_inner_peripheral!((@ peri_type
        #[doc = "TEE peripheral singleton"] TEE <= TEE() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "TIMG0 peripheral singleton"]
        TIMG0 <= TIMG0() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "TIMG1 peripheral singleton"] TIMG1 <= TIMG1() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "UART0 peripheral singleton"]
        UART0 <= UART0(UART0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "UART1 peripheral singleton"] UART1 <= UART1(UART1 : { bind_peri_interrupt,
        enable_peri_interrupt, disable_peri_interrupt })));
        _for_each_inner_peripheral!((@ peri_type #[doc = "UART2 peripheral singleton"]
        UART2 <= UART2(UART2 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "USB_DEVICE peripheral singleton"] USB_DEVICE <= USB_DEVICE(USB_DEVICE : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "ADC1 peripheral singleton"] ADC1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "BT peripheral singleton"] BT <=
        virtual(LP_TIMER : { bind_lp_timer_interrupt, enable_lp_timer_interrupt,
        disable_lp_timer_interrupt }, BT_MAC : { bind_mac_interrupt,
        enable_mac_interrupt, disable_mac_interrupt }) (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "FLASH peripheral singleton"]
        FLASH <= virtual() (unstable))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "GPIO_DEDICATED peripheral singleton"] GPIO_DEDICATED <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc = "WIFI peripheral singleton"]
        WIFI <= virtual(WIFI_BB : { bind_bb_interrupt, enable_bb_interrupt,
        disable_bb_interrupt }, WIFI_MAC : { bind_mac_interrupt, enable_mac_interrupt,
        disable_mac_interrupt }, WIFI_PWR : { bind_pwr_interrupt, enable_pwr_interrupt,
        disable_pwr_interrupt }))); _for_each_inner_peripheral!((@ peri_type #[doc =
        "PSRAM peripheral singleton"] PSRAM <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR0 peripheral singleton"] FROM_CPU_INTR0 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR1 peripheral singleton"] FROM_CPU_INTR1 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR2 peripheral singleton"] FROM_CPU_INTR2 <= virtual() (unstable)));
        _for_each_inner_peripheral!((@ peri_type #[doc =
        "FROM_CPU_INTR3 peripheral singleton"] FROM_CPU_INTR3 <= virtual() (unstable)));
        _for_each_inner_peripheral!((#[cfg(not(use_xtal32k))] GPIO0));
        _for_each_inner_peripheral!((#[cfg(not(use_xtal32k))] GPIO1));
        _for_each_inner_peripheral!((GPIO2)); _for_each_inner_peripheral!((GPIO3));
        _for_each_inner_peripheral!((GPIO4)); _for_each_inner_peripheral!((GPIO5));
        _for_each_inner_peripheral!((GPIO6)); _for_each_inner_peripheral!((GPIO7));
        _for_each_inner_peripheral!((GPIO8)); _for_each_inner_peripheral!((GPIO9));
        _for_each_inner_peripheral!((GPIO10)); _for_each_inner_peripheral!((GPIO11));
        _for_each_inner_peripheral!((GPIO12)); _for_each_inner_peripheral!((GPIO13));
        _for_each_inner_peripheral!((GPIO14)); _for_each_inner_peripheral!((GPIO15));
        _for_each_inner_peripheral!((GPIO16)); _for_each_inner_peripheral!((GPIO17));
        _for_each_inner_peripheral!((GPIO18)); _for_each_inner_peripheral!((GPIO19));
        _for_each_inner_peripheral!((GPIO20)); _for_each_inner_peripheral!((GPIO21));
        _for_each_inner_peripheral!((GPIO22)); _for_each_inner_peripheral!((GPIO23));
        _for_each_inner_peripheral!((GPIO24)); _for_each_inner_peripheral!((GPIO25));
        _for_each_inner_peripheral!((GPIO26)); _for_each_inner_peripheral!((GPIO27));
        _for_each_inner_peripheral!((GPIO28)); _for_each_inner_peripheral!((GPIO29));
        _for_each_inner_peripheral!((DMA_CH0(unstable)));
        _for_each_inner_peripheral!((DMA_CH1(unstable)));
        _for_each_inner_peripheral!((APB_SARADC(unstable)));
        _for_each_inner_peripheral!((ASSIST_DEBUG(unstable)));
        _for_each_inner_peripheral!((CACHE(unstable)));
        _for_each_inner_peripheral!((CLINT(unstable)));
        _for_each_inner_peripheral!((DMA(unstable)));
        _for_each_inner_peripheral!((ECC(unstable)));
        _for_each_inner_peripheral!((ECDSA(unstable)));
        _for_each_inner_peripheral!((EFUSE(unstable)));
        _for_each_inner_peripheral!((ETM(unstable)));
        _for_each_inner_peripheral!((GPIO(unstable)));
        _for_each_inner_peripheral!((GPIO_SD(unstable)));
        _for_each_inner_peripheral!((HP_APM(unstable)));
        _for_each_inner_peripheral!((HP_SYS(unstable)));
        _for_each_inner_peripheral!((I2C_ANA_MST(unstable)));
        _for_each_inner_peripheral!((I2C0));
        _for_each_inner_peripheral!((I2S0(unstable)));
        _for_each_inner_peripheral!((INTERRUPT_CORE0(unstable)));
        _for_each_inner_peripheral!((INTPRI(unstable)));
        _for_each_inner_peripheral!((IO_MUX(unstable)));
        _for_each_inner_peripheral!((LP_ANA(unstable)));
        _for_each_inner_peripheral!((LP_AON(unstable)));
        _for_each_inner_peripheral!((LP_APM(unstable)));
        _for_each_inner_peripheral!((LP_CLKRST(unstable)));
        _for_each_inner_peripheral!((LPWR(unstable)));
        _for_each_inner_peripheral!((LP_GPIO(unstable)));
        _for_each_inner_peripheral!((LP_IO_MUX(unstable)));
        _for_each_inner_peripheral!((LP_PERI(unstable)));
        _for_each_inner_peripheral!((LP_TEE(unstable)));
        _for_each_inner_peripheral!((RTC_TIMER(unstable)));
        _for_each_inner_peripheral!((LP_WDT(unstable)));
        _for_each_inner_peripheral!((MEM_MONITOR(unstable)));
        _for_each_inner_peripheral!((MODEM_LPCON(unstable)));
        _for_each_inner_peripheral!((MODEM_SYSCON(unstable)));
        _for_each_inner_peripheral!((PAU(unstable)));
        _for_each_inner_peripheral!((PCR(unstable)));
        _for_each_inner_peripheral!((PMU(unstable)));
        _for_each_inner_peripheral!((RNG(unstable)));
        _for_each_inner_peripheral!((SHA(unstable)));
        _for_each_inner_peripheral!((SLC(unstable)));
        _for_each_inner_peripheral!((SPI0(unstable)));
        _for_each_inner_peripheral!((SPI1(unstable)));
        _for_each_inner_peripheral!((SPI2));
        _for_each_inner_peripheral!((SYSTEM(unstable)));
        _for_each_inner_peripheral!((SYSTIMER(unstable)));
        _for_each_inner_peripheral!((TEE(unstable)));
        _for_each_inner_peripheral!((TIMG0(unstable)));
        _for_each_inner_peripheral!((TIMG1(unstable)));
        _for_each_inner_peripheral!((UART0)); _for_each_inner_peripheral!((UART1));
        _for_each_inner_peripheral!((UART2));
        _for_each_inner_peripheral!((USB_DEVICE(unstable)));
        _for_each_inner_peripheral!((ADC1(unstable)));
        _for_each_inner_peripheral!((BT(unstable)));
        _for_each_inner_peripheral!((FLASH(unstable)));
        _for_each_inner_peripheral!((GPIO_DEDICATED(unstable)));
        _for_each_inner_peripheral!((WIFI));
        _for_each_inner_peripheral!((PSRAM(unstable)));
        _for_each_inner_peripheral!((FROM_CPU_INTR0(unstable)));
        _for_each_inner_peripheral!((FROM_CPU_INTR1(unstable)));
        _for_each_inner_peripheral!((FROM_CPU_INTR2(unstable)));
        _for_each_inner_peripheral!((FROM_CPU_INTR3(unstable)));
        _for_each_inner_peripheral!((SPI2, Spi2, 1, AhbGdmaChannel));
        _for_each_inner_peripheral!((I2S0, I2s0, 3, AhbGdmaChannel));
        _for_each_inner_peripheral!((SHA, Sha, 7, AhbGdmaChannel));
        _for_each_inner_peripheral!((all(@ peri_type #[doc =
        "GPIO0 peripheral singleton"] GPIO0 <= virtual()), (@ peri_type #[doc =
        "GPIO1 peripheral singleton"] GPIO1 <= virtual()), (@ peri_type #[doc =
        "GPIO2 peripheral singleton"] GPIO2 <= virtual()), (@ peri_type #[doc =
        "GPIO3 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO3 <= virtual()), (@ peri_type #[doc =
        "GPIO4 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO4 <= virtual()), (@ peri_type #[doc =
        "GPIO5 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO5 <= virtual()), (@ peri_type #[doc =
        "GPIO6 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using an external JTAG debugger.</li>"]
        #[doc = "</ul>"] #[doc = "</section>"] GPIO6 <= virtual()), (@ peri_type #[doc =
        "GPIO7 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO7 <= virtual()), (@ peri_type #[doc =
        "GPIO8 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO8 <= virtual()), (@ peri_type #[doc =
        "GPIO9 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin is a strapping pin, it determines how the chip boots.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO9 <= virtual()), (@ peri_type #[doc =
        "GPIO10 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO10 <= virtual()), (@ peri_type #[doc =
        "GPIO11 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>By default, this pin is used by the UART programming interface.</li>"] #[doc
        = "</ul>"] #[doc = "</section>"] GPIO11 <= virtual()), (@ peri_type #[doc =
        "GPIO12 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO12 <= virtual()), (@ peri_type #[doc =
        "GPIO13 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>These pins may be used to debug the chip using USB.</li>"] #[doc = "</ul>"]
        #[doc = "</section>"] GPIO13 <= virtual()), (@ peri_type #[doc =
        "GPIO14 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO14 <= virtual()), (@ peri_type #[doc =
        "GPIO15 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO15 <= virtual()), (@ peri_type #[doc =
        "GPIO16 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO16 <= virtual()), (@ peri_type #[doc =
        "GPIO17 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO17 <= virtual()), (@ peri_type #[doc =
        "GPIO18 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO18 <= virtual()), (@ peri_type #[doc =
        "GPIO19 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO19 <= virtual()), (@ peri_type #[doc =
        "GPIO20 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO20 <= virtual()), (@ peri_type #[doc =
        "GPIO21 peripheral singleton (Limitations exist)"] #[doc = ""] #[doc =
        "<section class=\"warning\">"] #[doc =
        "This pin may be available with certain limitations. Check your hardware to make sure whether you can use it."]
        #[doc = "<ul>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI flash.</li>"] #[doc =
        "<li>This pin may be reserved for interfacing with SPI PSRAM.</li>"] #[doc =
        "</ul>"] #[doc = "</section>"] GPIO21 <= virtual()), (@ peri_type #[doc =
        "GPIO22 peripheral singleton"] GPIO22 <= virtual()), (@ peri_type #[doc =
        "GPIO23 peripheral singleton"] GPIO23 <= virtual()), (@ peri_type #[doc =
        "GPIO24 peripheral singleton"] GPIO24 <= virtual()), (@ peri_type #[doc =
        "GPIO25 peripheral singleton"] GPIO25 <= virtual()), (@ peri_type #[doc =
        "GPIO26 peripheral singleton"] GPIO26 <= virtual()), (@ peri_type #[doc =
        "GPIO27 peripheral singleton"] GPIO27 <= virtual()), (@ peri_type #[doc =
        "GPIO28 peripheral singleton"] GPIO28 <= virtual()), (@ peri_type #[doc =
        "GPIO29 peripheral singleton"] GPIO29 <= virtual()), (@ peri_type #[doc =
        "DMA_CH0 peripheral singleton"] DMA_CH0 <= virtual(DMA_IN_CH0 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        DMA_OUT_CH0 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable)), (@ peri_type #[doc =
        "DMA_CH1 peripheral singleton"] DMA_CH1 <= virtual(DMA_IN_CH1 : {
        bind_dma_in_interrupt, enable_dma_in_interrupt, disable_dma_in_interrupt },
        DMA_OUT_CH1 : { bind_dma_out_interrupt, enable_dma_out_interrupt,
        disable_dma_out_interrupt }) (unstable)), (@ peri_type #[doc =
        "APB_SARADC peripheral singleton"] APB_SARADC <= APB_SARADC() (unstable)), (@
        peri_type #[doc = "ASSIST_DEBUG peripheral singleton"] ASSIST_DEBUG <=
        ASSIST_DEBUG() (unstable)), (@ peri_type #[doc = "CACHE peripheral singleton"]
        CACHE <= CACHE() (unstable)), (@ peri_type #[doc = "CLIC peripheral singleton"]
        CLIC <= CLIC() (unstable)), (@ peri_type #[doc = "CLINT peripheral singleton"]
        CLINT <= CLINT() (unstable)), (@ peri_type #[doc = "DMA peripheral singleton"]
        DMA <= DMA() (unstable)), (@ peri_type #[doc = "ECC peripheral singleton"] ECC <=
        ECC() (unstable)), (@ peri_type #[doc = "ECDSA peripheral singleton"] ECDSA <=
        ECDSA() (unstable)), (@ peri_type #[doc = "EFUSE peripheral singleton"] EFUSE <=
        EFUSE() (unstable)), (@ peri_type #[doc = "ETM peripheral singleton"] ETM <=
        SOC_ETM() (unstable)), (@ peri_type #[doc = "GPIO peripheral singleton"] GPIO <=
        GPIO() (unstable)), (@ peri_type #[doc = "GPIO_SD peripheral singleton"] GPIO_SD
        <= GPIO_EXT() (unstable)), (@ peri_type #[doc = "HP_APM peripheral singleton"]
        HP_APM <= HP_APM() (unstable)), (@ peri_type #[doc =
        "HP_SYS peripheral singleton"] HP_SYS <= HP_SYS() (unstable)), (@ peri_type #[doc
        = "I2C_ANA_MST peripheral singleton"] I2C_ANA_MST <= I2C_ANA_MST() (unstable)),
        (@ peri_type #[doc = "I2C0 peripheral singleton"] I2C0 <= I2C0(I2C_EXT0 : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (@
        peri_type #[doc = "I2S0 peripheral singleton"] I2S0 <= I2S0(I2S0 : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "INTERRUPT_CORE0 peripheral singleton"]
        INTERRUPT_CORE0 <= INTERRUPT_CORE0() (unstable)), (@ peri_type #[doc =
        "INTPRI peripheral singleton"] INTPRI <= INTPRI() (unstable)), (@ peri_type #[doc
        = "IO_MUX peripheral singleton"] IO_MUX <= IO_MUX() (unstable)), (@ peri_type
        #[doc = "LP_ANA peripheral singleton"] LP_ANA <= LP_ANA() (unstable)), (@
        peri_type #[doc = "LP_AON peripheral singleton"] LP_AON <= LP_AON() (unstable)),
        (@ peri_type #[doc = "LP_APM peripheral singleton"] LP_APM <= LP_APM()
        (unstable)), (@ peri_type #[doc = "LP_CLKRST peripheral singleton"] LP_CLKRST <=
        LP_CLKRST() (unstable)), (@ peri_type #[doc = "LPWR peripheral singleton"] LPWR
        <= LP_CLKRST() (unstable)), (@ peri_type #[doc = "LP_GPIO peripheral singleton"]
        LP_GPIO <= LP_GPIO() (unstable)), (@ peri_type #[doc =
        "LP_IO_MUX peripheral singleton"] LP_IO_MUX <= LP_IO_MUX() (unstable)), (@
        peri_type #[doc = "LP_PERI peripheral singleton"] LP_PERI <= LPPERI()
        (unstable)), (@ peri_type #[doc = "LP_TEE peripheral singleton"] LP_TEE <=
        LP_TEE() (unstable)), (@ peri_type #[doc = "RTC_TIMER peripheral singleton"]
        RTC_TIMER <= LP_TIMER() (unstable)), (@ peri_type #[doc =
        "LP_WDT peripheral singleton"] LP_WDT <= LP_WDT() (unstable)), (@ peri_type #[doc
        = "MEM_MONITOR peripheral singleton"] MEM_MONITOR <= MEM_MONITOR() (unstable)),
        (@ peri_type #[doc = "MODEM_LPCON peripheral singleton"] MODEM_LPCON <=
        MODEM_LPCON() (unstable)), (@ peri_type #[doc =
        "MODEM_SYSCON peripheral singleton"] MODEM_SYSCON <= MODEM_SYSCON() (unstable)),
        (@ peri_type #[doc = "PAU peripheral singleton"] PAU <= PAU() (unstable)), (@
        peri_type #[doc = "PCR peripheral singleton"] PCR <= PCR() (unstable)), (@
        peri_type #[doc = "PMU peripheral singleton"] PMU <= PMU() (unstable)), (@
        peri_type #[doc = "RNG peripheral singleton"] RNG <= LPPERI() (unstable)), (@
        peri_type #[doc = "SHA peripheral singleton"] SHA <= SHA(SHA : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "SLC peripheral singleton"] SLC <= SLC()
        (unstable)), (@ peri_type #[doc = "SPI0 peripheral singleton"] SPI0 <= SPI0()
        (unstable)), (@ peri_type #[doc = "SPI1 peripheral singleton"] SPI1 <= SPI1()
        (unstable)), (@ peri_type #[doc = "SPI2 peripheral singleton"] SPI2 <= SPI2(SPI2
        : { bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })), (@
        peri_type #[doc = "SYSTEM peripheral singleton"] SYSTEM <= PCR() (unstable)), (@
        peri_type #[doc = "SYSTIMER peripheral singleton"] SYSTIMER <= SYSTIMER()
        (unstable)), (@ peri_type #[doc = "TEE peripheral singleton"] TEE <= TEE()
        (unstable)), (@ peri_type #[doc = "TIMG0 peripheral singleton"] TIMG0 <= TIMG0()
        (unstable)), (@ peri_type #[doc = "TIMG1 peripheral singleton"] TIMG1 <= TIMG1()
        (unstable)), (@ peri_type #[doc = "UART0 peripheral singleton"] UART0 <=
        UART0(UART0 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "UART1 peripheral singleton"]
        UART1 <= UART1(UART1 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc = "UART2 peripheral singleton"]
        UART2 <= UART2(UART2 : { bind_peri_interrupt, enable_peri_interrupt,
        disable_peri_interrupt })), (@ peri_type #[doc =
        "USB_DEVICE peripheral singleton"] USB_DEVICE <= USB_DEVICE(USB_DEVICE : {
        bind_peri_interrupt, enable_peri_interrupt, disable_peri_interrupt })
        (unstable)), (@ peri_type #[doc = "ADC1 peripheral singleton"] ADC1 <= virtual()
        (unstable)), (@ peri_type #[doc = "BT peripheral singleton"] BT <=
        virtual(LP_TIMER : { bind_lp_timer_interrupt, enable_lp_timer_interrupt,
        disable_lp_timer_interrupt }, BT_MAC : { bind_mac_interrupt,
        enable_mac_interrupt, disable_mac_interrupt }) (unstable)), (@ peri_type #[doc =
        "FLASH peripheral singleton"] FLASH <= virtual() (unstable)), (@ peri_type #[doc
        = "GPIO_DEDICATED peripheral singleton"] GPIO_DEDICATED <= virtual() (unstable)),
        (@ peri_type #[doc = "WIFI peripheral singleton"] WIFI <= virtual(WIFI_BB : {
        bind_bb_interrupt, enable_bb_interrupt, disable_bb_interrupt }, WIFI_MAC : {
        bind_mac_interrupt, enable_mac_interrupt, disable_mac_interrupt }, WIFI_PWR : {
        bind_pwr_interrupt, enable_pwr_interrupt, disable_pwr_interrupt })), (@ peri_type
        #[doc = "PSRAM peripheral singleton"] PSRAM <= virtual() (unstable)), (@
        peri_type #[doc = "FROM_CPU_INTR0 peripheral singleton"] FROM_CPU_INTR0 <=
        virtual() (unstable)), (@ peri_type #[doc =
        "FROM_CPU_INTR1 peripheral singleton"] FROM_CPU_INTR1 <= virtual() (unstable)),
        (@ peri_type #[doc = "FROM_CPU_INTR2 peripheral singleton"] FROM_CPU_INTR2 <=
        virtual() (unstable)), (@ peri_type #[doc =
        "FROM_CPU_INTR3 peripheral singleton"] FROM_CPU_INTR3 <= virtual() (unstable))));
        _for_each_inner_peripheral!((singletons(#[cfg(not(use_xtal32k))] GPIO0),
        (#[cfg(not(use_xtal32k))] GPIO1), (GPIO2), (GPIO3), (GPIO4), (GPIO5), (GPIO6),
        (GPIO7), (GPIO8), (GPIO9), (GPIO10), (GPIO11), (GPIO12), (GPIO13), (GPIO14),
        (GPIO15), (GPIO16), (GPIO17), (GPIO18), (GPIO19), (GPIO20), (GPIO21), (GPIO22),
        (GPIO23), (GPIO24), (GPIO25), (GPIO26), (GPIO27), (GPIO28), (GPIO29),
        (DMA_CH0(unstable)), (DMA_CH1(unstable)), (APB_SARADC(unstable)),
        (ASSIST_DEBUG(unstable)), (CACHE(unstable)), (CLINT(unstable)), (DMA(unstable)),
        (ECC(unstable)), (ECDSA(unstable)), (EFUSE(unstable)), (ETM(unstable)),
        (GPIO(unstable)), (GPIO_SD(unstable)), (HP_APM(unstable)), (HP_SYS(unstable)),
        (I2C_ANA_MST(unstable)), (I2C0), (I2S0(unstable)), (INTERRUPT_CORE0(unstable)),
        (INTPRI(unstable)), (IO_MUX(unstable)), (LP_ANA(unstable)), (LP_AON(unstable)),
        (LP_APM(unstable)), (LP_CLKRST(unstable)), (LPWR(unstable)), (LP_GPIO(unstable)),
        (LP_IO_MUX(unstable)), (LP_PERI(unstable)), (LP_TEE(unstable)),
        (RTC_TIMER(unstable)), (LP_WDT(unstable)), (MEM_MONITOR(unstable)),
        (MODEM_LPCON(unstable)), (MODEM_SYSCON(unstable)), (PAU(unstable)),
        (PCR(unstable)), (PMU(unstable)), (RNG(unstable)), (SHA(unstable)),
        (SLC(unstable)), (SPI0(unstable)), (SPI1(unstable)), (SPI2), (SYSTEM(unstable)),
        (SYSTIMER(unstable)), (TEE(unstable)), (TIMG0(unstable)), (TIMG1(unstable)),
        (UART0), (UART1), (UART2), (USB_DEVICE(unstable)), (ADC1(unstable)),
        (BT(unstable)), (FLASH(unstable)), (GPIO_DEDICATED(unstable)), (WIFI),
        (PSRAM(unstable)), (FROM_CPU_INTR0(unstable)), (FROM_CPU_INTR1(unstable)),
        (FROM_CPU_INTR2(unstable)), (FROM_CPU_INTR3(unstable))));
        _for_each_inner_peripheral!((dma_eligible(SPI2, Spi2, 1, AhbGdmaChannel), (I2S0,
        I2s0, 3, AhbGdmaChannel), (SHA, Sha, 7, AhbGdmaChannel)));
    };
}
/// This macro can be used to generate code for each `GPIOn` instance.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has one option for its "Individual matcher" case:
///
/// Syntax: `($n:literal, $gpio:ident ($($digital_input_function:ident =>
/// $digital_input_signal:ident)*) ($($digital_output_function:ident =>
/// $digital_output_signal:ident)*) ($([$pin_attribute:ident])*))`
///
/// Macro fragments:
///
/// - `$n`: the number of the GPIO. For `GPIO0`, `$n` is 0.
/// - `$gpio`: the name of the GPIO.
/// - `$digital_input_function`: the number of the digital function, as an identifier (i.e. for
///   function 0 this is `_0`).
/// - `$digital_input_function`: the name of the digital function, as an identifier.
/// - `$digital_output_function`: the number of the digital function, as an identifier (i.e. for
///   function 0 this is `_0`).
/// - `$digital_output_function`: the name of the digital function, as an identifier.
/// - `$pin_attribute`: `Input` and/or `Output`, marks the possible directions of the GPIO.
///   Bracketed so that they can also be matched as optional fragments. Order is always Input first.
///
/// Example data: `(0, GPIO0 (_5 => EMAC_TX_CLK) (_1 => CLK_OUT1 _5 => EMAC_TX_CLK) ([Input]
/// [Output]))`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_gpio {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_gpio { $(($pattern) => $code;)* ($other : tt) => {}
        } _for_each_inner_gpio!((0, GPIO0() () ([Input] [Output])));
        _for_each_inner_gpio!((1, GPIO1() () ([Input] [Output])));
        _for_each_inner_gpio!((2, GPIO2(_2 => FSPIQ) (_2 => FSPIQ) ([Input] [Output])));
        _for_each_inner_gpio!((3, GPIO3(_0 => MTMS _2 => FSPIHD) (_2 => FSPIHD) ([Input]
        [Output]))); _for_each_inner_gpio!((4, GPIO4(_0 => MTDI _2 => FSPIWP) (_2 =>
        FSPIWP) ([Input] [Output]))); _for_each_inner_gpio!((5, GPIO5(_0 => MTCK) ()
        ([Input] [Output]))); _for_each_inner_gpio!((6, GPIO6(_0 => MTDO _2 => FSPICLK)
        (_2 => FSPICLK) ([Input] [Output]))); _for_each_inner_gpio!((7, GPIO7(_2 =>
        FSPID) (_2 => FSPID) ([Input] [Output]))); _for_each_inner_gpio!((8, GPIO8(_2 =>
        FSPICS0) (_2 => FSPICS0) ([Input] [Output]))); _for_each_inner_gpio!((9, GPIO9()
        () ([Input] [Output]))); _for_each_inner_gpio!((10, GPIO10(_0 => U0RXD) ()
        ([Input] [Output]))); _for_each_inner_gpio!((11, GPIO11() (_0 => U0TXD) ([Input]
        [Output]))); _for_each_inner_gpio!((12, GPIO12() () ([Input] [Output])));
        _for_each_inner_gpio!((13, GPIO13() () ([Input] [Output])));
        _for_each_inner_gpio!((14, GPIO14() (_0 => FSPICS1) ([Input] [Output])));
        _for_each_inner_gpio!((15, GPIO15(_0 => FSPICS0) (_0 => FSPICS0) ([Input]
        [Output]))); _for_each_inner_gpio!((16, GPIO16(_0 => FSPIQ) (_0 => FSPIQ)
        ([Input] [Output]))); _for_each_inner_gpio!((17, GPIO17(_0 => FSPIWP) (_0 =>
        FSPIWP) ([Input] [Output]))); _for_each_inner_gpio!((18, GPIO18() () ([Input]
        [Output]))); _for_each_inner_gpio!((19, GPIO19(_0 => FSPIHD) (_0 => FSPIHD)
        ([Input] [Output]))); _for_each_inner_gpio!((20, GPIO20(_0 => FSPICLK) (_0 =>
        FSPICLK) ([Input] [Output]))); _for_each_inner_gpio!((21, GPIO21(_0 => FSPID) (_0
        => FSPID) ([Input] [Output]))); _for_each_inner_gpio!((22, GPIO22(_0 =>
        SDIO_DATA2) () ([Input] [Output]))); _for_each_inner_gpio!((23, GPIO23(_0 =>
        SDIO_DATA3) () ([Input] [Output]))); _for_each_inner_gpio!((24, GPIO24() ()
        ([Input] [Output]))); _for_each_inner_gpio!((25, GPIO25(_0 => SDIO_CMD) ()
        ([Input] [Output]))); _for_each_inner_gpio!((26, GPIO26(_0 => SDIO_CLK) ()
        ([Input] [Output]))); _for_each_inner_gpio!((27, GPIO27(_0 => SDIO_DATA0) ()
        ([Input] [Output]))); _for_each_inner_gpio!((28, GPIO28(_0 => SDIO_DATA1) ()
        ([Input] [Output]))); _for_each_inner_gpio!((29, GPIO29() () ([Input]
        [Output]))); _for_each_inner_gpio!((all(0, GPIO0() () ([Input] [Output])), (1,
        GPIO1() () ([Input] [Output])), (2, GPIO2(_2 => FSPIQ) (_2 => FSPIQ) ([Input]
        [Output])), (3, GPIO3(_0 => MTMS _2 => FSPIHD) (_2 => FSPIHD) ([Input]
        [Output])), (4, GPIO4(_0 => MTDI _2 => FSPIWP) (_2 => FSPIWP) ([Input]
        [Output])), (5, GPIO5(_0 => MTCK) () ([Input] [Output])), (6, GPIO6(_0 => MTDO _2
        => FSPICLK) (_2 => FSPICLK) ([Input] [Output])), (7, GPIO7(_2 => FSPID) (_2 =>
        FSPID) ([Input] [Output])), (8, GPIO8(_2 => FSPICS0) (_2 => FSPICS0) ([Input]
        [Output])), (9, GPIO9() () ([Input] [Output])), (10, GPIO10(_0 => U0RXD) ()
        ([Input] [Output])), (11, GPIO11() (_0 => U0TXD) ([Input] [Output])), (12,
        GPIO12() () ([Input] [Output])), (13, GPIO13() () ([Input] [Output])), (14,
        GPIO14() (_0 => FSPICS1) ([Input] [Output])), (15, GPIO15(_0 => FSPICS0) (_0 =>
        FSPICS0) ([Input] [Output])), (16, GPIO16(_0 => FSPIQ) (_0 => FSPIQ) ([Input]
        [Output])), (17, GPIO17(_0 => FSPIWP) (_0 => FSPIWP) ([Input] [Output])), (18,
        GPIO18() () ([Input] [Output])), (19, GPIO19(_0 => FSPIHD) (_0 => FSPIHD)
        ([Input] [Output])), (20, GPIO20(_0 => FSPICLK) (_0 => FSPICLK) ([Input]
        [Output])), (21, GPIO21(_0 => FSPID) (_0 => FSPID) ([Input] [Output])), (22,
        GPIO22(_0 => SDIO_DATA2) () ([Input] [Output])), (23, GPIO23(_0 => SDIO_DATA3) ()
        ([Input] [Output])), (24, GPIO24() () ([Input] [Output])), (25, GPIO25(_0 =>
        SDIO_CMD) () ([Input] [Output])), (26, GPIO26(_0 => SDIO_CLK) () ([Input]
        [Output])), (27, GPIO27(_0 => SDIO_DATA0) () ([Input] [Output])), (28, GPIO28(_0
        => SDIO_DATA1) () ([Input] [Output])), (29, GPIO29() () ([Input] [Output]))));
    };
}
/// This macro can be used to generate code for each analog function of each GPIO.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident)` - simple case where you only need identifiers
/// - group: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident)` - expanded signal
///   case, where you need the number(s) of a signal, or the general group to which the signal
///   belongs. For example, in case of `ADC2_CH3` the expanded form looks like `(ADC2_CH3, ADCn_CHm,
///   2, 3)`.
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders. For `ADC2_CH3` this
///   is `ADCn_CHm`.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
///
/// Example data:
/// - `(ADC2_CH5, GPIO12)`
/// - `((ADC2_CH5, ADCn_CHm, 2, 5), GPIO12)`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_analog_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_analog_function { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_analog_function!((XTAL_32K_P, GPIO0));
        _for_each_inner_analog_function!((XTAL_32K_N, GPIO1));
        _for_each_inner_analog_function!((ADC1_CH0, GPIO1));
        _for_each_inner_analog_function!((ADC1_CH1, GPIO3));
        _for_each_inner_analog_function!((ADC1_CH2, GPIO4));
        _for_each_inner_analog_function!((ADC1_CH3, GPIO5));
        _for_each_inner_analog_function!((ZCD0, GPIO8));
        _for_each_inner_analog_function!((ZCD1, GPIO9));
        _for_each_inner_analog_function!((USJ_DM, GPIO12));
        _for_each_inner_analog_function!((USJ_DP, GPIO13));
        _for_each_inner_analog_function!(((ADC1_CH0, ADCn_CHm, 1, 0), GPIO1));
        _for_each_inner_analog_function!(((ADC1_CH1, ADCn_CHm, 1, 1), GPIO3));
        _for_each_inner_analog_function!(((ADC1_CH2, ADCn_CHm, 1, 2), GPIO4));
        _for_each_inner_analog_function!(((ADC1_CH3, ADCn_CHm, 1, 3), GPIO5));
        _for_each_inner_analog_function!(((ZCD0, ZCDn, 0), GPIO8));
        _for_each_inner_analog_function!(((ZCD1, ZCDn, 1), GPIO9));
        _for_each_inner_analog_function!((all(XTAL_32K_P, GPIO0), (XTAL_32K_N, GPIO1),
        (ADC1_CH0, GPIO1), (ADC1_CH1, GPIO3), (ADC1_CH2, GPIO4), (ADC1_CH3, GPIO5),
        (ZCD0, GPIO8), (ZCD1, GPIO9), (USJ_DM, GPIO12), (USJ_DP, GPIO13)));
        _for_each_inner_analog_function!((ADCn_CHm((ADC1_CH0, ADCn_CHm, 1, 0), GPIO1),
        ((ADC1_CH1, ADCn_CHm, 1, 1), GPIO3), ((ADC1_CH2, ADCn_CHm, 1, 2), GPIO4),
        ((ADC1_CH3, ADCn_CHm, 1, 3), GPIO5)));
        _for_each_inner_analog_function!((ZCDn((ZCD0, ZCDn, 0), GPIO8), ((ZCD1, ZCDn, 1),
        GPIO9)));
    };
}
/// This macro can be used to generate code for each LP function of each GPIO.
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident, $af:ident)` - simple case where you only need
///   identifiers, and maybe the function.
/// - group: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident, $af:ident, ($(
///   $lp_input_af:ident => $lp_input_signal:ident )*) ($( $lp_output_af:ident =>
///   $lp_output_signal:ident )*))` - expanded signal case, where you need the number(s) of a
///   signal, or the general group to which the signal belongs. Every expanded branch ends with the
///   pad's LP input and output function groups (empty on chips without an LP GPIO matrix).
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders. For `ADC2_CH3` this
///   is `ADCn_CHm`.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
/// - `$af`: the LP IO MUX function, as an identifier (i.e. for function 0 this is `_0`). This is
///   the name of an `LpFunction` variant, and its number is the value to write to the pad's
///   function select field.
/// - `$lp_input_af`: the LP IO MUX function for an LP peripheral input on this pad.
/// - `$lp_input_signal`: the LP peripheral input signal name.
/// - `$lp_output_af`: the LP IO MUX function for an LP peripheral output on this pad.
/// - `$lp_output_signal`: the LP peripheral output signal name.
///
/// Example data:
/// - `(LP_GPIO15, GPIO12, _0)`
/// - `((LP_GPIO15, LP_GPIOn, 15), GPIO12, _0, () ())`
/// - `((LP_GPIO14, LP_GPIOn, 14), GPIO14, _1, () (_0 => LP_UART_TXD))`
/// - `((SAR_I2C_SCL_1, SAR_I2C_SCL_n, 1), GPIO2, _3, () ())`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_lp_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_lp_function { $(($pattern) => $code;)* ($other : tt)
        => {} } _for_each_inner_lp_function!((LP_GPIO0, GPIO0, _1));
        _for_each_inner_lp_function!((LP_GPIO1, GPIO1, _1));
        _for_each_inner_lp_function!((LP_GPIO2, GPIO2, _1));
        _for_each_inner_lp_function!((LP_GPIO3, GPIO3, _1));
        _for_each_inner_lp_function!((LP_GPIO4, GPIO4, _1));
        _for_each_inner_lp_function!((LP_GPIO5, GPIO5, _1));
        _for_each_inner_lp_function!((LP_GPIO6, GPIO6, _1));
        _for_each_inner_lp_function!(((LP_GPIO0, LP_GPIOn, 0), GPIO0, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO1, LP_GPIOn, 1), GPIO1, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO2, LP_GPIOn, 2), GPIO2, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO3, LP_GPIOn, 3), GPIO3, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO4, LP_GPIOn, 4), GPIO4, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO5, LP_GPIOn, 5), GPIO5, _1, () ()));
        _for_each_inner_lp_function!(((LP_GPIO6, LP_GPIOn, 6), GPIO6, _1, () ()));
        _for_each_inner_lp_function!((all(LP_GPIO0, GPIO0, _1), (LP_GPIO1, GPIO1, _1),
        (LP_GPIO2, GPIO2, _1), (LP_GPIO3, GPIO3, _1), (LP_GPIO4, GPIO4, _1), (LP_GPIO5,
        GPIO5, _1), (LP_GPIO6, GPIO6, _1)));
        _for_each_inner_lp_function!((LP_GPIOn((LP_GPIO0, LP_GPIOn, 0), GPIO0, _1, ()
        ()), ((LP_GPIO1, LP_GPIOn, 1), GPIO1, _1, () ()), ((LP_GPIO2, LP_GPIOn, 2),
        GPIO2, _1, () ()), ((LP_GPIO3, LP_GPIOn, 3), GPIO3, _1, () ()), ((LP_GPIO4,
        LP_GPIOn, 4), GPIO4, _1, () ()), ((LP_GPIO5, LP_GPIOn, 5), GPIO5, _1, () ()),
        ((LP_GPIO6, LP_GPIOn, 6), GPIO6, _1, () ())));
    };
}
/// This macro can be used to generate code for each IOMUX digital function of each GPIO.
///
/// IOMUX functions are the alternate digital functions configured via the IO_MUX registers.
/// Use this to implement signal-specific traits for peripherals whose pins must bypass the
/// GPIO matrix (e.g., EMAC, USB).
///
/// For an explanation on the general syntax, as well as usage of individual/repeated
/// matchers, refer to [the crate-level documentation][crate#for_each-macros].
///
/// This macro has two options for its "Individual matcher" case:
///
/// - `all`: `($signal:ident, $gpio:ident, $af:ident)` - simple case where you only need
///   identifiers, and maybe the alternate function.
/// - group: `(($signal:ident, $group:ident $(, $number:literal)+), $gpio:ident, $af:ident)` -
///   expanded signal case, where you need the number(s) of a signal, or the general group to which
///   the signal belongs.
///
/// Macro fragments:
///
/// - `$signal`: the name of the signal.
/// - `$group`: the name of the signal, with numbers replaced by placeholders.
/// - `$number`: the numbers extracted from `$signal`.
/// - `$gpio`: the name of the GPIO.
/// - `$af`: the alternate function number, as an identifier (e.g. `_5`).
///
/// Example data:
/// - `(EMAC_RXD0, GPIO25, _5)`
/// - `((EMAC_RXDn, EMAC_RXDn, 0), GPIO25, _5)`
///
/// The expanded syntax is only available when the signal has at least one numbered component.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! for_each_iomux_function {
    ($($pattern:tt => $code:tt;)*) => {
        macro_rules! _for_each_inner_iomux_function { $(($pattern) => $code;)* ($other :
        tt) => {} } _for_each_inner_iomux_function!((FSPIQ, GPIO2, _2));
        _for_each_inner_iomux_function!((MTMS, GPIO3, _0));
        _for_each_inner_iomux_function!((FSPIHD, GPIO3, _2));
        _for_each_inner_iomux_function!((MTDI, GPIO4, _0));
        _for_each_inner_iomux_function!((FSPIWP, GPIO4, _2));
        _for_each_inner_iomux_function!((MTCK, GPIO5, _0));
        _for_each_inner_iomux_function!((MTDO, GPIO6, _0));
        _for_each_inner_iomux_function!((FSPICLK, GPIO6, _2));
        _for_each_inner_iomux_function!((FSPID, GPIO7, _2));
        _for_each_inner_iomux_function!((FSPICS0, GPIO8, _2));
        _for_each_inner_iomux_function!((U0RXD, GPIO10, _0));
        _for_each_inner_iomux_function!((U0TXD, GPIO11, _0));
        _for_each_inner_iomux_function!((FSPICS1, GPIO14, _0));
        _for_each_inner_iomux_function!((FSPICS0, GPIO15, _0));
        _for_each_inner_iomux_function!((FSPIQ, GPIO16, _0));
        _for_each_inner_iomux_function!((FSPIWP, GPIO17, _0));
        _for_each_inner_iomux_function!((FSPIHD, GPIO19, _0));
        _for_each_inner_iomux_function!((FSPICLK, GPIO20, _0));
        _for_each_inner_iomux_function!((FSPID, GPIO21, _0));
        _for_each_inner_iomux_function!((SDIO_DATA2, GPIO22, _0));
        _for_each_inner_iomux_function!((SDIO_DATA3, GPIO23, _0));
        _for_each_inner_iomux_function!((SDIO_CMD, GPIO25, _0));
        _for_each_inner_iomux_function!((SDIO_CLK, GPIO26, _0));
        _for_each_inner_iomux_function!((SDIO_DATA0, GPIO27, _0));
        _for_each_inner_iomux_function!((SDIO_DATA1, GPIO28, _0));
        _for_each_inner_iomux_function!(((FSPICS0, FSPICSn, 0), GPIO8, _2));
        _for_each_inner_iomux_function!(((FSPICS1, FSPICSn, 1), GPIO14, _0));
        _for_each_inner_iomux_function!(((FSPICS0, FSPICSn, 0), GPIO15, _0));
        _for_each_inner_iomux_function!(((SDIO_DATA2, SDIO_DATAn, 2), GPIO22, _0));
        _for_each_inner_iomux_function!(((SDIO_DATA3, SDIO_DATAn, 3), GPIO23, _0));
        _for_each_inner_iomux_function!(((SDIO_DATA0, SDIO_DATAn, 0), GPIO27, _0));
        _for_each_inner_iomux_function!(((SDIO_DATA1, SDIO_DATAn, 1), GPIO28, _0));
        _for_each_inner_iomux_function!((all(FSPIQ, GPIO2, _2), (MTMS, GPIO3, _0),
        (FSPIHD, GPIO3, _2), (MTDI, GPIO4, _0), (FSPIWP, GPIO4, _2), (MTCK, GPIO5, _0),
        (MTDO, GPIO6, _0), (FSPICLK, GPIO6, _2), (FSPID, GPIO7, _2), (FSPICS0, GPIO8,
        _2), (U0RXD, GPIO10, _0), (U0TXD, GPIO11, _0), (FSPICS1, GPIO14, _0), (FSPICS0,
        GPIO15, _0), (FSPIQ, GPIO16, _0), (FSPIWP, GPIO17, _0), (FSPIHD, GPIO19, _0),
        (FSPICLK, GPIO20, _0), (FSPID, GPIO21, _0), (SDIO_DATA2, GPIO22, _0),
        (SDIO_DATA3, GPIO23, _0), (SDIO_CMD, GPIO25, _0), (SDIO_CLK, GPIO26, _0),
        (SDIO_DATA0, GPIO27, _0), (SDIO_DATA1, GPIO28, _0)));
        _for_each_inner_iomux_function!((FSPICSn((FSPICS0, FSPICSn, 0), GPIO8, _2),
        ((FSPICS1, FSPICSn, 1), GPIO14, _0), ((FSPICS0, FSPICSn, 0), GPIO15, _0)));
        _for_each_inner_iomux_function!((SDIO_DATAn((SDIO_DATA2, SDIO_DATAn, 2), GPIO22,
        _0), ((SDIO_DATA3, SDIO_DATAn, 3), GPIO23, _0), ((SDIO_DATA0, SDIO_DATAn, 0),
        GPIO27, _0), ((SDIO_DATA1, SDIO_DATAn, 1), GPIO28, _0)));
    };
}
/// Returns the name of the GPIO that provides the given signal, as a string.
///
/// The macro takes the name of a direct function - a digital IO MUX function, an analog
/// function, or an LP IO MUX function - and expands to a string literal like `"GPIO4"`. It
/// is meant to keep documentation free of per-chip pin lists.
///
/// Signals that are not wired to a pad on this chip have to be routed through the GPIO
/// matrix, which can reach any pad. The macro has no pad to return for those, so it accepts
/// an optional fallback to expand to instead. The fallback is not validated.
///
/// If multiple pads provide the signal, the macro returns one that is not reserved for some
/// other purpose, such as booting or interfacing with flash.
///
/// Example usage:
/// - `gpio_for_signal!(ADC1_CH0)`
/// - `gpio_for_signal!(LP_I2C_SDA, "GPIO6")`
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! gpio_for_signal {
    (XTAL_32K_P $(, $_fallback:literal)?) => {
        "GPIO0"
    };
    (LP_GPIO0 $(, $_fallback:literal)?) => {
        "GPIO0"
    };
    (XTAL_32K_N $(, $_fallback:literal)?) => {
        "GPIO1"
    };
    (ADC1_CH0 $(, $_fallback:literal)?) => {
        "GPIO1"
    };
    (LP_GPIO1 $(, $_fallback:literal)?) => {
        "GPIO1"
    };
    (FSPIQ $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (LP_GPIO2 $(, $_fallback:literal)?) => {
        "GPIO2"
    };
    (MTMS $(, $_fallback:literal)?) => {
        "GPIO3"
    };
    (FSPIHD $(, $_fallback:literal)?) => {
        "GPIO3"
    };
    (ADC1_CH1 $(, $_fallback:literal)?) => {
        "GPIO3"
    };
    (LP_GPIO3 $(, $_fallback:literal)?) => {
        "GPIO3"
    };
    (MTDI $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (FSPIWP $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (ADC1_CH2 $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (LP_GPIO4 $(, $_fallback:literal)?) => {
        "GPIO4"
    };
    (MTCK $(, $_fallback:literal)?) => {
        "GPIO5"
    };
    (ADC1_CH3 $(, $_fallback:literal)?) => {
        "GPIO5"
    };
    (LP_GPIO5 $(, $_fallback:literal)?) => {
        "GPIO5"
    };
    (MTDO $(, $_fallback:literal)?) => {
        "GPIO6"
    };
    (FSPICLK $(, $_fallback:literal)?) => {
        "GPIO6"
    };
    (LP_GPIO6 $(, $_fallback:literal)?) => {
        "GPIO6"
    };
    (FSPID $(, $_fallback:literal)?) => {
        "GPIO7"
    };
    (FSPICS0 $(, $_fallback:literal)?) => {
        "GPIO8"
    };
    (ZCD0 $(, $_fallback:literal)?) => {
        "GPIO8"
    };
    (ZCD1 $(, $_fallback:literal)?) => {
        "GPIO9"
    };
    (U0RXD $(, $_fallback:literal)?) => {
        "GPIO10"
    };
    (U0TXD $(, $_fallback:literal)?) => {
        "GPIO11"
    };
    (USJ_DM $(, $_fallback:literal)?) => {
        "GPIO12"
    };
    (USJ_DP $(, $_fallback:literal)?) => {
        "GPIO13"
    };
    (FSPICS1 $(, $_fallback:literal)?) => {
        "GPIO14"
    };
    (SDIO_DATA2 $(, $_fallback:literal)?) => {
        "GPIO22"
    };
    (SDIO_DATA3 $(, $_fallback:literal)?) => {
        "GPIO23"
    };
    (SDIO_CMD $(, $_fallback:literal)?) => {
        "GPIO25"
    };
    (SDIO_CLK $(, $_fallback:literal)?) => {
        "GPIO26"
    };
    (SDIO_DATA0 $(, $_fallback:literal)?) => {
        "GPIO27"
    };
    (SDIO_DATA1 $(, $_fallback:literal)?) => {
        "GPIO28"
    };
    ($_signal:ident, $fallback:literal) => {
        $fallback
    };
}
/// Defines the `InputSignal` and `OutputSignal` enums.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_io_mux_signals {
    () => {
        #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
        #[derive(Debug, PartialEq, Copy, Clone)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum InputSignal {
            U0RXD               = 6,
            U0CTS               = 7,
            U0DSR               = 8,
            U1RXD               = 9,
            U1CTS               = 10,
            U1DSR               = 11,
            I2S_MCLK            = 12,
            I2SO_BCK            = 13,
            I2SO_WS             = 14,
            I2SI_SD             = 15,
            I2SI_BCK            = 16,
            I2SI_WS             = 17,
            CPU_GPIO_0          = 27,
            CPU_GPIO_1          = 28,
            CPU_GPIO_2          = 29,
            CPU_GPIO_3          = 30,
            CPU_GPIO_4          = 31,
            CPU_GPIO_5          = 32,
            CPU_GPIO_6          = 33,
            CPU_GPIO_7          = 34,
            USB_JTAG_TDO_BRIDGE = 35,
            I2CEXT0_SCL         = 46,
            I2CEXT0_SDA         = 47,
            FSPICLK             = 64,
            FSPIQ               = 65,
            FSPID               = 66,
            FSPIHD              = 67,
            FSPIWP              = 68,
            FSPICS0             = 69,
            U2RXD               = 72,
            U2CTS               = 73,
            U2DSR               = 74,
            SIG_IN_FUNC97       = 97,
            SIG_IN_FUNC98       = 98,
            SIG_IN_FUNC99       = 99,
            SIG_IN_FUNC100      = 100,
            SDIO_CLK,
            SDIO_CMD,
            SDIO_DATA0,
            SDIO_DATA1,
            SDIO_DATA2,
            SDIO_DATA3,
            MTDI,
            MTDO,
            MTCK,
            MTMS,
        }
        #[allow(non_camel_case_types, clippy::upper_case_acronyms)]
        #[derive(Debug, PartialEq, Copy, Clone)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum OutputSignal {
            LEDC_LS_SIG0    = 0,
            LEDC_LS_SIG1    = 1,
            LEDC_LS_SIG2    = 2,
            LEDC_LS_SIG3    = 3,
            LEDC_LS_SIG4    = 4,
            LEDC_LS_SIG5    = 5,
            U0TXD           = 6,
            U0RTS           = 7,
            U0DTR           = 8,
            U1TXD           = 9,
            U1RTS           = 10,
            U1DTR           = 11,
            I2S_MCLK        = 12,
            I2SO_BCK        = 13,
            I2SO_WS         = 14,
            I2SO_SD         = 15,
            I2SI_BCK        = 16,
            I2SI_WS         = 17,
            I2SO_SD1        = 18,
            CPU_GPIO_0      = 27,
            CPU_GPIO_1      = 28,
            CPU_GPIO_2      = 29,
            CPU_GPIO_3      = 30,
            CPU_GPIO_4      = 31,
            CPU_GPIO_5      = 32,
            CPU_GPIO_6      = 33,
            CPU_GPIO_7      = 34,
            I2CEXT0_SCL     = 46,
            I2CEXT0_SDA     = 47,
            FSPICLK         = 64,
            FSPIQ           = 65,
            FSPID           = 66,
            FSPIHD          = 67,
            FSPIWP          = 68,
            FSPICS0         = 69,
            U2TXD           = 72,
            U2RTS           = 73,
            U2DTR           = 74,
            FSPICS1         = 102,
            FSPICS2         = 103,
            FSPICS3         = 104,
            FSPICS4         = 105,
            FSPICS5         = 106,
            SDIO_TOHOST_INT = 124,
            GPIO            = 256,
        }
    };
}
/// Defines the `LpFunction` enum.
///
/// The enum only contains the LP IO MUX functions that the chip implements. It is
/// empty on chips without an LP IO peripheral.
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_lp_functions {
    () => {
        /// LP IO MUX function of a pad.
        ///
        /// This is the low-power counterpart of `AlternateFunction`: it selects which function
        /// drives a pad while the pad belongs to the low-power domain.
        #[derive(Debug, Eq, PartialEq, Copy, Clone, Hash)]
        #[cfg_attr(feature = "defmt", derive(defmt::Format))]
        #[doc(hidden)]
        pub enum LpFunction {
            /// LP IO MUX function 1.
            _1 = 1,
        }
        impl LpFunction {
            /// The function that connects the pad to the LP GPIO peripheral.
            pub const LP_GPIO: Self = Self::_1;
        }
    };
}
/// Defines and implements the `io_mux_reg` function.
///
/// The generated function has the following signature:
///
/// ```rust,ignore
/// pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO0 {
///     // ...
/// # unimplemented!()
/// }
/// ```
///
/// This macro is intended to be called in esp-hal only.
#[macro_export]
#[expect(clippy::crate_in_macro_def)]
#[cfg_attr(docsrs, doc(cfg(feature = "_device-selected")))]
macro_rules! define_io_mux_reg {
    () => {
        pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static crate::pac::io_mux::GPIO {
            crate::peripherals::IO_MUX::regs().gpio(gpio_num as usize)
        }
    };
}